setup.c 17 KB

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  1. /*
  2. * arch/xtensa/kernel/setup.c
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 1995 Linus Torvalds
  9. * Copyright (C) 2001 - 2005 Tensilica Inc.
  10. * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
  11. *
  12. * Chris Zankel <chris@zankel.net>
  13. * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
  14. * Kevin Chea
  15. * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
  16. */
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/mm.h>
  20. #include <linux/proc_fs.h>
  21. #include <linux/screen_info.h>
  22. #include <linux/kernel.h>
  23. #include <linux/percpu.h>
  24. #include <linux/cpu.h>
  25. #include <linux/of.h>
  26. #include <linux/of_fdt.h>
  27. #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  28. # include <linux/console.h>
  29. #endif
  30. #ifdef CONFIG_PROC_FS
  31. # include <linux/seq_file.h>
  32. #endif
  33. #include <asm/bootparam.h>
  34. #include <asm/kasan.h>
  35. #include <asm/mmu_context.h>
  36. #include <asm/processor.h>
  37. #include <asm/timex.h>
  38. #include <asm/platform.h>
  39. #include <asm/page.h>
  40. #include <asm/setup.h>
  41. #include <asm/param.h>
  42. #include <asm/smp.h>
  43. #include <asm/sysmem.h>
  44. #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  45. struct screen_info screen_info = {
  46. .orig_x = 0,
  47. .orig_y = 24,
  48. .orig_video_cols = 80,
  49. .orig_video_lines = 24,
  50. .orig_video_isVGA = 1,
  51. .orig_video_points = 16,
  52. };
  53. #endif
  54. #ifdef CONFIG_BLK_DEV_INITRD
  55. extern unsigned long initrd_start;
  56. extern unsigned long initrd_end;
  57. extern int initrd_below_start_ok;
  58. #endif
  59. #ifdef CONFIG_USE_OF
  60. void *dtb_start = __dtb_start;
  61. #endif
  62. extern unsigned long loops_per_jiffy;
  63. /* Command line specified as configuration option. */
  64. static char __initdata command_line[COMMAND_LINE_SIZE];
  65. #ifdef CONFIG_CMDLINE_BOOL
  66. static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
  67. #endif
  68. #ifdef CONFIG_PARSE_BOOTPARAM
  69. /*
  70. * Boot parameter parsing.
  71. *
  72. * The Xtensa port uses a list of variable-sized tags to pass data to
  73. * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
  74. * to be recognised. The list is terminated with a zero-sized
  75. * BP_TAG_LAST tag.
  76. */
  77. typedef struct tagtable {
  78. u32 tag;
  79. int (*parse)(const bp_tag_t*);
  80. } tagtable_t;
  81. #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
  82. __section(".taglist") __attribute__((used)) = { tag, fn }
  83. /* parse current tag */
  84. static int __init parse_tag_mem(const bp_tag_t *tag)
  85. {
  86. struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
  87. if (mi->type != MEMORY_TYPE_CONVENTIONAL)
  88. return -1;
  89. return memblock_add(mi->start, mi->end - mi->start);
  90. }
  91. __tagtable(BP_TAG_MEMORY, parse_tag_mem);
  92. #ifdef CONFIG_BLK_DEV_INITRD
  93. static int __init parse_tag_initrd(const bp_tag_t* tag)
  94. {
  95. struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
  96. initrd_start = (unsigned long)__va(mi->start);
  97. initrd_end = (unsigned long)__va(mi->end);
  98. return 0;
  99. }
  100. __tagtable(BP_TAG_INITRD, parse_tag_initrd);
  101. #endif /* CONFIG_BLK_DEV_INITRD */
  102. #ifdef CONFIG_USE_OF
  103. static int __init parse_tag_fdt(const bp_tag_t *tag)
  104. {
  105. dtb_start = __va(tag->data[0]);
  106. return 0;
  107. }
  108. __tagtable(BP_TAG_FDT, parse_tag_fdt);
  109. #endif /* CONFIG_USE_OF */
  110. static int __init parse_tag_cmdline(const bp_tag_t* tag)
  111. {
  112. strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
  113. return 0;
  114. }
  115. __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
  116. static int __init parse_bootparam(const bp_tag_t* tag)
  117. {
  118. extern tagtable_t __tagtable_begin, __tagtable_end;
  119. tagtable_t *t;
  120. /* Boot parameters must start with a BP_TAG_FIRST tag. */
  121. if (tag->id != BP_TAG_FIRST) {
  122. pr_warn("Invalid boot parameters!\n");
  123. return 0;
  124. }
  125. tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
  126. /* Parse all tags. */
  127. while (tag != NULL && tag->id != BP_TAG_LAST) {
  128. for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
  129. if (tag->id == t->tag) {
  130. t->parse(tag);
  131. break;
  132. }
  133. }
  134. if (t == &__tagtable_end)
  135. pr_warn("Ignoring tag 0x%08x\n", tag->id);
  136. tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
  137. }
  138. return 0;
  139. }
  140. #else
  141. static int __init parse_bootparam(const bp_tag_t *tag)
  142. {
  143. pr_info("Ignoring boot parameters at %p\n", tag);
  144. return 0;
  145. }
  146. #endif
  147. #ifdef CONFIG_USE_OF
  148. #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
  149. unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
  150. EXPORT_SYMBOL(xtensa_kio_paddr);
  151. static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
  152. int depth, void *data)
  153. {
  154. const __be32 *ranges;
  155. int len;
  156. if (depth > 1)
  157. return 0;
  158. if (!of_flat_dt_is_compatible(node, "simple-bus"))
  159. return 0;
  160. ranges = of_get_flat_dt_prop(node, "ranges", &len);
  161. if (!ranges)
  162. return 1;
  163. if (len == 0)
  164. return 1;
  165. xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
  166. /* round down to nearest 256MB boundary */
  167. xtensa_kio_paddr &= 0xf0000000;
  168. init_kio();
  169. return 1;
  170. }
  171. #else
  172. static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
  173. int depth, void *data)
  174. {
  175. return 1;
  176. }
  177. #endif
  178. void __init early_init_devtree(void *params)
  179. {
  180. early_init_dt_scan(params);
  181. of_scan_flat_dt(xtensa_dt_io_area, NULL);
  182. if (!command_line[0])
  183. strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
  184. }
  185. #endif /* CONFIG_USE_OF */
  186. /*
  187. * Initialize architecture. (Early stage)
  188. */
  189. void __init init_arch(bp_tag_t *bp_start)
  190. {
  191. /* Initialize MMU. */
  192. init_mmu();
  193. /* Initialize initial KASAN shadow map */
  194. kasan_early_init();
  195. /* Parse boot parameters */
  196. if (bp_start)
  197. parse_bootparam(bp_start);
  198. #ifdef CONFIG_USE_OF
  199. early_init_devtree(dtb_start);
  200. #endif
  201. #ifdef CONFIG_CMDLINE_BOOL
  202. if (!command_line[0])
  203. strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
  204. #endif
  205. /* Early hook for platforms */
  206. platform_init(bp_start);
  207. }
  208. /*
  209. * Initialize system. Setup memory and reserve regions.
  210. */
  211. extern char _end[];
  212. extern char _stext[];
  213. extern char _WindowVectors_text_start;
  214. extern char _WindowVectors_text_end;
  215. extern char _DebugInterruptVector_text_start;
  216. extern char _DebugInterruptVector_text_end;
  217. extern char _KernelExceptionVector_text_start;
  218. extern char _KernelExceptionVector_text_end;
  219. extern char _UserExceptionVector_text_start;
  220. extern char _UserExceptionVector_text_end;
  221. extern char _DoubleExceptionVector_text_start;
  222. extern char _DoubleExceptionVector_text_end;
  223. extern char _exception_text_start;
  224. extern char _exception_text_end;
  225. #if XCHAL_EXCM_LEVEL >= 2
  226. extern char _Level2InterruptVector_text_start;
  227. extern char _Level2InterruptVector_text_end;
  228. #endif
  229. #if XCHAL_EXCM_LEVEL >= 3
  230. extern char _Level3InterruptVector_text_start;
  231. extern char _Level3InterruptVector_text_end;
  232. #endif
  233. #if XCHAL_EXCM_LEVEL >= 4
  234. extern char _Level4InterruptVector_text_start;
  235. extern char _Level4InterruptVector_text_end;
  236. #endif
  237. #if XCHAL_EXCM_LEVEL >= 5
  238. extern char _Level5InterruptVector_text_start;
  239. extern char _Level5InterruptVector_text_end;
  240. #endif
  241. #if XCHAL_EXCM_LEVEL >= 6
  242. extern char _Level6InterruptVector_text_start;
  243. extern char _Level6InterruptVector_text_end;
  244. #endif
  245. #ifdef CONFIG_SMP
  246. extern char _SecondaryResetVector_text_start;
  247. extern char _SecondaryResetVector_text_end;
  248. #endif
  249. #ifdef CONFIG_XIP_KERNEL
  250. extern char _xip_start[];
  251. extern char _xip_end[];
  252. #endif
  253. static inline int __init_memblock mem_reserve(unsigned long start,
  254. unsigned long end)
  255. {
  256. return memblock_reserve(start, end - start);
  257. }
  258. void __init setup_arch(char **cmdline_p)
  259. {
  260. pr_info("config ID: %08x:%08x\n",
  261. xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
  262. if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
  263. xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
  264. pr_info("built for config ID: %08x:%08x\n",
  265. XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
  266. *cmdline_p = command_line;
  267. platform_setup(cmdline_p);
  268. strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
  269. /* Reserve some memory regions */
  270. #ifdef CONFIG_BLK_DEV_INITRD
  271. if (initrd_start < initrd_end &&
  272. !mem_reserve(__pa(initrd_start), __pa(initrd_end)))
  273. initrd_below_start_ok = 1;
  274. else
  275. initrd_start = 0;
  276. #endif
  277. mem_reserve(__pa(_stext), __pa(_end));
  278. #ifdef CONFIG_XIP_KERNEL
  279. mem_reserve(__pa(_xip_start), __pa(_xip_end));
  280. #endif
  281. #ifdef CONFIG_VECTORS_ADDR
  282. mem_reserve(__pa(&_WindowVectors_text_start),
  283. __pa(&_WindowVectors_text_end));
  284. mem_reserve(__pa(&_DebugInterruptVector_text_start),
  285. __pa(&_DebugInterruptVector_text_end));
  286. mem_reserve(__pa(&_KernelExceptionVector_text_start),
  287. __pa(&_KernelExceptionVector_text_end));
  288. mem_reserve(__pa(&_UserExceptionVector_text_start),
  289. __pa(&_UserExceptionVector_text_end));
  290. mem_reserve(__pa(&_DoubleExceptionVector_text_start),
  291. __pa(&_DoubleExceptionVector_text_end));
  292. mem_reserve(__pa(&_exception_text_start),
  293. __pa(&_exception_text_end));
  294. #if XCHAL_EXCM_LEVEL >= 2
  295. mem_reserve(__pa(&_Level2InterruptVector_text_start),
  296. __pa(&_Level2InterruptVector_text_end));
  297. #endif
  298. #if XCHAL_EXCM_LEVEL >= 3
  299. mem_reserve(__pa(&_Level3InterruptVector_text_start),
  300. __pa(&_Level3InterruptVector_text_end));
  301. #endif
  302. #if XCHAL_EXCM_LEVEL >= 4
  303. mem_reserve(__pa(&_Level4InterruptVector_text_start),
  304. __pa(&_Level4InterruptVector_text_end));
  305. #endif
  306. #if XCHAL_EXCM_LEVEL >= 5
  307. mem_reserve(__pa(&_Level5InterruptVector_text_start),
  308. __pa(&_Level5InterruptVector_text_end));
  309. #endif
  310. #if XCHAL_EXCM_LEVEL >= 6
  311. mem_reserve(__pa(&_Level6InterruptVector_text_start),
  312. __pa(&_Level6InterruptVector_text_end));
  313. #endif
  314. #endif /* CONFIG_VECTORS_ADDR */
  315. #ifdef CONFIG_SMP
  316. mem_reserve(__pa(&_SecondaryResetVector_text_start),
  317. __pa(&_SecondaryResetVector_text_end));
  318. #endif
  319. parse_early_param();
  320. bootmem_init();
  321. kasan_init();
  322. unflatten_and_copy_device_tree();
  323. #ifdef CONFIG_SMP
  324. smp_init_cpus();
  325. #endif
  326. paging_init();
  327. zones_init();
  328. #ifdef CONFIG_VT
  329. # if defined(CONFIG_VGA_CONSOLE)
  330. conswitchp = &vga_con;
  331. # endif
  332. #endif
  333. }
  334. static DEFINE_PER_CPU(struct cpu, cpu_data);
  335. static int __init topology_init(void)
  336. {
  337. int i;
  338. for_each_possible_cpu(i) {
  339. struct cpu *cpu = &per_cpu(cpu_data, i);
  340. cpu->hotpluggable = !!i;
  341. register_cpu(cpu, i);
  342. }
  343. return 0;
  344. }
  345. subsys_initcall(topology_init);
  346. void cpu_reset(void)
  347. {
  348. #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
  349. local_irq_disable();
  350. /*
  351. * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
  352. * be flushed.
  353. * Way 4 is not currently used by linux.
  354. * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
  355. * Way 5 shall be flushed and way 6 shall be set to identity mapping
  356. * on MMUv3.
  357. */
  358. local_flush_tlb_all();
  359. invalidate_page_directory();
  360. #if XCHAL_HAVE_SPANNING_WAY
  361. /* MMU v3 */
  362. {
  363. unsigned long vaddr = (unsigned long)cpu_reset;
  364. unsigned long paddr = __pa(vaddr);
  365. unsigned long tmpaddr = vaddr + SZ_512M;
  366. unsigned long tmp0, tmp1, tmp2, tmp3;
  367. /*
  368. * Find a place for the temporary mapping. It must not be
  369. * in the same 512MB region with vaddr or paddr, otherwise
  370. * there may be multihit exception either on entry to the
  371. * temporary mapping, or on entry to the identity mapping.
  372. * (512MB is the biggest page size supported by TLB.)
  373. */
  374. while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
  375. tmpaddr += SZ_512M;
  376. /* Invalidate mapping in the selected temporary area */
  377. if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
  378. invalidate_itlb_entry(itlb_probe(tmpaddr));
  379. if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
  380. invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
  381. /*
  382. * Map two consecutive pages starting at the physical address
  383. * of this function to the temporary mapping area.
  384. */
  385. write_itlb_entry(__pte((paddr & PAGE_MASK) |
  386. _PAGE_HW_VALID |
  387. _PAGE_HW_EXEC |
  388. _PAGE_CA_BYPASS),
  389. tmpaddr & PAGE_MASK);
  390. write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
  391. _PAGE_HW_VALID |
  392. _PAGE_HW_EXEC |
  393. _PAGE_CA_BYPASS),
  394. (tmpaddr & PAGE_MASK) + PAGE_SIZE);
  395. /* Reinitialize TLB */
  396. __asm__ __volatile__ ("movi %0, 1f\n\t"
  397. "movi %3, 2f\n\t"
  398. "add %0, %0, %4\n\t"
  399. "add %3, %3, %5\n\t"
  400. "jx %0\n"
  401. /*
  402. * No literal, data or stack access
  403. * below this point
  404. */
  405. "1:\n\t"
  406. /* Initialize *tlbcfg */
  407. "movi %0, 0\n\t"
  408. "wsr %0, itlbcfg\n\t"
  409. "wsr %0, dtlbcfg\n\t"
  410. /* Invalidate TLB way 5 */
  411. "movi %0, 4\n\t"
  412. "movi %1, 5\n"
  413. "1:\n\t"
  414. "iitlb %1\n\t"
  415. "idtlb %1\n\t"
  416. "add %1, %1, %6\n\t"
  417. "addi %0, %0, -1\n\t"
  418. "bnez %0, 1b\n\t"
  419. /* Initialize TLB way 6 */
  420. "movi %0, 7\n\t"
  421. "addi %1, %9, 3\n\t"
  422. "addi %2, %9, 6\n"
  423. "1:\n\t"
  424. "witlb %1, %2\n\t"
  425. "wdtlb %1, %2\n\t"
  426. "add %1, %1, %7\n\t"
  427. "add %2, %2, %7\n\t"
  428. "addi %0, %0, -1\n\t"
  429. "bnez %0, 1b\n\t"
  430. "isync\n\t"
  431. /* Jump to identity mapping */
  432. "jx %3\n"
  433. "2:\n\t"
  434. /* Complete way 6 initialization */
  435. "witlb %1, %2\n\t"
  436. "wdtlb %1, %2\n\t"
  437. /* Invalidate temporary mapping */
  438. "sub %0, %9, %7\n\t"
  439. "iitlb %0\n\t"
  440. "add %0, %0, %8\n\t"
  441. "iitlb %0"
  442. : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
  443. "=&a"(tmp3)
  444. : "a"(tmpaddr - vaddr),
  445. "a"(paddr - vaddr),
  446. "a"(SZ_128M), "a"(SZ_512M),
  447. "a"(PAGE_SIZE),
  448. "a"((tmpaddr + SZ_512M) & PAGE_MASK)
  449. : "memory");
  450. }
  451. #endif
  452. #endif
  453. __asm__ __volatile__ ("movi a2, 0\n\t"
  454. "wsr a2, icountlevel\n\t"
  455. "movi a2, 0\n\t"
  456. "wsr a2, icount\n\t"
  457. #if XCHAL_NUM_IBREAK > 0
  458. "wsr a2, ibreakenable\n\t"
  459. #endif
  460. #if XCHAL_HAVE_LOOPS
  461. "wsr a2, lcount\n\t"
  462. #endif
  463. "movi a2, 0x1f\n\t"
  464. "wsr a2, ps\n\t"
  465. "isync\n\t"
  466. "jx %0\n\t"
  467. :
  468. : "a" (XCHAL_RESET_VECTOR_VADDR)
  469. : "a2");
  470. for (;;)
  471. ;
  472. }
  473. void machine_restart(char * cmd)
  474. {
  475. platform_restart();
  476. }
  477. void machine_halt(void)
  478. {
  479. platform_halt();
  480. while (1);
  481. }
  482. void machine_power_off(void)
  483. {
  484. platform_power_off();
  485. while (1);
  486. }
  487. #ifdef CONFIG_PROC_FS
  488. /*
  489. * Display some core information through /proc/cpuinfo.
  490. */
  491. static int
  492. c_show(struct seq_file *f, void *slot)
  493. {
  494. /* high-level stuff */
  495. seq_printf(f, "CPU count\t: %u\n"
  496. "CPU list\t: %*pbl\n"
  497. "vendor_id\t: Tensilica\n"
  498. "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
  499. "core ID\t\t: " XCHAL_CORE_ID "\n"
  500. "build ID\t: 0x%x\n"
  501. "config ID\t: %08x:%08x\n"
  502. "byte order\t: %s\n"
  503. "cpu MHz\t\t: %lu.%02lu\n"
  504. "bogomips\t: %lu.%02lu\n",
  505. num_online_cpus(),
  506. cpumask_pr_args(cpu_online_mask),
  507. XCHAL_BUILD_UNIQUE_ID,
  508. xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
  509. XCHAL_HAVE_BE ? "big" : "little",
  510. ccount_freq/1000000,
  511. (ccount_freq/10000) % 100,
  512. loops_per_jiffy/(500000/HZ),
  513. (loops_per_jiffy/(5000/HZ)) % 100);
  514. seq_puts(f, "flags\t\t: "
  515. #if XCHAL_HAVE_NMI
  516. "nmi "
  517. #endif
  518. #if XCHAL_HAVE_DEBUG
  519. "debug "
  520. # if XCHAL_HAVE_OCD
  521. "ocd "
  522. # endif
  523. #endif
  524. #if XCHAL_HAVE_DENSITY
  525. "density "
  526. #endif
  527. #if XCHAL_HAVE_BOOLEANS
  528. "boolean "
  529. #endif
  530. #if XCHAL_HAVE_LOOPS
  531. "loop "
  532. #endif
  533. #if XCHAL_HAVE_NSA
  534. "nsa "
  535. #endif
  536. #if XCHAL_HAVE_MINMAX
  537. "minmax "
  538. #endif
  539. #if XCHAL_HAVE_SEXT
  540. "sext "
  541. #endif
  542. #if XCHAL_HAVE_CLAMPS
  543. "clamps "
  544. #endif
  545. #if XCHAL_HAVE_MAC16
  546. "mac16 "
  547. #endif
  548. #if XCHAL_HAVE_MUL16
  549. "mul16 "
  550. #endif
  551. #if XCHAL_HAVE_MUL32
  552. "mul32 "
  553. #endif
  554. #if XCHAL_HAVE_MUL32_HIGH
  555. "mul32h "
  556. #endif
  557. #if XCHAL_HAVE_FP
  558. "fpu "
  559. #endif
  560. #if XCHAL_HAVE_S32C1I
  561. "s32c1i "
  562. #endif
  563. #if XCHAL_HAVE_EXCLUSIVE
  564. "exclusive "
  565. #endif
  566. "\n");
  567. /* Registers. */
  568. seq_printf(f,"physical aregs\t: %d\n"
  569. "misc regs\t: %d\n"
  570. "ibreak\t\t: %d\n"
  571. "dbreak\t\t: %d\n",
  572. XCHAL_NUM_AREGS,
  573. XCHAL_NUM_MISC_REGS,
  574. XCHAL_NUM_IBREAK,
  575. XCHAL_NUM_DBREAK);
  576. /* Interrupt. */
  577. seq_printf(f,"num ints\t: %d\n"
  578. "ext ints\t: %d\n"
  579. "int levels\t: %d\n"
  580. "timers\t\t: %d\n"
  581. "debug level\t: %d\n",
  582. XCHAL_NUM_INTERRUPTS,
  583. XCHAL_NUM_EXTINTERRUPTS,
  584. XCHAL_NUM_INTLEVELS,
  585. XCHAL_NUM_TIMERS,
  586. XCHAL_DEBUGLEVEL);
  587. /* Cache */
  588. seq_printf(f,"icache line size: %d\n"
  589. "icache ways\t: %d\n"
  590. "icache size\t: %d\n"
  591. "icache flags\t: "
  592. #if XCHAL_ICACHE_LINE_LOCKABLE
  593. "lock "
  594. #endif
  595. "\n"
  596. "dcache line size: %d\n"
  597. "dcache ways\t: %d\n"
  598. "dcache size\t: %d\n"
  599. "dcache flags\t: "
  600. #if XCHAL_DCACHE_IS_WRITEBACK
  601. "writeback "
  602. #endif
  603. #if XCHAL_DCACHE_LINE_LOCKABLE
  604. "lock "
  605. #endif
  606. "\n",
  607. XCHAL_ICACHE_LINESIZE,
  608. XCHAL_ICACHE_WAYS,
  609. XCHAL_ICACHE_SIZE,
  610. XCHAL_DCACHE_LINESIZE,
  611. XCHAL_DCACHE_WAYS,
  612. XCHAL_DCACHE_SIZE);
  613. return 0;
  614. }
  615. /*
  616. * We show only CPU #0 info.
  617. */
  618. static void *
  619. c_start(struct seq_file *f, loff_t *pos)
  620. {
  621. return (*pos == 0) ? (void *)1 : NULL;
  622. }
  623. static void *
  624. c_next(struct seq_file *f, void *v, loff_t *pos)
  625. {
  626. ++*pos;
  627. return c_start(f, pos);
  628. }
  629. static void
  630. c_stop(struct seq_file *f, void *v)
  631. {
  632. }
  633. const struct seq_operations cpuinfo_op =
  634. {
  635. .start = c_start,
  636. .next = c_next,
  637. .stop = c_stop,
  638. .show = c_show,
  639. };
  640. #endif /* CONFIG_PROC_FS */