pci-dma.c 2.1 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DMA coherent memory allocation.
  4. *
  5. * Copyright (C) 2002 - 2005 Tensilica Inc.
  6. * Copyright (C) 2015 Cadence Design Systems Inc.
  7. *
  8. * Based on version for i386.
  9. *
  10. * Chris Zankel <chris@zankel.net>
  11. * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
  12. */
  13. #include <linux/dma-map-ops.h>
  14. #include <linux/dma-direct.h>
  15. #include <linux/gfp.h>
  16. #include <linux/highmem.h>
  17. #include <linux/mm.h>
  18. #include <linux/types.h>
  19. #include <asm/cacheflush.h>
  20. #include <asm/io.h>
  21. #include <asm/platform.h>
  22. static void do_cache_op(phys_addr_t paddr, size_t size,
  23. void (*fn)(unsigned long, unsigned long))
  24. {
  25. unsigned long off = paddr & (PAGE_SIZE - 1);
  26. unsigned long pfn = PFN_DOWN(paddr);
  27. struct page *page = pfn_to_page(pfn);
  28. if (!PageHighMem(page))
  29. fn((unsigned long)phys_to_virt(paddr), size);
  30. else
  31. while (size > 0) {
  32. size_t sz = min_t(size_t, size, PAGE_SIZE - off);
  33. void *vaddr = kmap_atomic(page);
  34. fn((unsigned long)vaddr + off, sz);
  35. kunmap_atomic(vaddr);
  36. off = 0;
  37. ++page;
  38. size -= sz;
  39. }
  40. }
  41. void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
  42. enum dma_data_direction dir)
  43. {
  44. switch (dir) {
  45. case DMA_BIDIRECTIONAL:
  46. case DMA_FROM_DEVICE:
  47. do_cache_op(paddr, size, __invalidate_dcache_range);
  48. break;
  49. case DMA_NONE:
  50. BUG();
  51. break;
  52. default:
  53. break;
  54. }
  55. }
  56. void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
  57. enum dma_data_direction dir)
  58. {
  59. switch (dir) {
  60. case DMA_BIDIRECTIONAL:
  61. case DMA_TO_DEVICE:
  62. if (XCHAL_DCACHE_IS_WRITEBACK)
  63. do_cache_op(paddr, size, __flush_dcache_range);
  64. break;
  65. case DMA_NONE:
  66. BUG();
  67. break;
  68. default:
  69. break;
  70. }
  71. }
  72. void arch_dma_prep_coherent(struct page *page, size_t size)
  73. {
  74. __invalidate_dcache_range((unsigned long)page_address(page), size);
  75. }
  76. /*
  77. * Memory caching is platform-dependent in noMMU xtensa configurations.
  78. * This function should be implemented in platform code in order to enable
  79. * coherent DMA memory operations when CONFIG_MMU is not enabled.
  80. */
  81. #ifdef CONFIG_MMU
  82. void *arch_dma_set_uncached(void *p, size_t size)
  83. {
  84. return p + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR;
  85. }
  86. #endif /* CONFIG_MMU */