irq.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/xtensa/kernel/irq.c
  4. *
  5. * Xtensa built-in interrupt controller and some generic functions copied
  6. * from i386.
  7. *
  8. * Copyright (C) 2002 - 2013 Tensilica, Inc.
  9. * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
  10. *
  11. *
  12. * Chris Zankel <chris@zankel.net>
  13. * Kevin Chea
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/seq_file.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/irq.h>
  20. #include <linux/kernel_stat.h>
  21. #include <linux/irqchip.h>
  22. #include <linux/irqchip/xtensa-mx.h>
  23. #include <linux/irqchip/xtensa-pic.h>
  24. #include <linux/irqdomain.h>
  25. #include <linux/of.h>
  26. #include <asm/mxregs.h>
  27. #include <linux/uaccess.h>
  28. #include <asm/platform.h>
  29. DECLARE_PER_CPU(unsigned long, nmi_count);
  30. asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
  31. {
  32. int irq = irq_find_mapping(NULL, hwirq);
  33. #ifdef CONFIG_DEBUG_STACKOVERFLOW
  34. /* Debugging check for stack overflow: is there less than 1KB free? */
  35. {
  36. unsigned long sp;
  37. __asm__ __volatile__ ("mov %0, a1\n" : "=a" (sp));
  38. sp &= THREAD_SIZE - 1;
  39. if (unlikely(sp < (sizeof(thread_info) + 1024)))
  40. printk("Stack overflow in do_IRQ: %ld\n",
  41. sp - sizeof(struct thread_info));
  42. }
  43. #endif
  44. generic_handle_irq(irq);
  45. }
  46. int arch_show_interrupts(struct seq_file *p, int prec)
  47. {
  48. unsigned cpu __maybe_unused;
  49. #ifdef CONFIG_SMP
  50. show_ipi_list(p, prec);
  51. #endif
  52. #if XTENSA_FAKE_NMI
  53. seq_printf(p, "%*s:", prec, "NMI");
  54. for_each_online_cpu(cpu)
  55. seq_printf(p, " %10lu", per_cpu(nmi_count, cpu));
  56. seq_puts(p, " Non-maskable interrupts\n");
  57. #endif
  58. return 0;
  59. }
  60. int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize,
  61. unsigned long int_irq, unsigned long ext_irq,
  62. unsigned long *out_hwirq, unsigned int *out_type)
  63. {
  64. if (WARN_ON(intsize < 1 || intsize > 2))
  65. return -EINVAL;
  66. if (intsize == 2 && intspec[1] == 1) {
  67. int_irq = xtensa_map_ext_irq(ext_irq);
  68. if (int_irq < XCHAL_NUM_INTERRUPTS)
  69. *out_hwirq = int_irq;
  70. else
  71. return -EINVAL;
  72. } else {
  73. *out_hwirq = int_irq;
  74. }
  75. *out_type = IRQ_TYPE_NONE;
  76. return 0;
  77. }
  78. int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
  79. irq_hw_number_t hw)
  80. {
  81. struct irq_chip *irq_chip = d->host_data;
  82. u32 mask = 1 << hw;
  83. if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
  84. irq_set_chip_and_handler_name(irq, irq_chip,
  85. handle_simple_irq, "level");
  86. irq_set_status_flags(irq, IRQ_LEVEL);
  87. } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
  88. irq_set_chip_and_handler_name(irq, irq_chip,
  89. handle_edge_irq, "edge");
  90. irq_clear_status_flags(irq, IRQ_LEVEL);
  91. } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
  92. irq_set_chip_and_handler_name(irq, irq_chip,
  93. handle_level_irq, "level");
  94. irq_set_status_flags(irq, IRQ_LEVEL);
  95. } else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
  96. irq_set_chip_and_handler_name(irq, irq_chip,
  97. handle_percpu_irq, "timer");
  98. irq_clear_status_flags(irq, IRQ_LEVEL);
  99. #ifdef XCHAL_INTTYPE_MASK_PROFILING
  100. } else if (mask & XCHAL_INTTYPE_MASK_PROFILING) {
  101. irq_set_chip_and_handler_name(irq, irq_chip,
  102. handle_percpu_irq, "profiling");
  103. irq_set_status_flags(irq, IRQ_LEVEL);
  104. #endif
  105. } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */
  106. /* XCHAL_INTTYPE_MASK_NMI */
  107. irq_set_chip_and_handler_name(irq, irq_chip,
  108. handle_level_irq, "level");
  109. irq_set_status_flags(irq, IRQ_LEVEL);
  110. }
  111. return 0;
  112. }
  113. unsigned xtensa_map_ext_irq(unsigned ext_irq)
  114. {
  115. unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
  116. XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
  117. unsigned i;
  118. for (i = 0; mask; ++i, mask >>= 1) {
  119. if ((mask & 1) && ext_irq-- == 0)
  120. return i;
  121. }
  122. return XCHAL_NUM_INTERRUPTS;
  123. }
  124. unsigned xtensa_get_ext_irq_no(unsigned irq)
  125. {
  126. unsigned mask = (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
  127. XCHAL_INTTYPE_MASK_EXTERN_LEVEL) &
  128. ((1u << irq) - 1);
  129. return hweight32(mask);
  130. }
  131. void __init init_IRQ(void)
  132. {
  133. #ifdef CONFIG_USE_OF
  134. irqchip_init();
  135. #else
  136. #ifdef CONFIG_HAVE_SMP
  137. xtensa_mx_init_legacy(NULL);
  138. #else
  139. xtensa_pic_init_legacy(NULL);
  140. #endif
  141. #endif
  142. #ifdef CONFIG_SMP
  143. ipi_init();
  144. #endif
  145. }
  146. #ifdef CONFIG_HOTPLUG_CPU
  147. /*
  148. * The CPU has been marked offline. Migrate IRQs off this CPU. If
  149. * the affinity settings do not allow other CPUs, force them onto any
  150. * available CPU.
  151. */
  152. void migrate_irqs(void)
  153. {
  154. unsigned int i, cpu = smp_processor_id();
  155. for_each_active_irq(i) {
  156. struct irq_data *data = irq_get_irq_data(i);
  157. struct cpumask *mask;
  158. unsigned int newcpu;
  159. if (irqd_is_per_cpu(data))
  160. continue;
  161. mask = irq_data_get_affinity_mask(data);
  162. if (!cpumask_test_cpu(cpu, mask))
  163. continue;
  164. newcpu = cpumask_any_and(mask, cpu_online_mask);
  165. if (newcpu >= nr_cpu_ids) {
  166. pr_info_ratelimited("IRQ%u no longer affine to CPU%u\n",
  167. i, cpu);
  168. cpumask_setall(mask);
  169. }
  170. irq_set_affinity(i, mask);
  171. }
  172. }
  173. #endif /* CONFIG_HOTPLUG_CPU */