head.S 6.9 KB

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  1. /*
  2. * arch/xtensa/kernel/head.S
  3. *
  4. * Xtensa Processor startup code.
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. *
  10. * Copyright (C) 2001 - 2008 Tensilica Inc.
  11. *
  12. * Chris Zankel <chris@zankel.net>
  13. * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
  14. * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
  15. * Kevin Chea
  16. */
  17. #include <asm/processor.h>
  18. #include <asm/page.h>
  19. #include <asm/cacheasm.h>
  20. #include <asm/initialize_mmu.h>
  21. #include <asm/mxregs.h>
  22. #include <linux/init.h>
  23. #include <linux/linkage.h>
  24. /*
  25. * This module contains the entry code for kernel images. It performs the
  26. * minimal setup needed to call the generic C routines.
  27. *
  28. * Prerequisites:
  29. *
  30. * - The kernel image has been loaded to the actual address where it was
  31. * compiled to.
  32. * - a2 contains either 0 or a pointer to a list of boot parameters.
  33. * (see setup.c for more details)
  34. *
  35. */
  36. /*
  37. * _start
  38. *
  39. * The bootloader passes a pointer to a list of boot parameters in a2.
  40. */
  41. /* The first bytes of the kernel image must be an instruction, so we
  42. * manually allocate and define the literal constant we need for a jx
  43. * instruction.
  44. */
  45. __HEAD
  46. .begin no-absolute-literals
  47. ENTRY(_start)
  48. /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
  49. wsr a2, excsave1
  50. _j _SetupOCD
  51. .align 4
  52. .literal_position
  53. _SetupOCD:
  54. /*
  55. * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
  56. * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
  57. * xt-gdb to single step via DEBUG exceptions received directly
  58. * by ocd.
  59. */
  60. movi a1, 1
  61. movi a0, 0
  62. wsr a1, windowstart
  63. wsr a0, windowbase
  64. rsync
  65. movi a1, LOCKLEVEL
  66. wsr a1, ps
  67. rsync
  68. .global _SetupMMU
  69. _SetupMMU:
  70. Offset = _SetupMMU - _start
  71. #ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
  72. initialize_mmu
  73. #if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
  74. rsr a2, excsave1
  75. movi a3, XCHAL_KSEG_PADDR
  76. bltu a2, a3, 1f
  77. sub a2, a2, a3
  78. movi a3, XCHAL_KSEG_SIZE
  79. bgeu a2, a3, 1f
  80. movi a3, XCHAL_KSEG_CACHED_VADDR
  81. add a2, a2, a3
  82. wsr a2, excsave1
  83. 1:
  84. #endif
  85. #endif
  86. movi a0, _startup
  87. jx a0
  88. ENDPROC(_start)
  89. .end no-absolute-literals
  90. __REF
  91. .literal_position
  92. ENTRY(_startup)
  93. /* Set a0 to 0 for the remaining initialization. */
  94. movi a0, 0
  95. #if XCHAL_HAVE_VECBASE
  96. movi a2, VECBASE_VADDR
  97. wsr a2, vecbase
  98. #endif
  99. /* Clear debugging registers. */
  100. #if XCHAL_HAVE_DEBUG
  101. #if XCHAL_NUM_IBREAK > 0
  102. wsr a0, ibreakenable
  103. #endif
  104. wsr a0, icount
  105. movi a1, 15
  106. wsr a0, icountlevel
  107. .set _index, 0
  108. .rept XCHAL_NUM_DBREAK
  109. wsr a0, SREG_DBREAKC + _index
  110. .set _index, _index + 1
  111. .endr
  112. #endif
  113. /* Clear CCOUNT (not really necessary, but nice) */
  114. wsr a0, ccount # not really necessary, but nice
  115. /* Disable zero-loops. */
  116. #if XCHAL_HAVE_LOOPS
  117. wsr a0, lcount
  118. #endif
  119. /* Disable all timers. */
  120. .set _index, 0
  121. .rept XCHAL_NUM_TIMERS
  122. wsr a0, SREG_CCOMPARE + _index
  123. .set _index, _index + 1
  124. .endr
  125. /* Interrupt initialization. */
  126. movi a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE
  127. wsr a0, intenable
  128. wsr a2, intclear
  129. /* Disable coprocessors. */
  130. #if XCHAL_HAVE_CP
  131. wsr a0, cpenable
  132. #endif
  133. /* Initialize the caches.
  134. * a2, a3 are just working registers (clobbered).
  135. */
  136. #if XCHAL_DCACHE_LINE_LOCKABLE
  137. ___unlock_dcache_all a2 a3
  138. #endif
  139. #if XCHAL_ICACHE_LINE_LOCKABLE
  140. ___unlock_icache_all a2 a3
  141. #endif
  142. ___invalidate_dcache_all a2 a3
  143. ___invalidate_icache_all a2 a3
  144. isync
  145. initialize_cacheattr
  146. #ifdef CONFIG_HAVE_SMP
  147. movi a2, CCON # MX External Register to Configure Cache
  148. movi a3, 1
  149. wer a3, a2
  150. #endif
  151. /* Setup stack and enable window exceptions (keep irqs disabled) */
  152. movi a1, start_info
  153. l32i a1, a1, 0
  154. movi a2, PS_WOE_MASK | LOCKLEVEL
  155. # WOE=1, INTLEVEL=LOCKLEVEL, UM=0
  156. wsr a2, ps # (enable reg-windows; progmode stack)
  157. rsync
  158. #ifdef CONFIG_SMP
  159. /*
  160. * Notice that we assume with SMP that cores have PRID
  161. * supported by the cores.
  162. */
  163. rsr a2, prid
  164. bnez a2, .Lboot_secondary
  165. #endif /* CONFIG_SMP */
  166. /* Unpack data sections
  167. *
  168. * The linker script used to build the Linux kernel image
  169. * creates a table located at __boot_reloc_table_start
  170. * that contans the information what data needs to be unpacked.
  171. *
  172. * Uses a2-a7.
  173. */
  174. movi a2, __boot_reloc_table_start
  175. movi a3, __boot_reloc_table_end
  176. 1: beq a2, a3, 3f # no more entries?
  177. l32i a4, a2, 0 # start destination (in RAM)
  178. l32i a5, a2, 4 # end desination (in RAM)
  179. l32i a6, a2, 8 # start source (in ROM)
  180. addi a2, a2, 12 # next entry
  181. beq a4, a5, 1b # skip, empty entry
  182. beq a4, a6, 1b # skip, source and dest. are the same
  183. 2: l32i a7, a6, 0 # load word
  184. addi a6, a6, 4
  185. s32i a7, a4, 0 # store word
  186. addi a4, a4, 4
  187. bltu a4, a5, 2b
  188. j 1b
  189. 3:
  190. /* All code and initialized data segments have been copied.
  191. * Now clear the BSS segment.
  192. */
  193. movi a2, __bss_start # start of BSS
  194. movi a3, __bss_stop # end of BSS
  195. __loopt a2, a3, a4, 2
  196. s32i a0, a2, 0
  197. __endla a2, a3, 4
  198. #if XCHAL_DCACHE_IS_WRITEBACK
  199. /* After unpacking, flush the writeback cache to memory so the
  200. * instructions/data are available.
  201. */
  202. ___flush_dcache_all a2 a3
  203. #endif
  204. memw
  205. isync
  206. ___invalidate_icache_all a2 a3
  207. isync
  208. #ifdef CONFIG_XIP_KERNEL
  209. /* Setup bootstrap CPU stack in XIP kernel */
  210. movi a1, start_info
  211. l32i a1, a1, 0
  212. #endif
  213. movi a6, 0
  214. xsr a6, excsave1
  215. /* init_arch kick-starts the linux kernel */
  216. call4 init_arch
  217. call4 start_kernel
  218. should_never_return:
  219. j should_never_return
  220. #ifdef CONFIG_SMP
  221. .Lboot_secondary:
  222. movi a2, cpu_start_ccount
  223. 1:
  224. memw
  225. l32i a3, a2, 0
  226. beqi a3, 0, 1b
  227. movi a3, 0
  228. s32i a3, a2, 0
  229. 1:
  230. memw
  231. l32i a3, a2, 0
  232. beqi a3, 0, 1b
  233. wsr a3, ccount
  234. movi a3, 0
  235. s32i a3, a2, 0
  236. memw
  237. movi a6, 0
  238. wsr a6, excsave1
  239. call4 secondary_start_kernel
  240. j should_never_return
  241. #endif /* CONFIG_SMP */
  242. ENDPROC(_startup)
  243. #ifdef CONFIG_HOTPLUG_CPU
  244. ENTRY(cpu_restart)
  245. #if XCHAL_DCACHE_IS_WRITEBACK
  246. ___flush_invalidate_dcache_all a2 a3
  247. #else
  248. ___invalidate_dcache_all a2 a3
  249. #endif
  250. memw
  251. movi a2, CCON # MX External Register to Configure Cache
  252. movi a3, 0
  253. wer a3, a2
  254. extw
  255. rsr a0, prid
  256. neg a2, a0
  257. movi a3, cpu_start_id
  258. memw
  259. s32i a2, a3, 0
  260. #if XCHAL_DCACHE_IS_WRITEBACK
  261. dhwbi a3, 0
  262. #endif
  263. 1:
  264. memw
  265. l32i a2, a3, 0
  266. dhi a3, 0
  267. bne a2, a0, 1b
  268. /*
  269. * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
  270. * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
  271. * xt-gdb to single step via DEBUG exceptions received directly
  272. * by ocd.
  273. */
  274. movi a1, 1
  275. movi a0, 0
  276. wsr a1, windowstart
  277. wsr a0, windowbase
  278. rsync
  279. movi a1, LOCKLEVEL
  280. wsr a1, ps
  281. rsync
  282. j _startup
  283. ENDPROC(cpu_restart)
  284. #endif /* CONFIG_HOTPLUG_CPU */
  285. /*
  286. * DATA section
  287. */
  288. __REFDATA
  289. .align 4
  290. ENTRY(start_info)
  291. .long init_thread_union + KERNEL_STACK_SIZE
  292. /*
  293. * BSS section
  294. */
  295. __PAGE_ALIGNED_BSS
  296. #ifdef CONFIG_MMU
  297. ENTRY(swapper_pg_dir)
  298. .fill PAGE_SIZE, 1, 0
  299. END(swapper_pg_dir)
  300. #endif
  301. ENTRY(empty_zero_page)
  302. .fill PAGE_SIZE, 1, 0
  303. END(empty_zero_page)