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  1. /*
  2. * Low-level exception handling
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 2004 - 2008 by Tensilica Inc.
  9. * Copyright (C) 2015 Cadence Design Systems Inc.
  10. *
  11. * Chris Zankel <chris@zankel.net>
  12. *
  13. */
  14. #include <linux/linkage.h>
  15. #include <linux/pgtable.h>
  16. #include <asm/asm-offsets.h>
  17. #include <asm/asmmacro.h>
  18. #include <asm/processor.h>
  19. #include <asm/coprocessor.h>
  20. #include <asm/thread_info.h>
  21. #include <asm/asm-uaccess.h>
  22. #include <asm/unistd.h>
  23. #include <asm/ptrace.h>
  24. #include <asm/current.h>
  25. #include <asm/page.h>
  26. #include <asm/signal.h>
  27. #include <asm/tlbflush.h>
  28. #include <variant/tie-asm.h>
  29. /* Unimplemented features. */
  30. #undef KERNEL_STACK_OVERFLOW_CHECK
  31. /* Not well tested.
  32. *
  33. * - fast_coprocessor
  34. */
  35. /*
  36. * Macro to find first bit set in WINDOWBASE from the left + 1
  37. *
  38. * 100....0 -> 1
  39. * 010....0 -> 2
  40. * 000....1 -> WSBITS
  41. */
  42. .macro ffs_ws bit mask
  43. #if XCHAL_HAVE_NSA
  44. nsau \bit, \mask # 32-WSBITS ... 31 (32 iff 0)
  45. addi \bit, \bit, WSBITS - 32 + 1 # uppest bit set -> return 1
  46. #else
  47. movi \bit, WSBITS
  48. #if WSBITS > 16
  49. _bltui \mask, 0x10000, 99f
  50. addi \bit, \bit, -16
  51. extui \mask, \mask, 16, 16
  52. #endif
  53. #if WSBITS > 8
  54. 99: _bltui \mask, 0x100, 99f
  55. addi \bit, \bit, -8
  56. srli \mask, \mask, 8
  57. #endif
  58. 99: _bltui \mask, 0x10, 99f
  59. addi \bit, \bit, -4
  60. srli \mask, \mask, 4
  61. 99: _bltui \mask, 0x4, 99f
  62. addi \bit, \bit, -2
  63. srli \mask, \mask, 2
  64. 99: _bltui \mask, 0x2, 99f
  65. addi \bit, \bit, -1
  66. 99:
  67. #endif
  68. .endm
  69. .macro irq_save flags tmp
  70. #if XTENSA_FAKE_NMI
  71. #if defined(CONFIG_DEBUG_KERNEL) && (LOCKLEVEL | TOPLEVEL) >= XCHAL_DEBUGLEVEL
  72. rsr \flags, ps
  73. extui \tmp, \flags, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
  74. bgei \tmp, LOCKLEVEL, 99f
  75. rsil \tmp, LOCKLEVEL
  76. 99:
  77. #else
  78. movi \tmp, LOCKLEVEL
  79. rsr \flags, ps
  80. or \flags, \flags, \tmp
  81. xsr \flags, ps
  82. rsync
  83. #endif
  84. #else
  85. rsil \flags, LOCKLEVEL
  86. #endif
  87. .endm
  88. /* ----------------- DEFAULT FIRST LEVEL EXCEPTION HANDLERS ----------------- */
  89. /*
  90. * First-level exception handler for user exceptions.
  91. * Save some special registers, extra states and all registers in the AR
  92. * register file that were in use in the user task, and jump to the common
  93. * exception code.
  94. * We save SAR (used to calculate WMASK), and WB and WS (we don't have to
  95. * save them for kernel exceptions).
  96. *
  97. * Entry condition for user_exception:
  98. *
  99. * a0: trashed, original value saved on stack (PT_AREG0)
  100. * a1: a1
  101. * a2: new stack pointer, original value in depc
  102. * a3: a3
  103. * depc: a2, original value saved on stack (PT_DEPC)
  104. * excsave1: dispatch table
  105. *
  106. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  107. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  108. *
  109. * Entry condition for _user_exception:
  110. *
  111. * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
  112. * excsave has been restored, and
  113. * stack pointer (a1) has been set.
  114. *
  115. * Note: _user_exception might be at an odd address. Don't use call0..call12
  116. */
  117. .literal_position
  118. ENTRY(user_exception)
  119. /* Save a1, a2, a3, and set SP. */
  120. rsr a0, depc
  121. s32i a1, a2, PT_AREG1
  122. s32i a0, a2, PT_AREG2
  123. s32i a3, a2, PT_AREG3
  124. mov a1, a2
  125. .globl _user_exception
  126. _user_exception:
  127. /* Save SAR and turn off single stepping */
  128. movi a2, 0
  129. wsr a2, depc # terminate user stack trace with 0
  130. rsr a3, sar
  131. xsr a2, icountlevel
  132. s32i a3, a1, PT_SAR
  133. s32i a2, a1, PT_ICOUNTLEVEL
  134. #if XCHAL_HAVE_THREADPTR
  135. rur a2, threadptr
  136. s32i a2, a1, PT_THREADPTR
  137. #endif
  138. /* Rotate ws so that the current windowbase is at bit0. */
  139. /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
  140. rsr a2, windowbase
  141. rsr a3, windowstart
  142. ssr a2
  143. s32i a2, a1, PT_WINDOWBASE
  144. s32i a3, a1, PT_WINDOWSTART
  145. slli a2, a3, 32-WSBITS
  146. src a2, a3, a2
  147. srli a2, a2, 32-WSBITS
  148. s32i a2, a1, PT_WMASK # needed for restoring registers
  149. /* Save only live registers. */
  150. _bbsi.l a2, 1, 1f
  151. s32i a4, a1, PT_AREG4
  152. s32i a5, a1, PT_AREG5
  153. s32i a6, a1, PT_AREG6
  154. s32i a7, a1, PT_AREG7
  155. _bbsi.l a2, 2, 1f
  156. s32i a8, a1, PT_AREG8
  157. s32i a9, a1, PT_AREG9
  158. s32i a10, a1, PT_AREG10
  159. s32i a11, a1, PT_AREG11
  160. _bbsi.l a2, 3, 1f
  161. s32i a12, a1, PT_AREG12
  162. s32i a13, a1, PT_AREG13
  163. s32i a14, a1, PT_AREG14
  164. s32i a15, a1, PT_AREG15
  165. _bnei a2, 1, 1f # only one valid frame?
  166. /* Only one valid frame, skip saving regs. */
  167. j 2f
  168. /* Save the remaining registers.
  169. * We have to save all registers up to the first '1' from
  170. * the right, except the current frame (bit 0).
  171. * Assume a2 is: 001001000110001
  172. * All register frames starting from the top field to the marked '1'
  173. * must be saved.
  174. */
  175. 1: addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0
  176. neg a3, a3 # yyyyxxww0 -> YYYYXXWW1+1
  177. and a3, a3, a2 # max. only one bit is set
  178. /* Find number of frames to save */
  179. ffs_ws a0, a3 # number of frames to the '1' from left
  180. /* Store information into WMASK:
  181. * bits 0..3: xxx1 masked lower 4 bits of the rotated windowstart,
  182. * bits 4...: number of valid 4-register frames
  183. */
  184. slli a3, a0, 4 # number of frames to save in bits 8..4
  185. extui a2, a2, 0, 4 # mask for the first 16 registers
  186. or a2, a3, a2
  187. s32i a2, a1, PT_WMASK # needed when we restore the reg-file
  188. /* Save 4 registers at a time */
  189. 1: rotw -1
  190. s32i a0, a5, PT_AREG_END - 16
  191. s32i a1, a5, PT_AREG_END - 12
  192. s32i a2, a5, PT_AREG_END - 8
  193. s32i a3, a5, PT_AREG_END - 4
  194. addi a0, a4, -1
  195. addi a1, a5, -16
  196. _bnez a0, 1b
  197. /* WINDOWBASE still in SAR! */
  198. rsr a2, sar # original WINDOWBASE
  199. movi a3, 1
  200. ssl a2
  201. sll a3, a3
  202. wsr a3, windowstart # set corresponding WINDOWSTART bit
  203. wsr a2, windowbase # and WINDOWSTART
  204. rsync
  205. /* We are back to the original stack pointer (a1) */
  206. 2: /* Now, jump to the common exception handler. */
  207. j common_exception
  208. ENDPROC(user_exception)
  209. /*
  210. * First-level exit handler for kernel exceptions
  211. * Save special registers and the live window frame.
  212. * Note: Even though we changes the stack pointer, we don't have to do a
  213. * MOVSP here, as we do that when we return from the exception.
  214. * (See comment in the kernel exception exit code)
  215. *
  216. * Entry condition for kernel_exception:
  217. *
  218. * a0: trashed, original value saved on stack (PT_AREG0)
  219. * a1: a1
  220. * a2: new stack pointer, original in DEPC
  221. * a3: a3
  222. * depc: a2, original value saved on stack (PT_DEPC)
  223. * excsave_1: dispatch table
  224. *
  225. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  226. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  227. *
  228. * Entry condition for _kernel_exception:
  229. *
  230. * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
  231. * excsave has been restored, and
  232. * stack pointer (a1) has been set.
  233. *
  234. * Note: _kernel_exception might be at an odd address. Don't use call0..call12
  235. */
  236. ENTRY(kernel_exception)
  237. /* Save a1, a2, a3, and set SP. */
  238. rsr a0, depc # get a2
  239. s32i a1, a2, PT_AREG1
  240. s32i a0, a2, PT_AREG2
  241. s32i a3, a2, PT_AREG3
  242. mov a1, a2
  243. .globl _kernel_exception
  244. _kernel_exception:
  245. /* Save SAR and turn off single stepping */
  246. movi a2, 0
  247. rsr a3, sar
  248. xsr a2, icountlevel
  249. s32i a3, a1, PT_SAR
  250. s32i a2, a1, PT_ICOUNTLEVEL
  251. /* Rotate ws so that the current windowbase is at bit0. */
  252. /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
  253. rsr a2, windowbase # don't need to save these, we only
  254. rsr a3, windowstart # need shifted windowstart: windowmask
  255. ssr a2
  256. slli a2, a3, 32-WSBITS
  257. src a2, a3, a2
  258. srli a2, a2, 32-WSBITS
  259. s32i a2, a1, PT_WMASK # needed for kernel_exception_exit
  260. /* Save only the live window-frame */
  261. _bbsi.l a2, 1, 1f
  262. s32i a4, a1, PT_AREG4
  263. s32i a5, a1, PT_AREG5
  264. s32i a6, a1, PT_AREG6
  265. s32i a7, a1, PT_AREG7
  266. _bbsi.l a2, 2, 1f
  267. s32i a8, a1, PT_AREG8
  268. s32i a9, a1, PT_AREG9
  269. s32i a10, a1, PT_AREG10
  270. s32i a11, a1, PT_AREG11
  271. _bbsi.l a2, 3, 1f
  272. s32i a12, a1, PT_AREG12
  273. s32i a13, a1, PT_AREG13
  274. s32i a14, a1, PT_AREG14
  275. s32i a15, a1, PT_AREG15
  276. _bnei a2, 1, 1f
  277. /* Copy spill slots of a0 and a1 to imitate movsp
  278. * in order to keep exception stack continuous
  279. */
  280. l32i a3, a1, PT_SIZE
  281. l32i a0, a1, PT_SIZE + 4
  282. s32e a3, a1, -16
  283. s32e a0, a1, -12
  284. 1:
  285. l32i a0, a1, PT_AREG0 # restore saved a0
  286. wsr a0, depc
  287. #ifdef KERNEL_STACK_OVERFLOW_CHECK
  288. /* Stack overflow check, for debugging */
  289. extui a2, a1, TASK_SIZE_BITS,XX
  290. movi a3, SIZE??
  291. _bge a2, a3, out_of_stack_panic
  292. #endif
  293. /*
  294. * This is the common exception handler.
  295. * We get here from the user exception handler or simply by falling through
  296. * from the kernel exception handler.
  297. * Save the remaining special registers, switch to kernel mode, and jump
  298. * to the second-level exception handler.
  299. *
  300. */
  301. common_exception:
  302. /* Save some registers, disable loops and clear the syscall flag. */
  303. rsr a2, debugcause
  304. rsr a3, epc1
  305. s32i a2, a1, PT_DEBUGCAUSE
  306. s32i a3, a1, PT_PC
  307. movi a2, NO_SYSCALL
  308. rsr a3, excvaddr
  309. s32i a2, a1, PT_SYSCALL
  310. movi a2, 0
  311. s32i a3, a1, PT_EXCVADDR
  312. #if XCHAL_HAVE_LOOPS
  313. xsr a2, lcount
  314. s32i a2, a1, PT_LCOUNT
  315. #endif
  316. #if XCHAL_HAVE_EXCLUSIVE
  317. /* Clear exclusive access monitor set by interrupted code */
  318. clrex
  319. #endif
  320. /* It is now save to restore the EXC_TABLE_FIXUP variable. */
  321. rsr a2, exccause
  322. movi a3, 0
  323. rsr a0, excsave1
  324. s32i a2, a1, PT_EXCCAUSE
  325. s32i a3, a0, EXC_TABLE_FIXUP
  326. /* All unrecoverable states are saved on stack, now, and a1 is valid.
  327. * Now we can allow exceptions again. In case we've got an interrupt
  328. * PS.INTLEVEL is set to LOCKLEVEL disabling furhter interrupts,
  329. * otherwise it's left unchanged.
  330. *
  331. * Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X)
  332. */
  333. rsr a3, ps
  334. s32i a3, a1, PT_PS # save ps
  335. #if XTENSA_FAKE_NMI
  336. /* Correct PS needs to be saved in the PT_PS:
  337. * - in case of exception or level-1 interrupt it's in the PS,
  338. * and is already saved.
  339. * - in case of medium level interrupt it's in the excsave2.
  340. */
  341. movi a0, EXCCAUSE_MAPPED_NMI
  342. extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
  343. beq a2, a0, .Lmedium_level_irq
  344. bnei a2, EXCCAUSE_LEVEL1_INTERRUPT, .Lexception
  345. beqz a3, .Llevel1_irq # level-1 IRQ sets ps.intlevel to 0
  346. .Lmedium_level_irq:
  347. rsr a0, excsave2
  348. s32i a0, a1, PT_PS # save medium-level interrupt ps
  349. bgei a3, LOCKLEVEL, .Lexception
  350. .Llevel1_irq:
  351. movi a3, LOCKLEVEL
  352. .Lexception:
  353. movi a0, PS_WOE_MASK
  354. or a3, a3, a0
  355. #else
  356. addi a2, a2, -EXCCAUSE_LEVEL1_INTERRUPT
  357. movi a0, LOCKLEVEL
  358. extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
  359. # a3 = PS.INTLEVEL
  360. moveqz a3, a0, a2 # a3 = LOCKLEVEL iff interrupt
  361. movi a2, PS_WOE_MASK
  362. or a3, a3, a2
  363. rsr a2, exccause
  364. #endif
  365. /* restore return address (or 0 if return to userspace) */
  366. rsr a0, depc
  367. wsr a3, ps
  368. rsync # PS.WOE => rsync => overflow
  369. /* Save lbeg, lend */
  370. #if XCHAL_HAVE_LOOPS
  371. rsr a4, lbeg
  372. rsr a3, lend
  373. s32i a4, a1, PT_LBEG
  374. s32i a3, a1, PT_LEND
  375. #endif
  376. /* Save SCOMPARE1 */
  377. #if XCHAL_HAVE_S32C1I
  378. rsr a3, scompare1
  379. s32i a3, a1, PT_SCOMPARE1
  380. #endif
  381. /* Save optional registers. */
  382. save_xtregs_opt a1 a3 a4 a5 a6 a7 PT_XTREGS_OPT
  383. /* Go to second-level dispatcher. Set up parameters to pass to the
  384. * exception handler and call the exception handler.
  385. */
  386. rsr a4, excsave1
  387. mov a6, a1 # pass stack frame
  388. mov a7, a2 # pass EXCCAUSE
  389. addx4 a4, a2, a4
  390. l32i a4, a4, EXC_TABLE_DEFAULT # load handler
  391. /* Call the second-level handler */
  392. callx4 a4
  393. /* Jump here for exception exit */
  394. .global common_exception_return
  395. common_exception_return:
  396. #if XTENSA_FAKE_NMI
  397. l32i a2, a1, PT_EXCCAUSE
  398. movi a3, EXCCAUSE_MAPPED_NMI
  399. beq a2, a3, .LNMIexit
  400. #endif
  401. 1:
  402. irq_save a2, a3
  403. #ifdef CONFIG_TRACE_IRQFLAGS
  404. call4 trace_hardirqs_off
  405. #endif
  406. /* Jump if we are returning from kernel exceptions. */
  407. l32i a3, a1, PT_PS
  408. GET_THREAD_INFO(a2, a1)
  409. l32i a4, a2, TI_FLAGS
  410. _bbci.l a3, PS_UM_BIT, 6f
  411. /* Specific to a user exception exit:
  412. * We need to check some flags for signal handling and rescheduling,
  413. * and have to restore WB and WS, extra states, and all registers
  414. * in the register file that were in use in the user task.
  415. * Note that we don't disable interrupts here.
  416. */
  417. _bbsi.l a4, TIF_NEED_RESCHED, 3f
  418. _bbsi.l a4, TIF_NOTIFY_RESUME, 2f
  419. _bbci.l a4, TIF_SIGPENDING, 5f
  420. 2: l32i a4, a1, PT_DEPC
  421. bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
  422. /* Call do_signal() */
  423. #ifdef CONFIG_TRACE_IRQFLAGS
  424. call4 trace_hardirqs_on
  425. #endif
  426. rsil a2, 0
  427. mov a6, a1
  428. call4 do_notify_resume # int do_notify_resume(struct pt_regs*)
  429. j 1b
  430. 3: /* Reschedule */
  431. #ifdef CONFIG_TRACE_IRQFLAGS
  432. call4 trace_hardirqs_on
  433. #endif
  434. rsil a2, 0
  435. call4 schedule # void schedule (void)
  436. j 1b
  437. #ifdef CONFIG_PREEMPTION
  438. 6:
  439. _bbci.l a4, TIF_NEED_RESCHED, 4f
  440. /* Check current_thread_info->preempt_count */
  441. l32i a4, a2, TI_PRE_COUNT
  442. bnez a4, 4f
  443. call4 preempt_schedule_irq
  444. j 4f
  445. #endif
  446. #if XTENSA_FAKE_NMI
  447. .LNMIexit:
  448. l32i a3, a1, PT_PS
  449. _bbci.l a3, PS_UM_BIT, 4f
  450. #endif
  451. 5:
  452. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  453. _bbci.l a4, TIF_DB_DISABLED, 7f
  454. call4 restore_dbreak
  455. 7:
  456. #endif
  457. #ifdef CONFIG_DEBUG_TLB_SANITY
  458. l32i a4, a1, PT_DEPC
  459. bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
  460. call4 check_tlb_sanity
  461. #endif
  462. 6:
  463. 4:
  464. #ifdef CONFIG_TRACE_IRQFLAGS
  465. extui a4, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
  466. bgei a4, LOCKLEVEL, 1f
  467. call4 trace_hardirqs_on
  468. 1:
  469. #endif
  470. /* Restore optional registers. */
  471. load_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
  472. /* Restore SCOMPARE1 */
  473. #if XCHAL_HAVE_S32C1I
  474. l32i a2, a1, PT_SCOMPARE1
  475. wsr a2, scompare1
  476. #endif
  477. wsr a3, ps /* disable interrupts */
  478. _bbci.l a3, PS_UM_BIT, kernel_exception_exit
  479. user_exception_exit:
  480. /* Restore the state of the task and return from the exception. */
  481. /* Switch to the user thread WINDOWBASE. Save SP temporarily in DEPC */
  482. l32i a2, a1, PT_WINDOWBASE
  483. l32i a3, a1, PT_WINDOWSTART
  484. wsr a1, depc # use DEPC as temp storage
  485. wsr a3, windowstart # restore WINDOWSTART
  486. ssr a2 # preserve user's WB in the SAR
  487. wsr a2, windowbase # switch to user's saved WB
  488. rsync
  489. rsr a1, depc # restore stack pointer
  490. l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9)
  491. rotw -1 # we restore a4..a7
  492. _bltui a6, 16, 1f # only have to restore current window?
  493. /* The working registers are a0 and a3. We are restoring to
  494. * a4..a7. Be careful not to destroy what we have just restored.
  495. * Note: wmask has the format YYYYM:
  496. * Y: number of registers saved in groups of 4
  497. * M: 4 bit mask of first 16 registers
  498. */
  499. mov a2, a6
  500. mov a3, a5
  501. 2: rotw -1 # a0..a3 become a4..a7
  502. addi a3, a7, -4*4 # next iteration
  503. addi a2, a6, -16 # decrementing Y in WMASK
  504. l32i a4, a3, PT_AREG_END + 0
  505. l32i a5, a3, PT_AREG_END + 4
  506. l32i a6, a3, PT_AREG_END + 8
  507. l32i a7, a3, PT_AREG_END + 12
  508. _bgeui a2, 16, 2b
  509. /* Clear unrestored registers (don't leak anything to user-land */
  510. 1: rsr a0, windowbase
  511. rsr a3, sar
  512. sub a3, a0, a3
  513. beqz a3, 2f
  514. extui a3, a3, 0, WBBITS
  515. 1: rotw -1
  516. addi a3, a7, -1
  517. movi a4, 0
  518. movi a5, 0
  519. movi a6, 0
  520. movi a7, 0
  521. bgei a3, 1, 1b
  522. /* We are back were we were when we started.
  523. * Note: a2 still contains WMASK (if we've returned to the original
  524. * frame where we had loaded a2), or at least the lower 4 bits
  525. * (if we have restored WSBITS-1 frames).
  526. */
  527. 2:
  528. #if XCHAL_HAVE_THREADPTR
  529. l32i a3, a1, PT_THREADPTR
  530. wur a3, threadptr
  531. #endif
  532. j common_exception_exit
  533. /* This is the kernel exception exit.
  534. * We avoided to do a MOVSP when we entered the exception, but we
  535. * have to do it here.
  536. */
  537. kernel_exception_exit:
  538. /* Check if we have to do a movsp.
  539. *
  540. * We only have to do a movsp if the previous window-frame has
  541. * been spilled to the *temporary* exception stack instead of the
  542. * task's stack. This is the case if the corresponding bit in
  543. * WINDOWSTART for the previous window-frame was set before
  544. * (not spilled) but is zero now (spilled).
  545. * If this bit is zero, all other bits except the one for the
  546. * current window frame are also zero. So, we can use a simple test:
  547. * 'and' WINDOWSTART and WINDOWSTART-1:
  548. *
  549. * (XXXXXX1[0]* - 1) AND XXXXXX1[0]* = XXXXXX0[0]*
  550. *
  551. * The result is zero only if one bit was set.
  552. *
  553. * (Note: We might have gone through several task switches before
  554. * we come back to the current task, so WINDOWBASE might be
  555. * different from the time the exception occurred.)
  556. */
  557. /* Test WINDOWSTART before and after the exception.
  558. * We actually have WMASK, so we only have to test if it is 1 or not.
  559. */
  560. l32i a2, a1, PT_WMASK
  561. _beqi a2, 1, common_exception_exit # Spilled before exception,jump
  562. /* Test WINDOWSTART now. If spilled, do the movsp */
  563. rsr a3, windowstart
  564. addi a0, a3, -1
  565. and a3, a3, a0
  566. _bnez a3, common_exception_exit
  567. /* Do a movsp (we returned from a call4, so we have at least a0..a7) */
  568. addi a0, a1, -16
  569. l32i a3, a0, 0
  570. l32i a4, a0, 4
  571. s32i a3, a1, PT_SIZE+0
  572. s32i a4, a1, PT_SIZE+4
  573. l32i a3, a0, 8
  574. l32i a4, a0, 12
  575. s32i a3, a1, PT_SIZE+8
  576. s32i a4, a1, PT_SIZE+12
  577. /* Common exception exit.
  578. * We restore the special register and the current window frame, and
  579. * return from the exception.
  580. *
  581. * Note: We expect a2 to hold PT_WMASK
  582. */
  583. common_exception_exit:
  584. /* Restore address registers. */
  585. _bbsi.l a2, 1, 1f
  586. l32i a4, a1, PT_AREG4
  587. l32i a5, a1, PT_AREG5
  588. l32i a6, a1, PT_AREG6
  589. l32i a7, a1, PT_AREG7
  590. _bbsi.l a2, 2, 1f
  591. l32i a8, a1, PT_AREG8
  592. l32i a9, a1, PT_AREG9
  593. l32i a10, a1, PT_AREG10
  594. l32i a11, a1, PT_AREG11
  595. _bbsi.l a2, 3, 1f
  596. l32i a12, a1, PT_AREG12
  597. l32i a13, a1, PT_AREG13
  598. l32i a14, a1, PT_AREG14
  599. l32i a15, a1, PT_AREG15
  600. /* Restore PC, SAR */
  601. 1: l32i a2, a1, PT_PC
  602. l32i a3, a1, PT_SAR
  603. wsr a2, epc1
  604. wsr a3, sar
  605. /* Restore LBEG, LEND, LCOUNT */
  606. #if XCHAL_HAVE_LOOPS
  607. l32i a2, a1, PT_LBEG
  608. l32i a3, a1, PT_LEND
  609. wsr a2, lbeg
  610. l32i a2, a1, PT_LCOUNT
  611. wsr a3, lend
  612. wsr a2, lcount
  613. #endif
  614. /* We control single stepping through the ICOUNTLEVEL register. */
  615. l32i a2, a1, PT_ICOUNTLEVEL
  616. movi a3, -2
  617. wsr a2, icountlevel
  618. wsr a3, icount
  619. /* Check if it was double exception. */
  620. l32i a0, a1, PT_DEPC
  621. l32i a3, a1, PT_AREG3
  622. l32i a2, a1, PT_AREG2
  623. _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
  624. /* Restore a0...a3 and return */
  625. l32i a0, a1, PT_AREG0
  626. l32i a1, a1, PT_AREG1
  627. rfe
  628. 1: wsr a0, depc
  629. l32i a0, a1, PT_AREG0
  630. l32i a1, a1, PT_AREG1
  631. rfde
  632. ENDPROC(kernel_exception)
  633. /*
  634. * Debug exception handler.
  635. *
  636. * Currently, we don't support KGDB, so only user application can be debugged.
  637. *
  638. * When we get here, a0 is trashed and saved to excsave[debuglevel]
  639. */
  640. .literal_position
  641. ENTRY(debug_exception)
  642. rsr a0, SREG_EPS + XCHAL_DEBUGLEVEL
  643. bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
  644. /* Set EPC1 and EXCCAUSE */
  645. wsr a2, depc # save a2 temporarily
  646. rsr a2, SREG_EPC + XCHAL_DEBUGLEVEL
  647. wsr a2, epc1
  648. movi a2, EXCCAUSE_MAPPED_DEBUG
  649. wsr a2, exccause
  650. /* Restore PS to the value before the debug exc but with PS.EXCM set.*/
  651. movi a2, 1 << PS_EXCM_BIT
  652. or a2, a0, a2
  653. wsr a2, ps
  654. /* Switch to kernel/user stack, restore jump vector, and save a0 */
  655. bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
  656. addi a2, a1, -16-PT_SIZE # assume kernel stack
  657. 3:
  658. l32i a0, a3, DT_DEBUG_SAVE
  659. s32i a1, a2, PT_AREG1
  660. s32i a0, a2, PT_AREG0
  661. movi a0, 0
  662. s32i a0, a2, PT_DEPC # mark it as a regular exception
  663. xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
  664. xsr a0, depc
  665. s32i a3, a2, PT_AREG3
  666. s32i a0, a2, PT_AREG2
  667. mov a1, a2
  668. /* Debug exception is handled as an exception, so interrupts will
  669. * likely be enabled in the common exception handler. Disable
  670. * preemption if we have HW breakpoints to preserve DEBUGCAUSE.DBNUM
  671. * meaning.
  672. */
  673. #if defined(CONFIG_PREEMPT_COUNT) && defined(CONFIG_HAVE_HW_BREAKPOINT)
  674. GET_THREAD_INFO(a2, a1)
  675. l32i a3, a2, TI_PRE_COUNT
  676. addi a3, a3, 1
  677. s32i a3, a2, TI_PRE_COUNT
  678. #endif
  679. rsr a2, ps
  680. bbsi.l a2, PS_UM_BIT, _user_exception
  681. j _kernel_exception
  682. 2: rsr a2, excsave1
  683. l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
  684. j 3b
  685. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  686. /* Debug exception while in exception mode. This may happen when
  687. * window overflow/underflow handler or fast exception handler hits
  688. * data breakpoint, in which case save and disable all data
  689. * breakpoints, single-step faulting instruction and restore data
  690. * breakpoints.
  691. */
  692. 1:
  693. bbci.l a0, PS_UM_BIT, 1b # jump if kernel mode
  694. rsr a0, debugcause
  695. bbsi.l a0, DEBUGCAUSE_DBREAK_BIT, .Ldebug_save_dbreak
  696. .set _index, 0
  697. .rept XCHAL_NUM_DBREAK
  698. l32i a0, a3, DT_DBREAKC_SAVE + _index * 4
  699. wsr a0, SREG_DBREAKC + _index
  700. .set _index, _index + 1
  701. .endr
  702. l32i a0, a3, DT_ICOUNT_LEVEL_SAVE
  703. wsr a0, icountlevel
  704. l32i a0, a3, DT_ICOUNT_SAVE
  705. xsr a0, icount
  706. l32i a0, a3, DT_DEBUG_SAVE
  707. xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
  708. rfi XCHAL_DEBUGLEVEL
  709. .Ldebug_save_dbreak:
  710. .set _index, 0
  711. .rept XCHAL_NUM_DBREAK
  712. movi a0, 0
  713. xsr a0, SREG_DBREAKC + _index
  714. s32i a0, a3, DT_DBREAKC_SAVE + _index * 4
  715. .set _index, _index + 1
  716. .endr
  717. movi a0, XCHAL_EXCM_LEVEL + 1
  718. xsr a0, icountlevel
  719. s32i a0, a3, DT_ICOUNT_LEVEL_SAVE
  720. movi a0, 0xfffffffe
  721. xsr a0, icount
  722. s32i a0, a3, DT_ICOUNT_SAVE
  723. l32i a0, a3, DT_DEBUG_SAVE
  724. xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
  725. rfi XCHAL_DEBUGLEVEL
  726. #else
  727. /* Debug exception while in exception mode. Should not happen. */
  728. 1: j 1b // FIXME!!
  729. #endif
  730. ENDPROC(debug_exception)
  731. /*
  732. * We get here in case of an unrecoverable exception.
  733. * The only thing we can do is to be nice and print a panic message.
  734. * We only produce a single stack frame for panic, so ???
  735. *
  736. *
  737. * Entry conditions:
  738. *
  739. * - a0 contains the caller address; original value saved in excsave1.
  740. * - the original a0 contains a valid return address (backtrace) or 0.
  741. * - a2 contains a valid stackpointer
  742. *
  743. * Notes:
  744. *
  745. * - If the stack pointer could be invalid, the caller has to setup a
  746. * dummy stack pointer (e.g. the stack of the init_task)
  747. *
  748. * - If the return address could be invalid, the caller has to set it
  749. * to 0, so the backtrace would stop.
  750. *
  751. */
  752. .align 4
  753. unrecoverable_text:
  754. .ascii "Unrecoverable error in exception handler\0"
  755. .literal_position
  756. ENTRY(unrecoverable_exception)
  757. movi a0, 1
  758. movi a1, 0
  759. wsr a0, windowstart
  760. wsr a1, windowbase
  761. rsync
  762. movi a1, PS_WOE_MASK | LOCKLEVEL
  763. wsr a1, ps
  764. rsync
  765. movi a1, init_task
  766. movi a0, 0
  767. addi a1, a1, PT_REGS_OFFSET
  768. movi a6, unrecoverable_text
  769. call4 panic
  770. 1: j 1b
  771. ENDPROC(unrecoverable_exception)
  772. /* -------------------------- FAST EXCEPTION HANDLERS ----------------------- */
  773. __XTENSA_HANDLER
  774. .literal_position
  775. /*
  776. * Fast-handler for alloca exceptions
  777. *
  778. * The ALLOCA handler is entered when user code executes the MOVSP
  779. * instruction and the caller's frame is not in the register file.
  780. *
  781. * This algorithm was taken from the Ross Morley's RTOS Porting Layer:
  782. *
  783. * /home/ross/rtos/porting/XtensaRTOS-PortingLayer-20090507/xtensa_vectors.S
  784. *
  785. * It leverages the existing window spill/fill routines and their support for
  786. * double exceptions. The 'movsp' instruction will only cause an exception if
  787. * the next window needs to be loaded. In fact this ALLOCA exception may be
  788. * replaced at some point by changing the hardware to do a underflow exception
  789. * of the proper size instead.
  790. *
  791. * This algorithm simply backs out the register changes started by the user
  792. * exception handler, makes it appear that we have started a window underflow
  793. * by rotating the window back and then setting the old window base (OWB) in
  794. * the 'ps' register with the rolled back window base. The 'movsp' instruction
  795. * will be re-executed and this time since the next window frames is in the
  796. * active AR registers it won't cause an exception.
  797. *
  798. * If the WindowUnderflow code gets a TLB miss the page will get mapped
  799. * the partial WindowUnderflow will be handled in the double exception
  800. * handler.
  801. *
  802. * Entry condition:
  803. *
  804. * a0: trashed, original value saved on stack (PT_AREG0)
  805. * a1: a1
  806. * a2: new stack pointer, original in DEPC
  807. * a3: a3
  808. * depc: a2, original value saved on stack (PT_DEPC)
  809. * excsave_1: dispatch table
  810. *
  811. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  812. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  813. */
  814. ENTRY(fast_alloca)
  815. rsr a0, windowbase
  816. rotw -1
  817. rsr a2, ps
  818. extui a3, a2, PS_OWB_SHIFT, PS_OWB_WIDTH
  819. xor a3, a3, a4
  820. l32i a4, a6, PT_AREG0
  821. l32i a1, a6, PT_DEPC
  822. rsr a6, depc
  823. wsr a1, depc
  824. slli a3, a3, PS_OWB_SHIFT
  825. xor a2, a2, a3
  826. wsr a2, ps
  827. rsync
  828. _bbci.l a4, 31, 4f
  829. rotw -1
  830. _bbci.l a8, 30, 8f
  831. rotw -1
  832. j _WindowUnderflow12
  833. 8: j _WindowUnderflow8
  834. 4: j _WindowUnderflow4
  835. ENDPROC(fast_alloca)
  836. #ifdef CONFIG_USER_ABI_CALL0_PROBE
  837. /*
  838. * fast illegal instruction handler.
  839. *
  840. * This is used to fix up user PS.WOE on the exception caused
  841. * by the first opcode related to register window. If PS.WOE is
  842. * already set it goes directly to the common user exception handler.
  843. *
  844. * Entry condition:
  845. *
  846. * a0: trashed, original value saved on stack (PT_AREG0)
  847. * a1: a1
  848. * a2: new stack pointer, original in DEPC
  849. * a3: a3
  850. * depc: a2, original value saved on stack (PT_DEPC)
  851. * excsave_1: dispatch table
  852. */
  853. ENTRY(fast_illegal_instruction_user)
  854. rsr a0, ps
  855. bbsi.l a0, PS_WOE_BIT, 1f
  856. s32i a3, a2, PT_AREG3
  857. movi a3, PS_WOE_MASK
  858. or a0, a0, a3
  859. wsr a0, ps
  860. l32i a3, a2, PT_AREG3
  861. l32i a0, a2, PT_AREG0
  862. rsr a2, depc
  863. rfe
  864. 1:
  865. call0 user_exception
  866. ENDPROC(fast_illegal_instruction_user)
  867. #endif
  868. /*
  869. * fast system calls.
  870. *
  871. * WARNING: The kernel doesn't save the entire user context before
  872. * handling a fast system call. These functions are small and short,
  873. * usually offering some functionality not available to user tasks.
  874. *
  875. * BE CAREFUL TO PRESERVE THE USER'S CONTEXT.
  876. *
  877. * Entry condition:
  878. *
  879. * a0: trashed, original value saved on stack (PT_AREG0)
  880. * a1: a1
  881. * a2: new stack pointer, original in DEPC
  882. * a3: a3
  883. * depc: a2, original value saved on stack (PT_DEPC)
  884. * excsave_1: dispatch table
  885. */
  886. ENTRY(fast_syscall_user)
  887. /* Skip syscall. */
  888. rsr a0, epc1
  889. addi a0, a0, 3
  890. wsr a0, epc1
  891. l32i a0, a2, PT_DEPC
  892. bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
  893. rsr a0, depc # get syscall-nr
  894. _beqz a0, fast_syscall_spill_registers
  895. _beqi a0, __NR_xtensa, fast_syscall_xtensa
  896. call0 user_exception
  897. ENDPROC(fast_syscall_user)
  898. ENTRY(fast_syscall_unrecoverable)
  899. /* Restore all states. */
  900. l32i a0, a2, PT_AREG0 # restore a0
  901. xsr a2, depc # restore a2, depc
  902. wsr a0, excsave1
  903. call0 unrecoverable_exception
  904. ENDPROC(fast_syscall_unrecoverable)
  905. /*
  906. * sysxtensa syscall handler
  907. *
  908. * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused);
  909. * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused);
  910. * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused);
  911. * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval);
  912. * a2 a6 a3 a4 a5
  913. *
  914. * Entry condition:
  915. *
  916. * a0: a2 (syscall-nr), original value saved on stack (PT_AREG0)
  917. * a1: a1
  918. * a2: new stack pointer, original in a0 and DEPC
  919. * a3: a3
  920. * a4..a15: unchanged
  921. * depc: a2, original value saved on stack (PT_DEPC)
  922. * excsave_1: dispatch table
  923. *
  924. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  925. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  926. *
  927. * Note: we don't have to save a2; a2 holds the return value
  928. */
  929. .literal_position
  930. #ifdef CONFIG_FAST_SYSCALL_XTENSA
  931. ENTRY(fast_syscall_xtensa)
  932. s32i a7, a2, PT_AREG7 # we need an additional register
  933. movi a7, 4 # sizeof(unsigned int)
  934. access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp
  935. _bgeui a6, SYS_XTENSA_COUNT, .Lill
  936. _bnei a6, SYS_XTENSA_ATOMIC_CMP_SWP, .Lnswp
  937. /* Fall through for ATOMIC_CMP_SWP. */
  938. .Lswp: /* Atomic compare and swap */
  939. EX(.Leac) l32i a0, a3, 0 # read old value
  940. bne a0, a4, 1f # same as old value? jump
  941. EX(.Leac) s32i a5, a3, 0 # different, modify value
  942. l32i a7, a2, PT_AREG7 # restore a7
  943. l32i a0, a2, PT_AREG0 # restore a0
  944. movi a2, 1 # and return 1
  945. rfe
  946. 1: l32i a7, a2, PT_AREG7 # restore a7
  947. l32i a0, a2, PT_AREG0 # restore a0
  948. movi a2, 0 # return 0 (note that we cannot set
  949. rfe
  950. .Lnswp: /* Atomic set, add, and exg_add. */
  951. EX(.Leac) l32i a7, a3, 0 # orig
  952. addi a6, a6, -SYS_XTENSA_ATOMIC_SET
  953. add a0, a4, a7 # + arg
  954. moveqz a0, a4, a6 # set
  955. addi a6, a6, SYS_XTENSA_ATOMIC_SET
  956. EX(.Leac) s32i a0, a3, 0 # write new value
  957. mov a0, a2
  958. mov a2, a7
  959. l32i a7, a0, PT_AREG7 # restore a7
  960. l32i a0, a0, PT_AREG0 # restore a0
  961. rfe
  962. .Leac: l32i a7, a2, PT_AREG7 # restore a7
  963. l32i a0, a2, PT_AREG0 # restore a0
  964. movi a2, -EFAULT
  965. rfe
  966. .Lill: l32i a7, a2, PT_AREG7 # restore a7
  967. l32i a0, a2, PT_AREG0 # restore a0
  968. movi a2, -EINVAL
  969. rfe
  970. ENDPROC(fast_syscall_xtensa)
  971. #else /* CONFIG_FAST_SYSCALL_XTENSA */
  972. ENTRY(fast_syscall_xtensa)
  973. l32i a0, a2, PT_AREG0 # restore a0
  974. movi a2, -ENOSYS
  975. rfe
  976. ENDPROC(fast_syscall_xtensa)
  977. #endif /* CONFIG_FAST_SYSCALL_XTENSA */
  978. /* fast_syscall_spill_registers.
  979. *
  980. * Entry condition:
  981. *
  982. * a0: trashed, original value saved on stack (PT_AREG0)
  983. * a1: a1
  984. * a2: new stack pointer, original in DEPC
  985. * a3: a3
  986. * depc: a2, original value saved on stack (PT_DEPC)
  987. * excsave_1: dispatch table
  988. *
  989. * Note: We assume the stack pointer is EXC_TABLE_KSTK in the fixup handler.
  990. */
  991. #ifdef CONFIG_FAST_SYSCALL_SPILL_REGISTERS
  992. ENTRY(fast_syscall_spill_registers)
  993. /* Register a FIXUP handler (pass current wb as a parameter) */
  994. xsr a3, excsave1
  995. movi a0, fast_syscall_spill_registers_fixup
  996. s32i a0, a3, EXC_TABLE_FIXUP
  997. rsr a0, windowbase
  998. s32i a0, a3, EXC_TABLE_PARAM
  999. xsr a3, excsave1 # restore a3 and excsave_1
  1000. /* Save a3, a4 and SAR on stack. */
  1001. rsr a0, sar
  1002. s32i a3, a2, PT_AREG3
  1003. s32i a0, a2, PT_SAR
  1004. /* The spill routine might clobber a4, a7, a8, a11, a12, and a15. */
  1005. s32i a4, a2, PT_AREG4
  1006. s32i a7, a2, PT_AREG7
  1007. s32i a8, a2, PT_AREG8
  1008. s32i a11, a2, PT_AREG11
  1009. s32i a12, a2, PT_AREG12
  1010. s32i a15, a2, PT_AREG15
  1011. /*
  1012. * Rotate ws so that the current windowbase is at bit 0.
  1013. * Assume ws = xxxwww1yy (www1 current window frame).
  1014. * Rotate ws right so that a4 = yyxxxwww1.
  1015. */
  1016. rsr a0, windowbase
  1017. rsr a3, windowstart # a3 = xxxwww1yy
  1018. ssr a0 # holds WB
  1019. slli a0, a3, WSBITS
  1020. or a3, a3, a0 # a3 = xxxwww1yyxxxwww1yy
  1021. srl a3, a3 # a3 = 00xxxwww1yyxxxwww1
  1022. /* We are done if there are no more than the current register frame. */
  1023. extui a3, a3, 1, WSBITS-1 # a3 = 0yyxxxwww
  1024. movi a0, (1 << (WSBITS-1))
  1025. _beqz a3, .Lnospill # only one active frame? jump
  1026. /* We want 1 at the top, so that we return to the current windowbase */
  1027. or a3, a3, a0 # 1yyxxxwww
  1028. /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */
  1029. wsr a3, windowstart # save shifted windowstart
  1030. neg a0, a3
  1031. and a3, a0, a3 # first bit set from right: 000010000
  1032. ffs_ws a0, a3 # a0: shifts to skip empty frames
  1033. movi a3, WSBITS
  1034. sub a0, a3, a0 # WSBITS-a0:number of 0-bits from right
  1035. ssr a0 # save in SAR for later.
  1036. rsr a3, windowbase
  1037. add a3, a3, a0
  1038. wsr a3, windowbase
  1039. rsync
  1040. rsr a3, windowstart
  1041. srl a3, a3 # shift windowstart
  1042. /* WB is now just one frame below the oldest frame in the register
  1043. window. WS is shifted so the oldest frame is in bit 0, thus, WB
  1044. and WS differ by one 4-register frame. */
  1045. /* Save frames. Depending what call was used (call4, call8, call12),
  1046. * we have to save 4,8. or 12 registers.
  1047. */
  1048. .Lloop: _bbsi.l a3, 1, .Lc4
  1049. _bbci.l a3, 2, .Lc12
  1050. .Lc8: s32e a4, a13, -16
  1051. l32e a4, a5, -12
  1052. s32e a8, a4, -32
  1053. s32e a5, a13, -12
  1054. s32e a6, a13, -8
  1055. s32e a7, a13, -4
  1056. s32e a9, a4, -28
  1057. s32e a10, a4, -24
  1058. s32e a11, a4, -20
  1059. srli a11, a3, 2 # shift windowbase by 2
  1060. rotw 2
  1061. _bnei a3, 1, .Lloop
  1062. j .Lexit
  1063. .Lc4: s32e a4, a9, -16
  1064. s32e a5, a9, -12
  1065. s32e a6, a9, -8
  1066. s32e a7, a9, -4
  1067. srli a7, a3, 1
  1068. rotw 1
  1069. _bnei a3, 1, .Lloop
  1070. j .Lexit
  1071. .Lc12: _bbci.l a3, 3, .Linvalid_mask # bit 2 shouldn't be zero!
  1072. /* 12-register frame (call12) */
  1073. l32e a0, a5, -12
  1074. s32e a8, a0, -48
  1075. mov a8, a0
  1076. s32e a9, a8, -44
  1077. s32e a10, a8, -40
  1078. s32e a11, a8, -36
  1079. s32e a12, a8, -32
  1080. s32e a13, a8, -28
  1081. s32e a14, a8, -24
  1082. s32e a15, a8, -20
  1083. srli a15, a3, 3
  1084. /* The stack pointer for a4..a7 is out of reach, so we rotate the
  1085. * window, grab the stackpointer, and rotate back.
  1086. * Alternatively, we could also use the following approach, but that
  1087. * makes the fixup routine much more complicated:
  1088. * rotw 1
  1089. * s32e a0, a13, -16
  1090. * ...
  1091. * rotw 2
  1092. */
  1093. rotw 1
  1094. mov a4, a13
  1095. rotw -1
  1096. s32e a4, a8, -16
  1097. s32e a5, a8, -12
  1098. s32e a6, a8, -8
  1099. s32e a7, a8, -4
  1100. rotw 3
  1101. _beqi a3, 1, .Lexit
  1102. j .Lloop
  1103. .Lexit:
  1104. /* Done. Do the final rotation and set WS */
  1105. rotw 1
  1106. rsr a3, windowbase
  1107. ssl a3
  1108. movi a3, 1
  1109. sll a3, a3
  1110. wsr a3, windowstart
  1111. .Lnospill:
  1112. /* Advance PC, restore registers and SAR, and return from exception. */
  1113. l32i a3, a2, PT_SAR
  1114. l32i a0, a2, PT_AREG0
  1115. wsr a3, sar
  1116. l32i a3, a2, PT_AREG3
  1117. /* Restore clobbered registers. */
  1118. l32i a4, a2, PT_AREG4
  1119. l32i a7, a2, PT_AREG7
  1120. l32i a8, a2, PT_AREG8
  1121. l32i a11, a2, PT_AREG11
  1122. l32i a12, a2, PT_AREG12
  1123. l32i a15, a2, PT_AREG15
  1124. movi a2, 0
  1125. rfe
  1126. .Linvalid_mask:
  1127. /* We get here because of an unrecoverable error in the window
  1128. * registers, so set up a dummy frame and kill the user application.
  1129. * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
  1130. */
  1131. movi a0, 1
  1132. movi a1, 0
  1133. wsr a0, windowstart
  1134. wsr a1, windowbase
  1135. rsync
  1136. movi a0, 0
  1137. rsr a3, excsave1
  1138. l32i a1, a3, EXC_TABLE_KSTK
  1139. movi a4, PS_WOE_MASK | LOCKLEVEL
  1140. wsr a4, ps
  1141. rsync
  1142. movi a6, SIGSEGV
  1143. call4 do_exit
  1144. /* shouldn't return, so panic */
  1145. wsr a0, excsave1
  1146. call0 unrecoverable_exception # should not return
  1147. 1: j 1b
  1148. ENDPROC(fast_syscall_spill_registers)
  1149. /* Fixup handler.
  1150. *
  1151. * We get here if the spill routine causes an exception, e.g. tlb miss.
  1152. * We basically restore WINDOWBASE and WINDOWSTART to the condition when
  1153. * we entered the spill routine and jump to the user exception handler.
  1154. *
  1155. * Note that we only need to restore the bits in windowstart that have not
  1156. * been spilled yet by the _spill_register routine. Luckily, a3 contains a
  1157. * rotated windowstart with only those bits set for frames that haven't been
  1158. * spilled yet. Because a3 is rotated such that bit 0 represents the register
  1159. * frame for the current windowbase - 1, we need to rotate a3 left by the
  1160. * value of the current windowbase + 1 and move it to windowstart.
  1161. *
  1162. * a0: value of depc, original value in depc
  1163. * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE
  1164. * a3: exctable, original value in excsave1
  1165. */
  1166. ENTRY(fast_syscall_spill_registers_fixup)
  1167. rsr a2, windowbase # get current windowbase (a2 is saved)
  1168. xsr a0, depc # restore depc and a0
  1169. ssl a2 # set shift (32 - WB)
  1170. /* We need to make sure the current registers (a0-a3) are preserved.
  1171. * To do this, we simply set the bit for the current window frame
  1172. * in WS, so that the exception handlers save them to the task stack.
  1173. *
  1174. * Note: we use a3 to set the windowbase, so we take a special care
  1175. * of it, saving it in the original _spill_registers frame across
  1176. * the exception handler call.
  1177. */
  1178. xsr a3, excsave1 # get spill-mask
  1179. slli a3, a3, 1 # shift left by one
  1180. addi a3, a3, 1 # set the bit for the current window frame
  1181. slli a2, a3, 32-WSBITS
  1182. src a2, a3, a2 # a2 = xxwww1yyxxxwww1yy......
  1183. wsr a2, windowstart # set corrected windowstart
  1184. srli a3, a3, 1
  1185. rsr a2, excsave1
  1186. l32i a2, a2, EXC_TABLE_DOUBLE_SAVE # restore a2
  1187. xsr a2, excsave1
  1188. s32i a3, a2, EXC_TABLE_DOUBLE_SAVE # save a3
  1189. l32i a3, a2, EXC_TABLE_PARAM # original WB (in user task)
  1190. xsr a2, excsave1
  1191. /* Return to the original (user task) WINDOWBASE.
  1192. * We leave the following frame behind:
  1193. * a0, a1, a2 same
  1194. * a3: trashed (saved in EXC_TABLE_DOUBLE_SAVE)
  1195. * depc: depc (we have to return to that address)
  1196. * excsave_1: exctable
  1197. */
  1198. wsr a3, windowbase
  1199. rsync
  1200. /* We are now in the original frame when we entered _spill_registers:
  1201. * a0: return address
  1202. * a1: used, stack pointer
  1203. * a2: kernel stack pointer
  1204. * a3: available
  1205. * depc: exception address
  1206. * excsave: exctable
  1207. * Note: This frame might be the same as above.
  1208. */
  1209. /* Setup stack pointer. */
  1210. addi a2, a2, -PT_USER_SIZE
  1211. s32i a0, a2, PT_AREG0
  1212. /* Make sure we return to this fixup handler. */
  1213. movi a3, fast_syscall_spill_registers_fixup_return
  1214. s32i a3, a2, PT_DEPC # setup depc
  1215. /* Jump to the exception handler. */
  1216. rsr a3, excsave1
  1217. rsr a0, exccause
  1218. addx4 a0, a0, a3 # find entry in table
  1219. l32i a0, a0, EXC_TABLE_FAST_USER # load handler
  1220. l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
  1221. jx a0
  1222. ENDPROC(fast_syscall_spill_registers_fixup)
  1223. ENTRY(fast_syscall_spill_registers_fixup_return)
  1224. /* When we return here, all registers have been restored (a2: DEPC) */
  1225. wsr a2, depc # exception address
  1226. /* Restore fixup handler. */
  1227. rsr a2, excsave1
  1228. s32i a3, a2, EXC_TABLE_DOUBLE_SAVE
  1229. movi a3, fast_syscall_spill_registers_fixup
  1230. s32i a3, a2, EXC_TABLE_FIXUP
  1231. rsr a3, windowbase
  1232. s32i a3, a2, EXC_TABLE_PARAM
  1233. l32i a2, a2, EXC_TABLE_KSTK
  1234. /* Load WB at the time the exception occurred. */
  1235. rsr a3, sar # WB is still in SAR
  1236. neg a3, a3
  1237. wsr a3, windowbase
  1238. rsync
  1239. rsr a3, excsave1
  1240. l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
  1241. rfde
  1242. ENDPROC(fast_syscall_spill_registers_fixup_return)
  1243. #else /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */
  1244. ENTRY(fast_syscall_spill_registers)
  1245. l32i a0, a2, PT_AREG0 # restore a0
  1246. movi a2, -ENOSYS
  1247. rfe
  1248. ENDPROC(fast_syscall_spill_registers)
  1249. #endif /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */
  1250. #ifdef CONFIG_MMU
  1251. /*
  1252. * We should never get here. Bail out!
  1253. */
  1254. ENTRY(fast_second_level_miss_double_kernel)
  1255. 1:
  1256. call0 unrecoverable_exception # should not return
  1257. 1: j 1b
  1258. ENDPROC(fast_second_level_miss_double_kernel)
  1259. /* First-level entry handler for user, kernel, and double 2nd-level
  1260. * TLB miss exceptions. Note that for now, user and kernel miss
  1261. * exceptions share the same entry point and are handled identically.
  1262. *
  1263. * An old, less-efficient C version of this function used to exist.
  1264. * We include it below, interleaved as comments, for reference.
  1265. *
  1266. * Entry condition:
  1267. *
  1268. * a0: trashed, original value saved on stack (PT_AREG0)
  1269. * a1: a1
  1270. * a2: new stack pointer, original in DEPC
  1271. * a3: a3
  1272. * depc: a2, original value saved on stack (PT_DEPC)
  1273. * excsave_1: dispatch table
  1274. *
  1275. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  1276. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  1277. */
  1278. ENTRY(fast_second_level_miss)
  1279. /* Save a1 and a3. Note: we don't expect a double exception. */
  1280. s32i a1, a2, PT_AREG1
  1281. s32i a3, a2, PT_AREG3
  1282. /* We need to map the page of PTEs for the user task. Find
  1283. * the pointer to that page. Also, it's possible for tsk->mm
  1284. * to be NULL while tsk->active_mm is nonzero if we faulted on
  1285. * a vmalloc address. In that rare case, we must use
  1286. * active_mm instead to avoid a fault in this handler. See
  1287. *
  1288. * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html
  1289. * (or search Internet on "mm vs. active_mm")
  1290. *
  1291. * if (!mm)
  1292. * mm = tsk->active_mm;
  1293. * pgd = pgd_offset (mm, regs->excvaddr);
  1294. * pmd = pmd_offset (pgd, regs->excvaddr);
  1295. * pmdval = *pmd;
  1296. */
  1297. GET_CURRENT(a1,a2)
  1298. l32i a0, a1, TASK_MM # tsk->mm
  1299. beqz a0, 9f
  1300. 8: rsr a3, excvaddr # fault address
  1301. _PGD_OFFSET(a0, a3, a1)
  1302. l32i a0, a0, 0 # read pmdval
  1303. beqz a0, 2f
  1304. /* Read ptevaddr and convert to top of page-table page.
  1305. *
  1306. * vpnval = read_ptevaddr_register() & PAGE_MASK;
  1307. * vpnval += DTLB_WAY_PGTABLE;
  1308. * pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL);
  1309. * write_dtlb_entry (pteval, vpnval);
  1310. *
  1311. * The messy computation for 'pteval' above really simplifies
  1312. * into the following:
  1313. *
  1314. * pteval = ((pmdval - PAGE_OFFSET + PHYS_OFFSET) & PAGE_MASK)
  1315. * | PAGE_DIRECTORY
  1316. */
  1317. movi a1, (PHYS_OFFSET - PAGE_OFFSET) & 0xffffffff
  1318. add a0, a0, a1 # pmdval - PAGE_OFFSET
  1319. extui a1, a0, 0, PAGE_SHIFT # ... & PAGE_MASK
  1320. xor a0, a0, a1
  1321. movi a1, _PAGE_DIRECTORY
  1322. or a0, a0, a1 # ... | PAGE_DIRECTORY
  1323. /*
  1324. * We utilize all three wired-ways (7-9) to hold pmd translations.
  1325. * Memory regions are mapped to the DTLBs according to bits 28 and 29.
  1326. * This allows to map the three most common regions to three different
  1327. * DTLBs:
  1328. * 0,1 -> way 7 program (0040.0000) and virtual (c000.0000)
  1329. * 2 -> way 8 shared libaries (2000.0000)
  1330. * 3 -> way 0 stack (3000.0000)
  1331. */
  1332. extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3
  1333. rsr a1, ptevaddr
  1334. addx2 a3, a3, a3 # -> 0,3,6,9
  1335. srli a1, a1, PAGE_SHIFT
  1336. extui a3, a3, 2, 2 # -> 0,0,1,2
  1337. slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK
  1338. addi a3, a3, DTLB_WAY_PGD
  1339. add a1, a1, a3 # ... + way_number
  1340. 3: wdtlb a0, a1
  1341. dsync
  1342. /* Exit critical section. */
  1343. 4: rsr a3, excsave1
  1344. movi a0, 0
  1345. s32i a0, a3, EXC_TABLE_FIXUP
  1346. /* Restore the working registers, and return. */
  1347. l32i a0, a2, PT_AREG0
  1348. l32i a1, a2, PT_AREG1
  1349. l32i a3, a2, PT_AREG3
  1350. l32i a2, a2, PT_DEPC
  1351. bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
  1352. /* Restore excsave1 and return. */
  1353. rsr a2, depc
  1354. rfe
  1355. /* Return from double exception. */
  1356. 1: xsr a2, depc
  1357. esync
  1358. rfde
  1359. 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
  1360. bnez a0, 8b
  1361. /* Even more unlikely case active_mm == 0.
  1362. * We can get here with NMI in the middle of context_switch that
  1363. * touches vmalloc area.
  1364. */
  1365. movi a0, init_mm
  1366. j 8b
  1367. #if (DCACHE_WAY_SIZE > PAGE_SIZE)
  1368. 2: /* Special case for cache aliasing.
  1369. * We (should) only get here if a clear_user_page, copy_user_page
  1370. * or the aliased cache flush functions got preemptively interrupted
  1371. * by another task. Re-establish temporary mapping to the
  1372. * TLBTEMP_BASE areas.
  1373. */
  1374. /* We shouldn't be in a double exception */
  1375. l32i a0, a2, PT_DEPC
  1376. bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 2f
  1377. /* Make sure the exception originated in the special functions */
  1378. movi a0, __tlbtemp_mapping_start
  1379. rsr a3, epc1
  1380. bltu a3, a0, 2f
  1381. movi a0, __tlbtemp_mapping_end
  1382. bgeu a3, a0, 2f
  1383. /* Check if excvaddr was in one of the TLBTEMP_BASE areas. */
  1384. movi a3, TLBTEMP_BASE_1
  1385. rsr a0, excvaddr
  1386. bltu a0, a3, 2f
  1387. addi a1, a0, -TLBTEMP_SIZE
  1388. bgeu a1, a3, 2f
  1389. /* Check if we have to restore an ITLB mapping. */
  1390. movi a1, __tlbtemp_mapping_itlb
  1391. rsr a3, epc1
  1392. sub a3, a3, a1
  1393. /* Calculate VPN */
  1394. movi a1, PAGE_MASK
  1395. and a1, a1, a0
  1396. /* Jump for ITLB entry */
  1397. bgez a3, 1f
  1398. /* We can use up to two TLBTEMP areas, one for src and one for dst. */
  1399. extui a3, a0, PAGE_SHIFT + DCACHE_ALIAS_ORDER, 1
  1400. add a1, a3, a1
  1401. /* PPN is in a6 for the first TLBTEMP area and in a7 for the second. */
  1402. mov a0, a6
  1403. movnez a0, a7, a3
  1404. j 3b
  1405. /* ITLB entry. We only use dst in a6. */
  1406. 1: witlb a6, a1
  1407. isync
  1408. j 4b
  1409. #endif // DCACHE_WAY_SIZE > PAGE_SIZE
  1410. 2: /* Invalid PGD, default exception handling */
  1411. rsr a1, depc
  1412. s32i a1, a2, PT_AREG2
  1413. mov a1, a2
  1414. rsr a2, ps
  1415. bbsi.l a2, PS_UM_BIT, 1f
  1416. call0 _kernel_exception
  1417. 1: call0 _user_exception
  1418. ENDPROC(fast_second_level_miss)
  1419. /*
  1420. * StoreProhibitedException
  1421. *
  1422. * Update the pte and invalidate the itlb mapping for this pte.
  1423. *
  1424. * Entry condition:
  1425. *
  1426. * a0: trashed, original value saved on stack (PT_AREG0)
  1427. * a1: a1
  1428. * a2: new stack pointer, original in DEPC
  1429. * a3: a3
  1430. * depc: a2, original value saved on stack (PT_DEPC)
  1431. * excsave_1: dispatch table
  1432. *
  1433. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  1434. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  1435. */
  1436. ENTRY(fast_store_prohibited)
  1437. /* Save a1 and a3. */
  1438. s32i a1, a2, PT_AREG1
  1439. s32i a3, a2, PT_AREG3
  1440. GET_CURRENT(a1,a2)
  1441. l32i a0, a1, TASK_MM # tsk->mm
  1442. beqz a0, 9f
  1443. 8: rsr a1, excvaddr # fault address
  1444. _PGD_OFFSET(a0, a1, a3)
  1445. l32i a0, a0, 0
  1446. beqz a0, 2f
  1447. /*
  1448. * Note that we test _PAGE_WRITABLE_BIT only if PTE is present
  1449. * and is not PAGE_NONE. See pgtable.h for possible PTE layouts.
  1450. */
  1451. _PTE_OFFSET(a0, a1, a3)
  1452. l32i a3, a0, 0 # read pteval
  1453. movi a1, _PAGE_CA_INVALID
  1454. ball a3, a1, 2f
  1455. bbci.l a3, _PAGE_WRITABLE_BIT, 2f
  1456. movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE
  1457. or a3, a3, a1
  1458. rsr a1, excvaddr
  1459. s32i a3, a0, 0
  1460. /* We need to flush the cache if we have page coloring. */
  1461. #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
  1462. dhwb a0, 0
  1463. #endif
  1464. pdtlb a0, a1
  1465. wdtlb a3, a0
  1466. /* Exit critical section. */
  1467. movi a0, 0
  1468. rsr a3, excsave1
  1469. s32i a0, a3, EXC_TABLE_FIXUP
  1470. /* Restore the working registers, and return. */
  1471. l32i a3, a2, PT_AREG3
  1472. l32i a1, a2, PT_AREG1
  1473. l32i a0, a2, PT_AREG0
  1474. l32i a2, a2, PT_DEPC
  1475. bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
  1476. rsr a2, depc
  1477. rfe
  1478. /* Double exception. Restore FIXUP handler and return. */
  1479. 1: xsr a2, depc
  1480. esync
  1481. rfde
  1482. 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
  1483. j 8b
  1484. 2: /* If there was a problem, handle fault in C */
  1485. rsr a3, depc # still holds a2
  1486. s32i a3, a2, PT_AREG2
  1487. mov a1, a2
  1488. rsr a2, ps
  1489. bbsi.l a2, PS_UM_BIT, 1f
  1490. call0 _kernel_exception
  1491. 1: call0 _user_exception
  1492. ENDPROC(fast_store_prohibited)
  1493. #endif /* CONFIG_MMU */
  1494. .text
  1495. /*
  1496. * System Calls.
  1497. *
  1498. * void system_call (struct pt_regs* regs, int exccause)
  1499. * a2 a3
  1500. */
  1501. .literal_position
  1502. ENTRY(system_call)
  1503. abi_entry_default
  1504. /* regs->syscall = regs->areg[2] */
  1505. l32i a7, a2, PT_AREG2
  1506. s32i a7, a2, PT_SYSCALL
  1507. GET_THREAD_INFO(a4, a1)
  1508. l32i a3, a4, TI_FLAGS
  1509. movi a4, _TIF_WORK_MASK
  1510. and a3, a3, a4
  1511. beqz a3, 1f
  1512. mov a6, a2
  1513. call4 do_syscall_trace_enter
  1514. beqz a6, .Lsyscall_exit
  1515. l32i a7, a2, PT_SYSCALL
  1516. 1:
  1517. /* syscall = sys_call_table[syscall_nr] */
  1518. movi a4, sys_call_table
  1519. movi a5, __NR_syscalls
  1520. movi a6, -ENOSYS
  1521. bgeu a7, a5, 1f
  1522. addx4 a4, a7, a4
  1523. l32i a4, a4, 0
  1524. /* Load args: arg0 - arg5 are passed via regs. */
  1525. l32i a6, a2, PT_AREG6
  1526. l32i a7, a2, PT_AREG3
  1527. l32i a8, a2, PT_AREG4
  1528. l32i a9, a2, PT_AREG5
  1529. l32i a10, a2, PT_AREG8
  1530. l32i a11, a2, PT_AREG9
  1531. callx4 a4
  1532. 1: /* regs->areg[2] = return_value */
  1533. s32i a6, a2, PT_AREG2
  1534. bnez a3, 1f
  1535. .Lsyscall_exit:
  1536. abi_ret_default
  1537. 1:
  1538. mov a6, a2
  1539. call4 do_syscall_trace_leave
  1540. abi_ret_default
  1541. ENDPROC(system_call)
  1542. /*
  1543. * Spill live registers on the kernel stack macro.
  1544. *
  1545. * Entry condition: ps.woe is set, ps.excm is cleared
  1546. * Exit condition: windowstart has single bit set
  1547. * May clobber: a12, a13
  1548. */
  1549. .macro spill_registers_kernel
  1550. #if XCHAL_NUM_AREGS > 16
  1551. call12 1f
  1552. _j 2f
  1553. retw
  1554. .align 4
  1555. 1:
  1556. _entry a1, 48
  1557. addi a12, a0, 3
  1558. #if XCHAL_NUM_AREGS > 32
  1559. .rept (XCHAL_NUM_AREGS - 32) / 12
  1560. _entry a1, 48
  1561. mov a12, a0
  1562. .endr
  1563. #endif
  1564. _entry a1, 16
  1565. #if XCHAL_NUM_AREGS % 12 == 0
  1566. mov a8, a8
  1567. #elif XCHAL_NUM_AREGS % 12 == 4
  1568. mov a12, a12
  1569. #elif XCHAL_NUM_AREGS % 12 == 8
  1570. mov a4, a4
  1571. #endif
  1572. retw
  1573. 2:
  1574. #else
  1575. mov a12, a12
  1576. #endif
  1577. .endm
  1578. /*
  1579. * Task switch.
  1580. *
  1581. * struct task* _switch_to (struct task* prev, struct task* next)
  1582. * a2 a2 a3
  1583. */
  1584. ENTRY(_switch_to)
  1585. abi_entry(XTENSA_SPILL_STACK_RESERVE)
  1586. mov a11, a3 # and 'next' (a3)
  1587. l32i a4, a2, TASK_THREAD_INFO
  1588. l32i a5, a3, TASK_THREAD_INFO
  1589. save_xtregs_user a4 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
  1590. #if THREAD_RA > 1020 || THREAD_SP > 1020
  1591. addi a10, a2, TASK_THREAD
  1592. s32i a0, a10, THREAD_RA - TASK_THREAD # save return address
  1593. s32i a1, a10, THREAD_SP - TASK_THREAD # save stack pointer
  1594. #else
  1595. s32i a0, a2, THREAD_RA # save return address
  1596. s32i a1, a2, THREAD_SP # save stack pointer
  1597. #endif
  1598. #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
  1599. movi a6, __stack_chk_guard
  1600. l32i a8, a3, TASK_STACK_CANARY
  1601. s32i a8, a6, 0
  1602. #endif
  1603. /* Disable ints while we manipulate the stack pointer. */
  1604. irq_save a14, a3
  1605. rsync
  1606. /* Switch CPENABLE */
  1607. #if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS)
  1608. l32i a3, a5, THREAD_CPENABLE
  1609. xsr a3, cpenable
  1610. s32i a3, a4, THREAD_CPENABLE
  1611. #endif
  1612. #if XCHAL_HAVE_EXCLUSIVE
  1613. l32i a3, a5, THREAD_ATOMCTL8
  1614. getex a3
  1615. s32i a3, a4, THREAD_ATOMCTL8
  1616. #endif
  1617. /* Flush register file. */
  1618. spill_registers_kernel
  1619. /* Set kernel stack (and leave critical section)
  1620. * Note: It's save to set it here. The stack will not be overwritten
  1621. * because the kernel stack will only be loaded again after
  1622. * we return from kernel space.
  1623. */
  1624. rsr a3, excsave1 # exc_table
  1625. addi a7, a5, PT_REGS_OFFSET
  1626. s32i a7, a3, EXC_TABLE_KSTK
  1627. /* restore context of the task 'next' */
  1628. l32i a0, a11, THREAD_RA # restore return address
  1629. l32i a1, a11, THREAD_SP # restore stack pointer
  1630. load_xtregs_user a5 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
  1631. wsr a14, ps
  1632. rsync
  1633. abi_ret(XTENSA_SPILL_STACK_RESERVE)
  1634. ENDPROC(_switch_to)
  1635. ENTRY(ret_from_fork)
  1636. /* void schedule_tail (struct task_struct *prev)
  1637. * Note: prev is still in a6 (return value from fake call4 frame)
  1638. */
  1639. call4 schedule_tail
  1640. mov a6, a1
  1641. call4 do_syscall_trace_leave
  1642. j common_exception_return
  1643. ENDPROC(ret_from_fork)
  1644. /*
  1645. * Kernel thread creation helper
  1646. * On entry, set up by copy_thread: a2 = thread_fn, a3 = thread_fn arg
  1647. * left from _switch_to: a6 = prev
  1648. */
  1649. ENTRY(ret_from_kernel_thread)
  1650. call4 schedule_tail
  1651. mov a6, a3
  1652. callx4 a2
  1653. j common_exception_return
  1654. ENDPROC(ret_from_kernel_thread)