coprocessor.S 5.3 KB

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  1. /*
  2. * arch/xtensa/kernel/coprocessor.S
  3. *
  4. * Xtensa processor configuration-specific table of coprocessor and
  5. * other custom register layout information.
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. *
  11. * Copyright (C) 2003 - 2007 Tensilica Inc.
  12. */
  13. #include <linux/linkage.h>
  14. #include <asm/asm-offsets.h>
  15. #include <asm/asmmacro.h>
  16. #include <asm/coprocessor.h>
  17. #include <asm/current.h>
  18. #include <asm/regs.h>
  19. #if XTENSA_HAVE_COPROCESSORS
  20. /*
  21. * Macros for lazy context switch.
  22. */
  23. #define SAVE_CP_REGS(x) \
  24. .if XTENSA_HAVE_COPROCESSOR(x); \
  25. .align 4; \
  26. .Lsave_cp_regs_cp##x: \
  27. xchal_cp##x##_store a2 a3 a4 a5 a6; \
  28. jx a0; \
  29. .endif
  30. #define SAVE_CP_REGS_TAB(x) \
  31. .if XTENSA_HAVE_COPROCESSOR(x); \
  32. .long .Lsave_cp_regs_cp##x; \
  33. .else; \
  34. .long 0; \
  35. .endif; \
  36. .long THREAD_XTREGS_CP##x
  37. #define LOAD_CP_REGS(x) \
  38. .if XTENSA_HAVE_COPROCESSOR(x); \
  39. .align 4; \
  40. .Lload_cp_regs_cp##x: \
  41. xchal_cp##x##_load a2 a3 a4 a5 a6; \
  42. jx a0; \
  43. .endif
  44. #define LOAD_CP_REGS_TAB(x) \
  45. .if XTENSA_HAVE_COPROCESSOR(x); \
  46. .long .Lload_cp_regs_cp##x; \
  47. .else; \
  48. .long 0; \
  49. .endif; \
  50. .long THREAD_XTREGS_CP##x
  51. __XTENSA_HANDLER
  52. SAVE_CP_REGS(0)
  53. SAVE_CP_REGS(1)
  54. SAVE_CP_REGS(2)
  55. SAVE_CP_REGS(3)
  56. SAVE_CP_REGS(4)
  57. SAVE_CP_REGS(5)
  58. SAVE_CP_REGS(6)
  59. SAVE_CP_REGS(7)
  60. LOAD_CP_REGS(0)
  61. LOAD_CP_REGS(1)
  62. LOAD_CP_REGS(2)
  63. LOAD_CP_REGS(3)
  64. LOAD_CP_REGS(4)
  65. LOAD_CP_REGS(5)
  66. LOAD_CP_REGS(6)
  67. LOAD_CP_REGS(7)
  68. .align 4
  69. .Lsave_cp_regs_jump_table:
  70. SAVE_CP_REGS_TAB(0)
  71. SAVE_CP_REGS_TAB(1)
  72. SAVE_CP_REGS_TAB(2)
  73. SAVE_CP_REGS_TAB(3)
  74. SAVE_CP_REGS_TAB(4)
  75. SAVE_CP_REGS_TAB(5)
  76. SAVE_CP_REGS_TAB(6)
  77. SAVE_CP_REGS_TAB(7)
  78. .Lload_cp_regs_jump_table:
  79. LOAD_CP_REGS_TAB(0)
  80. LOAD_CP_REGS_TAB(1)
  81. LOAD_CP_REGS_TAB(2)
  82. LOAD_CP_REGS_TAB(3)
  83. LOAD_CP_REGS_TAB(4)
  84. LOAD_CP_REGS_TAB(5)
  85. LOAD_CP_REGS_TAB(6)
  86. LOAD_CP_REGS_TAB(7)
  87. /*
  88. * Entry condition:
  89. *
  90. * a0: trashed, original value saved on stack (PT_AREG0)
  91. * a1: a1
  92. * a2: new stack pointer, original in DEPC
  93. * a3: a3
  94. * depc: a2, original value saved on stack (PT_DEPC)
  95. * excsave_1: dispatch table
  96. *
  97. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  98. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  99. */
  100. ENTRY(fast_coprocessor)
  101. /* Save remaining registers a1-a3 and SAR */
  102. s32i a3, a2, PT_AREG3
  103. rsr a3, sar
  104. s32i a1, a2, PT_AREG1
  105. s32i a3, a2, PT_SAR
  106. mov a1, a2
  107. rsr a2, depc
  108. s32i a2, a1, PT_AREG2
  109. /*
  110. * The hal macros require up to 4 temporary registers. We use a3..a6.
  111. */
  112. s32i a4, a1, PT_AREG4
  113. s32i a5, a1, PT_AREG5
  114. s32i a6, a1, PT_AREG6
  115. /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
  116. rsr a3, exccause
  117. addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
  118. /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
  119. ssl a3 # SAR: 32 - coprocessor_number
  120. movi a2, 1
  121. rsr a0, cpenable
  122. sll a2, a2
  123. or a0, a0, a2
  124. wsr a0, cpenable
  125. rsync
  126. /* Retrieve previous owner. (a3 still holds CP number) */
  127. movi a0, coprocessor_owner # list of owners
  128. addx4 a0, a3, a0 # entry for CP
  129. l32i a4, a0, 0
  130. beqz a4, 1f # skip 'save' if no previous owner
  131. /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */
  132. l32i a5, a4, THREAD_CPENABLE
  133. xor a5, a5, a2 # (1 << cp-id) still in a2
  134. s32i a5, a4, THREAD_CPENABLE
  135. /*
  136. * Get context save area and 'call' save routine.
  137. * (a4 still holds previous owner (thread_info), a3 CP number)
  138. */
  139. movi a5, .Lsave_cp_regs_jump_table
  140. movi a0, 2f # a0: 'return' address
  141. addx8 a3, a3, a5 # a3: coprocessor number
  142. l32i a2, a3, 4 # a2: xtregs offset
  143. l32i a3, a3, 0 # a3: jump address
  144. add a2, a2, a4
  145. jx a3
  146. /* Note that only a0 and a1 were preserved. */
  147. 2: rsr a3, exccause
  148. addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
  149. movi a0, coprocessor_owner
  150. addx4 a0, a3, a0
  151. /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */
  152. 1: GET_THREAD_INFO (a4, a1)
  153. s32i a4, a0, 0
  154. /* Get context save area and 'call' load routine. */
  155. movi a5, .Lload_cp_regs_jump_table
  156. movi a0, 1f
  157. addx8 a3, a3, a5
  158. l32i a2, a3, 4 # a2: xtregs offset
  159. l32i a3, a3, 0 # a3: jump address
  160. add a2, a2, a4
  161. jx a3
  162. /* Restore all registers and return from exception handler. */
  163. 1: l32i a6, a1, PT_AREG6
  164. l32i a5, a1, PT_AREG5
  165. l32i a4, a1, PT_AREG4
  166. l32i a0, a1, PT_SAR
  167. l32i a3, a1, PT_AREG3
  168. l32i a2, a1, PT_AREG2
  169. wsr a0, sar
  170. l32i a0, a1, PT_AREG0
  171. l32i a1, a1, PT_AREG1
  172. rfe
  173. ENDPROC(fast_coprocessor)
  174. .text
  175. /*
  176. * coprocessor_flush(struct thread_info*, index)
  177. * a2 a3
  178. *
  179. * Save coprocessor registers for coprocessor 'index'.
  180. * The register values are saved to or loaded from the coprocessor area
  181. * inside the task_info structure.
  182. *
  183. * Note that this function doesn't update the coprocessor_owner information!
  184. *
  185. */
  186. ENTRY(coprocessor_flush)
  187. /* reserve 4 bytes on stack to save a0 */
  188. abi_entry(4)
  189. s32i a0, a1, 0
  190. movi a0, .Lsave_cp_regs_jump_table
  191. addx8 a3, a3, a0
  192. l32i a4, a3, 4
  193. l32i a3, a3, 0
  194. add a2, a2, a4
  195. beqz a3, 1f
  196. callx0 a3
  197. 1: l32i a0, a1, 0
  198. abi_ret(4)
  199. ENDPROC(coprocessor_flush)
  200. .data
  201. ENTRY(coprocessor_owner)
  202. .fill XCHAL_CP_MAX, 4, 0
  203. END(coprocessor_owner)
  204. #endif /* XTENSA_HAVE_COPROCESSORS */