tsc_msr.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * TSC frequency enumeration via MSR
  4. *
  5. * Copyright (C) 2013, 2018 Intel Corporation
  6. * Author: Bin Gao <bin.gao@intel.com>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/thread_info.h>
  10. #include <asm/apic.h>
  11. #include <asm/cpu_device_id.h>
  12. #include <asm/intel-family.h>
  13. #include <asm/msr.h>
  14. #include <asm/param.h>
  15. #include <asm/tsc.h>
  16. #define MAX_NUM_FREQS 16 /* 4 bits to select the frequency */
  17. /*
  18. * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
  19. * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
  20. * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
  21. * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
  22. * unclear if the root PLL outputs are used directly by the CPU clock PLL or
  23. * if there is another PLL in between.
  24. * This does not matter though, we can model the chain of PLLs as a single PLL
  25. * with a quotient equal to the quotients of all PLLs in the chain multiplied.
  26. * So we can create a simplified model of the CPU clock setup using a reference
  27. * clock of 100 MHz plus a quotient which gets us as close to the frequency
  28. * from the SDM as possible.
  29. * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
  30. * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
  31. */
  32. #define TSC_REFERENCE_KHZ 100000
  33. struct muldiv {
  34. u32 multiplier;
  35. u32 divider;
  36. };
  37. /*
  38. * If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
  39. * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
  40. * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
  41. * so we need manually differentiate SoC families. This is what the
  42. * field use_msr_plat does.
  43. */
  44. struct freq_desc {
  45. bool use_msr_plat;
  46. struct muldiv muldiv[MAX_NUM_FREQS];
  47. /*
  48. * Some CPU frequencies in the SDM do not map to known PLL freqs, in
  49. * that case the muldiv array is empty and the freqs array is used.
  50. */
  51. u32 freqs[MAX_NUM_FREQS];
  52. u32 mask;
  53. };
  54. /*
  55. * Penwell and Clovertrail use spread spectrum clock,
  56. * so the freq number is not exactly the same as reported
  57. * by MSR based on SDM.
  58. */
  59. static const struct freq_desc freq_desc_pnw = {
  60. .use_msr_plat = false,
  61. .freqs = { 0, 0, 0, 0, 0, 99840, 0, 83200 },
  62. .mask = 0x07,
  63. };
  64. static const struct freq_desc freq_desc_clv = {
  65. .use_msr_plat = false,
  66. .freqs = { 0, 133200, 0, 0, 0, 99840, 0, 83200 },
  67. .mask = 0x07,
  68. };
  69. /*
  70. * Bay Trail SDM MSR_FSB_FREQ frequencies simplified PLL model:
  71. * 000: 100 * 5 / 6 = 83.3333 MHz
  72. * 001: 100 * 1 / 1 = 100.0000 MHz
  73. * 010: 100 * 4 / 3 = 133.3333 MHz
  74. * 011: 100 * 7 / 6 = 116.6667 MHz
  75. * 100: 100 * 4 / 5 = 80.0000 MHz
  76. */
  77. static const struct freq_desc freq_desc_byt = {
  78. .use_msr_plat = true,
  79. .muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 7, 6 },
  80. { 4, 5 } },
  81. .mask = 0x07,
  82. };
  83. /*
  84. * Cherry Trail SDM MSR_FSB_FREQ frequencies simplified PLL model:
  85. * 0000: 100 * 5 / 6 = 83.3333 MHz
  86. * 0001: 100 * 1 / 1 = 100.0000 MHz
  87. * 0010: 100 * 4 / 3 = 133.3333 MHz
  88. * 0011: 100 * 7 / 6 = 116.6667 MHz
  89. * 0100: 100 * 4 / 5 = 80.0000 MHz
  90. * 0101: 100 * 14 / 15 = 93.3333 MHz
  91. * 0110: 100 * 9 / 10 = 90.0000 MHz
  92. * 0111: 100 * 8 / 9 = 88.8889 MHz
  93. * 1000: 100 * 7 / 8 = 87.5000 MHz
  94. */
  95. static const struct freq_desc freq_desc_cht = {
  96. .use_msr_plat = true,
  97. .muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 7, 6 },
  98. { 4, 5 }, { 14, 15 }, { 9, 10 }, { 8, 9 },
  99. { 7, 8 } },
  100. .mask = 0x0f,
  101. };
  102. /*
  103. * Merriefield SDM MSR_FSB_FREQ frequencies simplified PLL model:
  104. * 0001: 100 * 1 / 1 = 100.0000 MHz
  105. * 0010: 100 * 4 / 3 = 133.3333 MHz
  106. */
  107. static const struct freq_desc freq_desc_tng = {
  108. .use_msr_plat = true,
  109. .muldiv = { { 0, 0 }, { 1, 1 }, { 4, 3 } },
  110. .mask = 0x07,
  111. };
  112. /*
  113. * Moorefield SDM MSR_FSB_FREQ frequencies simplified PLL model:
  114. * 0000: 100 * 5 / 6 = 83.3333 MHz
  115. * 0001: 100 * 1 / 1 = 100.0000 MHz
  116. * 0010: 100 * 4 / 3 = 133.3333 MHz
  117. * 0011: 100 * 1 / 1 = 100.0000 MHz
  118. */
  119. static const struct freq_desc freq_desc_ann = {
  120. .use_msr_plat = true,
  121. .muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 1, 1 } },
  122. .mask = 0x0f,
  123. };
  124. /*
  125. * 24 MHz crystal? : 24 * 13 / 4 = 78 MHz
  126. * Frequency step for Lightning Mountain SoC is fixed to 78 MHz,
  127. * so all the frequency entries are 78000.
  128. */
  129. static const struct freq_desc freq_desc_lgm = {
  130. .use_msr_plat = true,
  131. .freqs = { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000,
  132. 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 },
  133. .mask = 0x0f,
  134. };
  135. static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
  136. X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, &freq_desc_pnw),
  137. X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_TABLET,&freq_desc_clv),
  138. X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &freq_desc_byt),
  139. X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &freq_desc_tng),
  140. X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &freq_desc_cht),
  141. X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_MID, &freq_desc_ann),
  142. X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_NP, &freq_desc_lgm),
  143. {}
  144. };
  145. /*
  146. * MSR-based CPU/TSC frequency discovery for certain CPUs.
  147. *
  148. * Set global "lapic_timer_period" to bus_clock_cycles/jiffy
  149. * Return processor base frequency in KHz, or 0 on failure.
  150. */
  151. unsigned long cpu_khz_from_msr(void)
  152. {
  153. u32 lo, hi, ratio, freq, tscref;
  154. const struct freq_desc *freq_desc;
  155. const struct x86_cpu_id *id;
  156. const struct muldiv *md;
  157. unsigned long res;
  158. int index;
  159. id = x86_match_cpu(tsc_msr_cpu_ids);
  160. if (!id)
  161. return 0;
  162. freq_desc = (struct freq_desc *)id->driver_data;
  163. if (freq_desc->use_msr_plat) {
  164. rdmsr(MSR_PLATFORM_INFO, lo, hi);
  165. ratio = (lo >> 8) & 0xff;
  166. } else {
  167. rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
  168. ratio = (hi >> 8) & 0x1f;
  169. }
  170. /* Get FSB FREQ ID */
  171. rdmsr(MSR_FSB_FREQ, lo, hi);
  172. index = lo & freq_desc->mask;
  173. md = &freq_desc->muldiv[index];
  174. /*
  175. * Note this also catches cases where the index points to an unpopulated
  176. * part of muldiv, in that case the else will set freq and res to 0.
  177. */
  178. if (md->divider) {
  179. tscref = TSC_REFERENCE_KHZ * md->multiplier;
  180. freq = DIV_ROUND_CLOSEST(tscref, md->divider);
  181. /*
  182. * Multiplying by ratio before the division has better
  183. * accuracy than just calculating freq * ratio.
  184. */
  185. res = DIV_ROUND_CLOSEST(tscref * ratio, md->divider);
  186. } else {
  187. freq = freq_desc->freqs[index];
  188. res = freq * ratio;
  189. }
  190. if (freq == 0)
  191. pr_err("Error MSR_FSB_FREQ index %d is unknown\n", index);
  192. #ifdef CONFIG_X86_LOCAL_APIC
  193. lapic_timer_period = (freq * 1000) / HZ;
  194. #endif
  195. /*
  196. * TSC frequency determined by MSR is always considered "known"
  197. * because it is reported by HW.
  198. * Another fact is that on MSR capable platforms, PIT/HPET is
  199. * generally not available so calibration won't work at all.
  200. */
  201. setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
  202. /*
  203. * Unfortunately there is no way for hardware to tell whether the
  204. * TSC is reliable. We were told by silicon design team that TSC
  205. * on Atom SoCs are always "reliable". TSC is also the only
  206. * reliable clocksource on these SoCs (HPET is either not present
  207. * or not functional) so mark TSC reliable which removes the
  208. * requirement for a watchdog clocksource.
  209. */
  210. setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
  211. return res;
  212. }