irqinit.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/linkage.h>
  3. #include <linux/errno.h>
  4. #include <linux/signal.h>
  5. #include <linux/sched.h>
  6. #include <linux/ioport.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/irq.h>
  9. #include <linux/timex.h>
  10. #include <linux/random.h>
  11. #include <linux/kprobes.h>
  12. #include <linux/init.h>
  13. #include <linux/kernel_stat.h>
  14. #include <linux/device.h>
  15. #include <linux/bitops.h>
  16. #include <linux/acpi.h>
  17. #include <linux/io.h>
  18. #include <linux/delay.h>
  19. #include <linux/pgtable.h>
  20. #include <linux/atomic.h>
  21. #include <asm/timer.h>
  22. #include <asm/hw_irq.h>
  23. #include <asm/desc.h>
  24. #include <asm/io_apic.h>
  25. #include <asm/acpi.h>
  26. #include <asm/apic.h>
  27. #include <asm/setup.h>
  28. #include <asm/i8259.h>
  29. #include <asm/traps.h>
  30. #include <asm/prom.h>
  31. /*
  32. * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  33. * (these are usually mapped to vectors 0x30-0x3f)
  34. */
  35. /*
  36. * The IO-APIC gives us many more interrupt sources. Most of these
  37. * are unused but an SMP system is supposed to have enough memory ...
  38. * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  39. * across the spectrum, so we really want to be prepared to get all
  40. * of these. Plus, more powerful systems might have more than 64
  41. * IO-APIC registers.
  42. *
  43. * (these are usually mapped into the 0x30-0xff vector range)
  44. */
  45. DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  46. [0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
  47. };
  48. void __init init_ISA_irqs(void)
  49. {
  50. struct irq_chip *chip = legacy_pic->chip;
  51. int i;
  52. /*
  53. * Try to set up the through-local-APIC virtual wire mode earlier.
  54. *
  55. * On some 32-bit UP machines, whose APIC has been disabled by BIOS
  56. * and then got re-enabled by "lapic", it hangs at boot time without this.
  57. */
  58. init_bsp_APIC();
  59. legacy_pic->init(0);
  60. for (i = 0; i < nr_legacy_irqs(); i++)
  61. irq_set_chip_and_handler(i, chip, handle_level_irq);
  62. }
  63. void __init init_IRQ(void)
  64. {
  65. int i;
  66. /*
  67. * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
  68. * If these IRQ's are handled by legacy interrupt-controllers like PIC,
  69. * then this configuration will likely be static after the boot. If
  70. * these IRQs are handled by more modern controllers like IO-APIC,
  71. * then this vector space can be freed and re-used dynamically as the
  72. * irq's migrate etc.
  73. */
  74. for (i = 0; i < nr_legacy_irqs(); i++)
  75. per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
  76. BUG_ON(irq_init_percpu_irqstack(smp_processor_id()));
  77. x86_init.irqs.intr_init();
  78. }
  79. void __init native_init_IRQ(void)
  80. {
  81. /* Execute any quirks before the call gates are initialised: */
  82. x86_init.irqs.pre_vector_init();
  83. idt_setup_apic_and_irq_gates();
  84. lapic_assign_system_vectors();
  85. if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) {
  86. /* IRQ2 is cascade interrupt to second interrupt controller */
  87. if (request_irq(2, no_action, IRQF_NO_THREAD, "cascade", NULL))
  88. pr_err("%s: request_irq() failed\n", "cascade");
  89. }
  90. }