idt.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Interrupt descriptor table related code
  4. */
  5. #include <linux/interrupt.h>
  6. #include <asm/cpu_entry_area.h>
  7. #include <asm/set_memory.h>
  8. #include <asm/traps.h>
  9. #include <asm/proto.h>
  10. #include <asm/desc.h>
  11. #include <asm/hw_irq.h>
  12. #define DPL0 0x0
  13. #define DPL3 0x3
  14. #define DEFAULT_STACK 0
  15. #define G(_vector, _addr, _ist, _type, _dpl, _segment) \
  16. { \
  17. .vector = _vector, \
  18. .bits.ist = _ist, \
  19. .bits.type = _type, \
  20. .bits.dpl = _dpl, \
  21. .bits.p = 1, \
  22. .addr = _addr, \
  23. .segment = _segment, \
  24. }
  25. /* Interrupt gate */
  26. #define INTG(_vector, _addr) \
  27. G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
  28. /* System interrupt gate */
  29. #define SYSG(_vector, _addr) \
  30. G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
  31. /*
  32. * Interrupt gate with interrupt stack. The _ist index is the index in
  33. * the tss.ist[] array, but for the descriptor it needs to start at 1.
  34. */
  35. #define ISTG(_vector, _addr, _ist) \
  36. G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS)
  37. /* Task gate */
  38. #define TSKG(_vector, _gdt) \
  39. G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
  40. #define IDT_TABLE_SIZE (IDT_ENTRIES * sizeof(gate_desc))
  41. static bool idt_setup_done __initdata;
  42. /*
  43. * Early traps running on the DEFAULT_STACK because the other interrupt
  44. * stacks work only after cpu_init().
  45. */
  46. static const __initconst struct idt_data early_idts[] = {
  47. INTG(X86_TRAP_DB, asm_exc_debug),
  48. SYSG(X86_TRAP_BP, asm_exc_int3),
  49. #ifdef CONFIG_X86_32
  50. /*
  51. * Not possible on 64-bit. See idt_setup_early_pf() for details.
  52. */
  53. INTG(X86_TRAP_PF, asm_exc_page_fault),
  54. #endif
  55. };
  56. /*
  57. * The default IDT entries which are set up in trap_init() before
  58. * cpu_init() is invoked. Interrupt stacks cannot be used at that point and
  59. * the traps which use them are reinitialized with IST after cpu_init() has
  60. * set up TSS.
  61. */
  62. static const __initconst struct idt_data def_idts[] = {
  63. INTG(X86_TRAP_DE, asm_exc_divide_error),
  64. INTG(X86_TRAP_NMI, asm_exc_nmi),
  65. INTG(X86_TRAP_BR, asm_exc_bounds),
  66. INTG(X86_TRAP_UD, asm_exc_invalid_op),
  67. INTG(X86_TRAP_NM, asm_exc_device_not_available),
  68. INTG(X86_TRAP_OLD_MF, asm_exc_coproc_segment_overrun),
  69. INTG(X86_TRAP_TS, asm_exc_invalid_tss),
  70. INTG(X86_TRAP_NP, asm_exc_segment_not_present),
  71. INTG(X86_TRAP_SS, asm_exc_stack_segment),
  72. INTG(X86_TRAP_GP, asm_exc_general_protection),
  73. INTG(X86_TRAP_SPURIOUS, asm_exc_spurious_interrupt_bug),
  74. INTG(X86_TRAP_MF, asm_exc_coprocessor_error),
  75. INTG(X86_TRAP_AC, asm_exc_alignment_check),
  76. INTG(X86_TRAP_XF, asm_exc_simd_coprocessor_error),
  77. #ifdef CONFIG_X86_32
  78. TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS),
  79. #else
  80. INTG(X86_TRAP_DF, asm_exc_double_fault),
  81. #endif
  82. INTG(X86_TRAP_DB, asm_exc_debug),
  83. #ifdef CONFIG_X86_MCE
  84. INTG(X86_TRAP_MC, asm_exc_machine_check),
  85. #endif
  86. SYSG(X86_TRAP_OF, asm_exc_overflow),
  87. #if defined(CONFIG_IA32_EMULATION)
  88. SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat),
  89. #elif defined(CONFIG_X86_32)
  90. SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32),
  91. #endif
  92. };
  93. /*
  94. * The APIC and SMP idt entries
  95. */
  96. static const __initconst struct idt_data apic_idts[] = {
  97. #ifdef CONFIG_SMP
  98. INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi),
  99. INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function),
  100. INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single),
  101. INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup),
  102. INTG(REBOOT_VECTOR, asm_sysvec_reboot),
  103. #endif
  104. #ifdef CONFIG_X86_THERMAL_VECTOR
  105. INTG(THERMAL_APIC_VECTOR, asm_sysvec_thermal),
  106. #endif
  107. #ifdef CONFIG_X86_MCE_THRESHOLD
  108. INTG(THRESHOLD_APIC_VECTOR, asm_sysvec_threshold),
  109. #endif
  110. #ifdef CONFIG_X86_MCE_AMD
  111. INTG(DEFERRED_ERROR_VECTOR, asm_sysvec_deferred_error),
  112. #endif
  113. #ifdef CONFIG_X86_LOCAL_APIC
  114. INTG(LOCAL_TIMER_VECTOR, asm_sysvec_apic_timer_interrupt),
  115. INTG(X86_PLATFORM_IPI_VECTOR, asm_sysvec_x86_platform_ipi),
  116. # ifdef CONFIG_HAVE_KVM
  117. INTG(POSTED_INTR_VECTOR, asm_sysvec_kvm_posted_intr_ipi),
  118. INTG(POSTED_INTR_WAKEUP_VECTOR, asm_sysvec_kvm_posted_intr_wakeup_ipi),
  119. INTG(POSTED_INTR_NESTED_VECTOR, asm_sysvec_kvm_posted_intr_nested_ipi),
  120. # endif
  121. # ifdef CONFIG_IRQ_WORK
  122. INTG(IRQ_WORK_VECTOR, asm_sysvec_irq_work),
  123. # endif
  124. INTG(SPURIOUS_APIC_VECTOR, asm_sysvec_spurious_apic_interrupt),
  125. INTG(ERROR_APIC_VECTOR, asm_sysvec_error_interrupt),
  126. #endif
  127. };
  128. /* Must be page-aligned because the real IDT is used in the cpu entry area */
  129. static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;
  130. static struct desc_ptr idt_descr __ro_after_init = {
  131. .size = IDT_TABLE_SIZE - 1,
  132. .address = (unsigned long) idt_table,
  133. };
  134. void load_current_idt(void)
  135. {
  136. lockdep_assert_irqs_disabled();
  137. load_idt(&idt_descr);
  138. }
  139. #ifdef CONFIG_X86_F00F_BUG
  140. bool idt_is_f00f_address(unsigned long address)
  141. {
  142. return ((address - idt_descr.address) >> 3) == 6;
  143. }
  144. #endif
  145. static __init void
  146. idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys)
  147. {
  148. gate_desc desc;
  149. for (; size > 0; t++, size--) {
  150. idt_init_desc(&desc, t);
  151. write_idt_entry(idt, t->vector, &desc);
  152. if (sys)
  153. set_bit(t->vector, system_vectors);
  154. }
  155. }
  156. static __init void set_intr_gate(unsigned int n, const void *addr)
  157. {
  158. struct idt_data data;
  159. init_idt_data(&data, n, addr);
  160. idt_setup_from_table(idt_table, &data, 1, false);
  161. }
  162. /**
  163. * idt_setup_early_traps - Initialize the idt table with early traps
  164. *
  165. * On X8664 these traps do not use interrupt stacks as they can't work
  166. * before cpu_init() is invoked and sets up TSS. The IST variants are
  167. * installed after that.
  168. */
  169. void __init idt_setup_early_traps(void)
  170. {
  171. idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts),
  172. true);
  173. load_idt(&idt_descr);
  174. }
  175. /**
  176. * idt_setup_traps - Initialize the idt table with default traps
  177. */
  178. void __init idt_setup_traps(void)
  179. {
  180. idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true);
  181. }
  182. #ifdef CONFIG_X86_64
  183. /*
  184. * Early traps running on the DEFAULT_STACK because the other interrupt
  185. * stacks work only after cpu_init().
  186. */
  187. static const __initconst struct idt_data early_pf_idts[] = {
  188. INTG(X86_TRAP_PF, asm_exc_page_fault),
  189. };
  190. /*
  191. * The exceptions which use Interrupt stacks. They are setup after
  192. * cpu_init() when the TSS has been initialized.
  193. */
  194. static const __initconst struct idt_data ist_idts[] = {
  195. ISTG(X86_TRAP_DB, asm_exc_debug, IST_INDEX_DB),
  196. ISTG(X86_TRAP_NMI, asm_exc_nmi, IST_INDEX_NMI),
  197. ISTG(X86_TRAP_DF, asm_exc_double_fault, IST_INDEX_DF),
  198. #ifdef CONFIG_X86_MCE
  199. ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE),
  200. #endif
  201. #ifdef CONFIG_AMD_MEM_ENCRYPT
  202. ISTG(X86_TRAP_VC, asm_exc_vmm_communication, IST_INDEX_VC),
  203. #endif
  204. };
  205. /**
  206. * idt_setup_early_pf - Initialize the idt table with early pagefault handler
  207. *
  208. * On X8664 this does not use interrupt stacks as they can't work before
  209. * cpu_init() is invoked and sets up TSS. The IST variant is installed
  210. * after that.
  211. *
  212. * Note, that X86_64 cannot install the real #PF handler in
  213. * idt_setup_early_traps() because the memory intialization needs the #PF
  214. * handler from the early_idt_handler_array to initialize the early page
  215. * tables.
  216. */
  217. void __init idt_setup_early_pf(void)
  218. {
  219. idt_setup_from_table(idt_table, early_pf_idts,
  220. ARRAY_SIZE(early_pf_idts), true);
  221. }
  222. /**
  223. * idt_setup_ist_traps - Initialize the idt table with traps using IST
  224. */
  225. void __init idt_setup_ist_traps(void)
  226. {
  227. idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts), true);
  228. }
  229. #endif
  230. static void __init idt_map_in_cea(void)
  231. {
  232. /*
  233. * Set the IDT descriptor to a fixed read-only location in the cpu
  234. * entry area, so that the "sidt" instruction will not leak the
  235. * location of the kernel, and to defend the IDT against arbitrary
  236. * memory write vulnerabilities.
  237. */
  238. cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
  239. PAGE_KERNEL_RO);
  240. idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
  241. }
  242. /**
  243. * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates
  244. */
  245. void __init idt_setup_apic_and_irq_gates(void)
  246. {
  247. int i = FIRST_EXTERNAL_VECTOR;
  248. void *entry;
  249. idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true);
  250. for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) {
  251. entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR);
  252. set_intr_gate(i, entry);
  253. }
  254. #ifdef CONFIG_X86_LOCAL_APIC
  255. for_each_clear_bit_from(i, system_vectors, NR_VECTORS) {
  256. /*
  257. * Don't set the non assigned system vectors in the
  258. * system_vectors bitmap. Otherwise they show up in
  259. * /proc/interrupts.
  260. */
  261. entry = spurious_entries_start + 8 * (i - FIRST_SYSTEM_VECTOR);
  262. set_intr_gate(i, entry);
  263. }
  264. #endif
  265. /* Map IDT into CPU entry area and reload it. */
  266. idt_map_in_cea();
  267. load_idt(&idt_descr);
  268. /* Make the IDT table read only */
  269. set_memory_ro((unsigned long)&idt_table, 1);
  270. idt_setup_done = true;
  271. }
  272. /**
  273. * idt_setup_early_handler - Initializes the idt table with early handlers
  274. */
  275. void __init idt_setup_early_handler(void)
  276. {
  277. int i;
  278. for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
  279. set_intr_gate(i, early_idt_handler_array[i]);
  280. #ifdef CONFIG_X86_32
  281. for ( ; i < NR_VECTORS; i++)
  282. set_intr_gate(i, early_ignore_irq);
  283. #endif
  284. load_idt(&idt_descr);
  285. }
  286. /**
  287. * idt_invalidate - Invalidate interrupt descriptor table
  288. * @addr: The virtual address of the 'invalid' IDT
  289. */
  290. void idt_invalidate(void *addr)
  291. {
  292. struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 };
  293. load_idt(&idt);
  294. }
  295. void __init alloc_intr_gate(unsigned int n, const void *addr)
  296. {
  297. if (WARN_ON(n < FIRST_SYSTEM_VECTOR))
  298. return;
  299. if (WARN_ON(idt_setup_done))
  300. return;
  301. if (!WARN_ON(test_and_set_bit(n, system_vectors)))
  302. set_intr_gate(n, addr);
  303. }