hpet.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include <linux/clockchips.h>
  3. #include <linux/interrupt.h>
  4. #include <linux/export.h>
  5. #include <linux/delay.h>
  6. #include <linux/hpet.h>
  7. #include <linux/cpu.h>
  8. #include <linux/irq.h>
  9. #include <asm/hpet.h>
  10. #include <asm/time.h>
  11. #include <asm/mwait.h>
  12. #undef pr_fmt
  13. #define pr_fmt(fmt) "hpet: " fmt
  14. enum hpet_mode {
  15. HPET_MODE_UNUSED,
  16. HPET_MODE_LEGACY,
  17. HPET_MODE_CLOCKEVT,
  18. HPET_MODE_DEVICE,
  19. };
  20. struct hpet_channel {
  21. struct clock_event_device evt;
  22. unsigned int num;
  23. unsigned int cpu;
  24. unsigned int irq;
  25. unsigned int in_use;
  26. enum hpet_mode mode;
  27. unsigned int boot_cfg;
  28. char name[10];
  29. };
  30. struct hpet_base {
  31. unsigned int nr_channels;
  32. unsigned int nr_clockevents;
  33. unsigned int boot_cfg;
  34. struct hpet_channel *channels;
  35. };
  36. #define HPET_MASK CLOCKSOURCE_MASK(32)
  37. #define HPET_MIN_CYCLES 128
  38. #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
  39. /*
  40. * HPET address is set in acpi/boot.c, when an ACPI entry exists
  41. */
  42. unsigned long hpet_address;
  43. u8 hpet_blockid; /* OS timer block num */
  44. bool hpet_msi_disable;
  45. #ifdef CONFIG_PCI_MSI
  46. static DEFINE_PER_CPU(struct hpet_channel *, cpu_hpet_channel);
  47. static struct irq_domain *hpet_domain;
  48. #endif
  49. static void __iomem *hpet_virt_address;
  50. static struct hpet_base hpet_base;
  51. static bool hpet_legacy_int_enabled;
  52. static unsigned long hpet_freq;
  53. bool boot_hpet_disable;
  54. bool hpet_force_user;
  55. static bool hpet_verbose;
  56. static inline
  57. struct hpet_channel *clockevent_to_channel(struct clock_event_device *evt)
  58. {
  59. return container_of(evt, struct hpet_channel, evt);
  60. }
  61. inline unsigned int hpet_readl(unsigned int a)
  62. {
  63. return readl(hpet_virt_address + a);
  64. }
  65. static inline void hpet_writel(unsigned int d, unsigned int a)
  66. {
  67. writel(d, hpet_virt_address + a);
  68. }
  69. static inline void hpet_set_mapping(void)
  70. {
  71. hpet_virt_address = ioremap(hpet_address, HPET_MMAP_SIZE);
  72. }
  73. static inline void hpet_clear_mapping(void)
  74. {
  75. iounmap(hpet_virt_address);
  76. hpet_virt_address = NULL;
  77. }
  78. /*
  79. * HPET command line enable / disable
  80. */
  81. static int __init hpet_setup(char *str)
  82. {
  83. while (str) {
  84. char *next = strchr(str, ',');
  85. if (next)
  86. *next++ = 0;
  87. if (!strncmp("disable", str, 7))
  88. boot_hpet_disable = true;
  89. if (!strncmp("force", str, 5))
  90. hpet_force_user = true;
  91. if (!strncmp("verbose", str, 7))
  92. hpet_verbose = true;
  93. str = next;
  94. }
  95. return 1;
  96. }
  97. __setup("hpet=", hpet_setup);
  98. static int __init disable_hpet(char *str)
  99. {
  100. boot_hpet_disable = true;
  101. return 1;
  102. }
  103. __setup("nohpet", disable_hpet);
  104. static inline int is_hpet_capable(void)
  105. {
  106. return !boot_hpet_disable && hpet_address;
  107. }
  108. /**
  109. * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
  110. */
  111. int is_hpet_enabled(void)
  112. {
  113. return is_hpet_capable() && hpet_legacy_int_enabled;
  114. }
  115. EXPORT_SYMBOL_GPL(is_hpet_enabled);
  116. static void _hpet_print_config(const char *function, int line)
  117. {
  118. u32 i, id, period, cfg, status, channels, l, h;
  119. pr_info("%s(%d):\n", function, line);
  120. id = hpet_readl(HPET_ID);
  121. period = hpet_readl(HPET_PERIOD);
  122. pr_info("ID: 0x%x, PERIOD: 0x%x\n", id, period);
  123. cfg = hpet_readl(HPET_CFG);
  124. status = hpet_readl(HPET_STATUS);
  125. pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status);
  126. l = hpet_readl(HPET_COUNTER);
  127. h = hpet_readl(HPET_COUNTER+4);
  128. pr_info("COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
  129. channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
  130. for (i = 0; i < channels; i++) {
  131. l = hpet_readl(HPET_Tn_CFG(i));
  132. h = hpet_readl(HPET_Tn_CFG(i)+4);
  133. pr_info("T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", i, l, h);
  134. l = hpet_readl(HPET_Tn_CMP(i));
  135. h = hpet_readl(HPET_Tn_CMP(i)+4);
  136. pr_info("T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", i, l, h);
  137. l = hpet_readl(HPET_Tn_ROUTE(i));
  138. h = hpet_readl(HPET_Tn_ROUTE(i)+4);
  139. pr_info("T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", i, l, h);
  140. }
  141. }
  142. #define hpet_print_config() \
  143. do { \
  144. if (hpet_verbose) \
  145. _hpet_print_config(__func__, __LINE__); \
  146. } while (0)
  147. /*
  148. * When the HPET driver (/dev/hpet) is enabled, we need to reserve
  149. * timer 0 and timer 1 in case of RTC emulation.
  150. */
  151. #ifdef CONFIG_HPET
  152. static void __init hpet_reserve_platform_timers(void)
  153. {
  154. struct hpet_data hd;
  155. unsigned int i;
  156. memset(&hd, 0, sizeof(hd));
  157. hd.hd_phys_address = hpet_address;
  158. hd.hd_address = hpet_virt_address;
  159. hd.hd_nirqs = hpet_base.nr_channels;
  160. /*
  161. * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
  162. * is wrong for i8259!) not the output IRQ. Many BIOS writers
  163. * don't bother configuring *any* comparator interrupts.
  164. */
  165. hd.hd_irq[0] = HPET_LEGACY_8254;
  166. hd.hd_irq[1] = HPET_LEGACY_RTC;
  167. for (i = 0; i < hpet_base.nr_channels; i++) {
  168. struct hpet_channel *hc = hpet_base.channels + i;
  169. if (i >= 2)
  170. hd.hd_irq[i] = hc->irq;
  171. switch (hc->mode) {
  172. case HPET_MODE_UNUSED:
  173. case HPET_MODE_DEVICE:
  174. hc->mode = HPET_MODE_DEVICE;
  175. break;
  176. case HPET_MODE_CLOCKEVT:
  177. case HPET_MODE_LEGACY:
  178. hpet_reserve_timer(&hd, hc->num);
  179. break;
  180. }
  181. }
  182. hpet_alloc(&hd);
  183. }
  184. static void __init hpet_select_device_channel(void)
  185. {
  186. int i;
  187. for (i = 0; i < hpet_base.nr_channels; i++) {
  188. struct hpet_channel *hc = hpet_base.channels + i;
  189. /* Associate the first unused channel to /dev/hpet */
  190. if (hc->mode == HPET_MODE_UNUSED) {
  191. hc->mode = HPET_MODE_DEVICE;
  192. return;
  193. }
  194. }
  195. }
  196. #else
  197. static inline void hpet_reserve_platform_timers(void) { }
  198. static inline void hpet_select_device_channel(void) {}
  199. #endif
  200. /* Common HPET functions */
  201. static void hpet_stop_counter(void)
  202. {
  203. u32 cfg = hpet_readl(HPET_CFG);
  204. cfg &= ~HPET_CFG_ENABLE;
  205. hpet_writel(cfg, HPET_CFG);
  206. }
  207. static void hpet_reset_counter(void)
  208. {
  209. hpet_writel(0, HPET_COUNTER);
  210. hpet_writel(0, HPET_COUNTER + 4);
  211. }
  212. static void hpet_start_counter(void)
  213. {
  214. unsigned int cfg = hpet_readl(HPET_CFG);
  215. cfg |= HPET_CFG_ENABLE;
  216. hpet_writel(cfg, HPET_CFG);
  217. }
  218. static void hpet_restart_counter(void)
  219. {
  220. hpet_stop_counter();
  221. hpet_reset_counter();
  222. hpet_start_counter();
  223. }
  224. static void hpet_resume_device(void)
  225. {
  226. force_hpet_resume();
  227. }
  228. static void hpet_resume_counter(struct clocksource *cs)
  229. {
  230. hpet_resume_device();
  231. hpet_restart_counter();
  232. }
  233. static void hpet_enable_legacy_int(void)
  234. {
  235. unsigned int cfg = hpet_readl(HPET_CFG);
  236. cfg |= HPET_CFG_LEGACY;
  237. hpet_writel(cfg, HPET_CFG);
  238. hpet_legacy_int_enabled = true;
  239. }
  240. static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt)
  241. {
  242. unsigned int channel = clockevent_to_channel(evt)->num;
  243. unsigned int cfg, cmp, now;
  244. uint64_t delta;
  245. hpet_stop_counter();
  246. delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
  247. delta >>= evt->shift;
  248. now = hpet_readl(HPET_COUNTER);
  249. cmp = now + (unsigned int)delta;
  250. cfg = hpet_readl(HPET_Tn_CFG(channel));
  251. cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
  252. HPET_TN_32BIT;
  253. hpet_writel(cfg, HPET_Tn_CFG(channel));
  254. hpet_writel(cmp, HPET_Tn_CMP(channel));
  255. udelay(1);
  256. /*
  257. * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
  258. * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
  259. * bit is automatically cleared after the first write.
  260. * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
  261. * Publication # 24674)
  262. */
  263. hpet_writel((unsigned int)delta, HPET_Tn_CMP(channel));
  264. hpet_start_counter();
  265. hpet_print_config();
  266. return 0;
  267. }
  268. static int hpet_clkevt_set_state_oneshot(struct clock_event_device *evt)
  269. {
  270. unsigned int channel = clockevent_to_channel(evt)->num;
  271. unsigned int cfg;
  272. cfg = hpet_readl(HPET_Tn_CFG(channel));
  273. cfg &= ~HPET_TN_PERIODIC;
  274. cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
  275. hpet_writel(cfg, HPET_Tn_CFG(channel));
  276. return 0;
  277. }
  278. static int hpet_clkevt_set_state_shutdown(struct clock_event_device *evt)
  279. {
  280. unsigned int channel = clockevent_to_channel(evt)->num;
  281. unsigned int cfg;
  282. cfg = hpet_readl(HPET_Tn_CFG(channel));
  283. cfg &= ~HPET_TN_ENABLE;
  284. hpet_writel(cfg, HPET_Tn_CFG(channel));
  285. return 0;
  286. }
  287. static int hpet_clkevt_legacy_resume(struct clock_event_device *evt)
  288. {
  289. hpet_enable_legacy_int();
  290. hpet_print_config();
  291. return 0;
  292. }
  293. static int
  294. hpet_clkevt_set_next_event(unsigned long delta, struct clock_event_device *evt)
  295. {
  296. unsigned int channel = clockevent_to_channel(evt)->num;
  297. u32 cnt;
  298. s32 res;
  299. cnt = hpet_readl(HPET_COUNTER);
  300. cnt += (u32) delta;
  301. hpet_writel(cnt, HPET_Tn_CMP(channel));
  302. /*
  303. * HPETs are a complete disaster. The compare register is
  304. * based on a equal comparison and neither provides a less
  305. * than or equal functionality (which would require to take
  306. * the wraparound into account) nor a simple count down event
  307. * mode. Further the write to the comparator register is
  308. * delayed internally up to two HPET clock cycles in certain
  309. * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
  310. * longer delays. We worked around that by reading back the
  311. * compare register, but that required another workaround for
  312. * ICH9,10 chips where the first readout after write can
  313. * return the old stale value. We already had a minimum
  314. * programming delta of 5us enforced, but a NMI or SMI hitting
  315. * between the counter readout and the comparator write can
  316. * move us behind that point easily. Now instead of reading
  317. * the compare register back several times, we make the ETIME
  318. * decision based on the following: Return ETIME if the
  319. * counter value after the write is less than HPET_MIN_CYCLES
  320. * away from the event or if the counter is already ahead of
  321. * the event. The minimum programming delta for the generic
  322. * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
  323. */
  324. res = (s32)(cnt - hpet_readl(HPET_COUNTER));
  325. return res < HPET_MIN_CYCLES ? -ETIME : 0;
  326. }
  327. static void hpet_init_clockevent(struct hpet_channel *hc, unsigned int rating)
  328. {
  329. struct clock_event_device *evt = &hc->evt;
  330. evt->rating = rating;
  331. evt->irq = hc->irq;
  332. evt->name = hc->name;
  333. evt->cpumask = cpumask_of(hc->cpu);
  334. evt->set_state_oneshot = hpet_clkevt_set_state_oneshot;
  335. evt->set_next_event = hpet_clkevt_set_next_event;
  336. evt->set_state_shutdown = hpet_clkevt_set_state_shutdown;
  337. evt->features = CLOCK_EVT_FEAT_ONESHOT;
  338. if (hc->boot_cfg & HPET_TN_PERIODIC) {
  339. evt->features |= CLOCK_EVT_FEAT_PERIODIC;
  340. evt->set_state_periodic = hpet_clkevt_set_state_periodic;
  341. }
  342. }
  343. static void __init hpet_legacy_clockevent_register(struct hpet_channel *hc)
  344. {
  345. /*
  346. * Start HPET with the boot CPU's cpumask and make it global after
  347. * the IO_APIC has been initialized.
  348. */
  349. hc->cpu = boot_cpu_data.cpu_index;
  350. strncpy(hc->name, "hpet", sizeof(hc->name));
  351. hpet_init_clockevent(hc, 50);
  352. hc->evt.tick_resume = hpet_clkevt_legacy_resume;
  353. /*
  354. * Legacy horrors and sins from the past. HPET used periodic mode
  355. * unconditionally forever on the legacy channel 0. Removing the
  356. * below hack and using the conditional in hpet_init_clockevent()
  357. * makes at least Qemu and one hardware machine fail to boot.
  358. * There are two issues which cause the boot failure:
  359. *
  360. * #1 After the timer delivery test in IOAPIC and the IOAPIC setup
  361. * the next interrupt is not delivered despite the HPET channel
  362. * being programmed correctly. Reprogramming the HPET after
  363. * switching to IOAPIC makes it work again. After fixing this,
  364. * the next issue surfaces:
  365. *
  366. * #2 Due to the unconditional periodic mode availability the Local
  367. * APIC timer calibration can hijack the global clockevents
  368. * event handler without causing damage. Using oneshot at this
  369. * stage makes if hang because the HPET does not get
  370. * reprogrammed due to the handler hijacking. Duh, stupid me!
  371. *
  372. * Both issues require major surgery and especially the kick HPET
  373. * again after enabling IOAPIC results in really nasty hackery.
  374. * This 'assume periodic works' magic has survived since HPET
  375. * support got added, so it's questionable whether this should be
  376. * fixed. Both Qemu and the failing hardware machine support
  377. * periodic mode despite the fact that both don't advertise it in
  378. * the configuration register and both need that extra kick after
  379. * switching to IOAPIC. Seems to be a feature...
  380. */
  381. hc->evt.features |= CLOCK_EVT_FEAT_PERIODIC;
  382. hc->evt.set_state_periodic = hpet_clkevt_set_state_periodic;
  383. /* Start HPET legacy interrupts */
  384. hpet_enable_legacy_int();
  385. clockevents_config_and_register(&hc->evt, hpet_freq,
  386. HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
  387. global_clock_event = &hc->evt;
  388. pr_debug("Clockevent registered\n");
  389. }
  390. /*
  391. * HPET MSI Support
  392. */
  393. #ifdef CONFIG_PCI_MSI
  394. void hpet_msi_unmask(struct irq_data *data)
  395. {
  396. struct hpet_channel *hc = irq_data_get_irq_handler_data(data);
  397. unsigned int cfg;
  398. cfg = hpet_readl(HPET_Tn_CFG(hc->num));
  399. cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
  400. hpet_writel(cfg, HPET_Tn_CFG(hc->num));
  401. }
  402. void hpet_msi_mask(struct irq_data *data)
  403. {
  404. struct hpet_channel *hc = irq_data_get_irq_handler_data(data);
  405. unsigned int cfg;
  406. cfg = hpet_readl(HPET_Tn_CFG(hc->num));
  407. cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
  408. hpet_writel(cfg, HPET_Tn_CFG(hc->num));
  409. }
  410. void hpet_msi_write(struct hpet_channel *hc, struct msi_msg *msg)
  411. {
  412. hpet_writel(msg->data, HPET_Tn_ROUTE(hc->num));
  413. hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hc->num) + 4);
  414. }
  415. static int hpet_clkevt_msi_resume(struct clock_event_device *evt)
  416. {
  417. struct hpet_channel *hc = clockevent_to_channel(evt);
  418. struct irq_data *data = irq_get_irq_data(hc->irq);
  419. struct msi_msg msg;
  420. /* Restore the MSI msg and unmask the interrupt */
  421. irq_chip_compose_msi_msg(data, &msg);
  422. hpet_msi_write(hc, &msg);
  423. hpet_msi_unmask(data);
  424. return 0;
  425. }
  426. static irqreturn_t hpet_msi_interrupt_handler(int irq, void *data)
  427. {
  428. struct hpet_channel *hc = data;
  429. struct clock_event_device *evt = &hc->evt;
  430. if (!evt->event_handler) {
  431. pr_info("Spurious interrupt HPET channel %d\n", hc->num);
  432. return IRQ_HANDLED;
  433. }
  434. evt->event_handler(evt);
  435. return IRQ_HANDLED;
  436. }
  437. static int hpet_setup_msi_irq(struct hpet_channel *hc)
  438. {
  439. if (request_irq(hc->irq, hpet_msi_interrupt_handler,
  440. IRQF_TIMER | IRQF_NOBALANCING,
  441. hc->name, hc))
  442. return -1;
  443. disable_irq(hc->irq);
  444. irq_set_affinity(hc->irq, cpumask_of(hc->cpu));
  445. enable_irq(hc->irq);
  446. pr_debug("%s irq %u for MSI\n", hc->name, hc->irq);
  447. return 0;
  448. }
  449. /* Invoked from the hotplug callback on @cpu */
  450. static void init_one_hpet_msi_clockevent(struct hpet_channel *hc, int cpu)
  451. {
  452. struct clock_event_device *evt = &hc->evt;
  453. hc->cpu = cpu;
  454. per_cpu(cpu_hpet_channel, cpu) = hc;
  455. hpet_setup_msi_irq(hc);
  456. hpet_init_clockevent(hc, 110);
  457. evt->tick_resume = hpet_clkevt_msi_resume;
  458. clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
  459. 0x7FFFFFFF);
  460. }
  461. static struct hpet_channel *hpet_get_unused_clockevent(void)
  462. {
  463. int i;
  464. for (i = 0; i < hpet_base.nr_channels; i++) {
  465. struct hpet_channel *hc = hpet_base.channels + i;
  466. if (hc->mode != HPET_MODE_CLOCKEVT || hc->in_use)
  467. continue;
  468. hc->in_use = 1;
  469. return hc;
  470. }
  471. return NULL;
  472. }
  473. static int hpet_cpuhp_online(unsigned int cpu)
  474. {
  475. struct hpet_channel *hc = hpet_get_unused_clockevent();
  476. if (hc)
  477. init_one_hpet_msi_clockevent(hc, cpu);
  478. return 0;
  479. }
  480. static int hpet_cpuhp_dead(unsigned int cpu)
  481. {
  482. struct hpet_channel *hc = per_cpu(cpu_hpet_channel, cpu);
  483. if (!hc)
  484. return 0;
  485. free_irq(hc->irq, hc);
  486. hc->in_use = 0;
  487. per_cpu(cpu_hpet_channel, cpu) = NULL;
  488. return 0;
  489. }
  490. static void __init hpet_select_clockevents(void)
  491. {
  492. unsigned int i;
  493. hpet_base.nr_clockevents = 0;
  494. /* No point if MSI is disabled or CPU has an Always Runing APIC Timer */
  495. if (hpet_msi_disable || boot_cpu_has(X86_FEATURE_ARAT))
  496. return;
  497. hpet_print_config();
  498. hpet_domain = hpet_create_irq_domain(hpet_blockid);
  499. if (!hpet_domain)
  500. return;
  501. for (i = 0; i < hpet_base.nr_channels; i++) {
  502. struct hpet_channel *hc = hpet_base.channels + i;
  503. int irq;
  504. if (hc->mode != HPET_MODE_UNUSED)
  505. continue;
  506. /* Only consider HPET channel with MSI support */
  507. if (!(hc->boot_cfg & HPET_TN_FSB_CAP))
  508. continue;
  509. sprintf(hc->name, "hpet%d", i);
  510. irq = hpet_assign_irq(hpet_domain, hc, hc->num);
  511. if (irq <= 0)
  512. continue;
  513. hc->irq = irq;
  514. hc->mode = HPET_MODE_CLOCKEVT;
  515. if (++hpet_base.nr_clockevents == num_possible_cpus())
  516. break;
  517. }
  518. pr_info("%d channels of %d reserved for per-cpu timers\n",
  519. hpet_base.nr_channels, hpet_base.nr_clockevents);
  520. }
  521. #else
  522. static inline void hpet_select_clockevents(void) { }
  523. #define hpet_cpuhp_online NULL
  524. #define hpet_cpuhp_dead NULL
  525. #endif
  526. /*
  527. * Clock source related code
  528. */
  529. #if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
  530. /*
  531. * Reading the HPET counter is a very slow operation. If a large number of
  532. * CPUs are trying to access the HPET counter simultaneously, it can cause
  533. * massive delays and slow down system performance dramatically. This may
  534. * happen when HPET is the default clock source instead of TSC. For a
  535. * really large system with hundreds of CPUs, the slowdown may be so
  536. * severe, that it can actually crash the system because of a NMI watchdog
  537. * soft lockup, for example.
  538. *
  539. * If multiple CPUs are trying to access the HPET counter at the same time,
  540. * we don't actually need to read the counter multiple times. Instead, the
  541. * other CPUs can use the counter value read by the first CPU in the group.
  542. *
  543. * This special feature is only enabled on x86-64 systems. It is unlikely
  544. * that 32-bit x86 systems will have enough CPUs to require this feature
  545. * with its associated locking overhead. We also need 64-bit atomic read.
  546. *
  547. * The lock and the HPET value are stored together and can be read in a
  548. * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
  549. * is 32 bits in size.
  550. */
  551. union hpet_lock {
  552. struct {
  553. arch_spinlock_t lock;
  554. u32 value;
  555. };
  556. u64 lockval;
  557. };
  558. static union hpet_lock hpet __cacheline_aligned = {
  559. { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
  560. };
  561. static u64 read_hpet(struct clocksource *cs)
  562. {
  563. unsigned long flags;
  564. union hpet_lock old, new;
  565. BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
  566. /*
  567. * Read HPET directly if in NMI.
  568. */
  569. if (in_nmi())
  570. return (u64)hpet_readl(HPET_COUNTER);
  571. /*
  572. * Read the current state of the lock and HPET value atomically.
  573. */
  574. old.lockval = READ_ONCE(hpet.lockval);
  575. if (arch_spin_is_locked(&old.lock))
  576. goto contended;
  577. local_irq_save(flags);
  578. if (arch_spin_trylock(&hpet.lock)) {
  579. new.value = hpet_readl(HPET_COUNTER);
  580. /*
  581. * Use WRITE_ONCE() to prevent store tearing.
  582. */
  583. WRITE_ONCE(hpet.value, new.value);
  584. arch_spin_unlock(&hpet.lock);
  585. local_irq_restore(flags);
  586. return (u64)new.value;
  587. }
  588. local_irq_restore(flags);
  589. contended:
  590. /*
  591. * Contended case
  592. * --------------
  593. * Wait until the HPET value change or the lock is free to indicate
  594. * its value is up-to-date.
  595. *
  596. * It is possible that old.value has already contained the latest
  597. * HPET value while the lock holder was in the process of releasing
  598. * the lock. Checking for lock state change will enable us to return
  599. * the value immediately instead of waiting for the next HPET reader
  600. * to come along.
  601. */
  602. do {
  603. cpu_relax();
  604. new.lockval = READ_ONCE(hpet.lockval);
  605. } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
  606. return (u64)new.value;
  607. }
  608. #else
  609. /*
  610. * For UP or 32-bit.
  611. */
  612. static u64 read_hpet(struct clocksource *cs)
  613. {
  614. return (u64)hpet_readl(HPET_COUNTER);
  615. }
  616. #endif
  617. static struct clocksource clocksource_hpet = {
  618. .name = "hpet",
  619. .rating = 250,
  620. .read = read_hpet,
  621. .mask = HPET_MASK,
  622. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  623. .resume = hpet_resume_counter,
  624. };
  625. /*
  626. * AMD SB700 based systems with spread spectrum enabled use a SMM based
  627. * HPET emulation to provide proper frequency setting.
  628. *
  629. * On such systems the SMM code is initialized with the first HPET register
  630. * access and takes some time to complete. During this time the config
  631. * register reads 0xffffffff. We check for max 1000 loops whether the
  632. * config register reads a non-0xffffffff value to make sure that the
  633. * HPET is up and running before we proceed any further.
  634. *
  635. * A counting loop is safe, as the HPET access takes thousands of CPU cycles.
  636. *
  637. * On non-SB700 based machines this check is only done once and has no
  638. * side effects.
  639. */
  640. static bool __init hpet_cfg_working(void)
  641. {
  642. int i;
  643. for (i = 0; i < 1000; i++) {
  644. if (hpet_readl(HPET_CFG) != 0xFFFFFFFF)
  645. return true;
  646. }
  647. pr_warn("Config register invalid. Disabling HPET\n");
  648. return false;
  649. }
  650. static bool __init hpet_counting(void)
  651. {
  652. u64 start, now, t1;
  653. hpet_restart_counter();
  654. t1 = hpet_readl(HPET_COUNTER);
  655. start = rdtsc();
  656. /*
  657. * We don't know the TSC frequency yet, but waiting for
  658. * 200000 TSC cycles is safe:
  659. * 4 GHz == 50us
  660. * 1 GHz == 200us
  661. */
  662. do {
  663. if (t1 != hpet_readl(HPET_COUNTER))
  664. return true;
  665. now = rdtsc();
  666. } while ((now - start) < 200000UL);
  667. pr_warn("Counter not counting. HPET disabled\n");
  668. return false;
  669. }
  670. static bool __init mwait_pc10_supported(void)
  671. {
  672. unsigned int eax, ebx, ecx, mwait_substates;
  673. if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
  674. return false;
  675. if (!cpu_feature_enabled(X86_FEATURE_MWAIT))
  676. return false;
  677. if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
  678. return false;
  679. cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
  680. return (ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) &&
  681. (ecx & CPUID5_ECX_INTERRUPT_BREAK) &&
  682. (mwait_substates & (0xF << 28));
  683. }
  684. /*
  685. * Check whether the system supports PC10. If so force disable HPET as that
  686. * stops counting in PC10. This check is overbroad as it does not take any
  687. * of the following into account:
  688. *
  689. * - ACPI tables
  690. * - Enablement of intel_idle
  691. * - Command line arguments which limit intel_idle C-state support
  692. *
  693. * That's perfectly fine. HPET is a piece of hardware designed by committee
  694. * and the only reasons why it is still in use on modern systems is the
  695. * fact that it is impossible to reliably query TSC and CPU frequency via
  696. * CPUID or firmware.
  697. *
  698. * If HPET is functional it is useful for calibrating TSC, but this can be
  699. * done via PMTIMER as well which seems to be the last remaining timer on
  700. * X86/INTEL platforms that has not been completely wreckaged by feature
  701. * creep.
  702. *
  703. * In theory HPET support should be removed altogether, but there are older
  704. * systems out there which depend on it because TSC and APIC timer are
  705. * dysfunctional in deeper C-states.
  706. *
  707. * It's only 20 years now that hardware people have been asked to provide
  708. * reliable and discoverable facilities which can be used for timekeeping
  709. * and per CPU timer interrupts.
  710. *
  711. * The probability that this problem is going to be solved in the
  712. * forseeable future is close to zero, so the kernel has to be cluttered
  713. * with heuristics to keep up with the ever growing amount of hardware and
  714. * firmware trainwrecks. Hopefully some day hardware people will understand
  715. * that the approach of "This can be fixed in software" is not sustainable.
  716. * Hope dies last...
  717. */
  718. static bool __init hpet_is_pc10_damaged(void)
  719. {
  720. unsigned long long pcfg;
  721. /* Check whether PC10 substates are supported */
  722. if (!mwait_pc10_supported())
  723. return false;
  724. /* Check whether PC10 is enabled in PKG C-state limit */
  725. rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, pcfg);
  726. if ((pcfg & 0xF) < 8)
  727. return false;
  728. if (hpet_force_user) {
  729. pr_warn("HPET force enabled via command line, but dysfunctional in PC10.\n");
  730. return false;
  731. }
  732. pr_info("HPET dysfunctional in PC10. Force disabled.\n");
  733. boot_hpet_disable = true;
  734. return true;
  735. }
  736. /**
  737. * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
  738. */
  739. int __init hpet_enable(void)
  740. {
  741. u32 hpet_period, cfg, id, irq;
  742. unsigned int i, channels;
  743. struct hpet_channel *hc;
  744. u64 freq;
  745. if (!is_hpet_capable())
  746. return 0;
  747. if (hpet_is_pc10_damaged())
  748. return 0;
  749. hpet_set_mapping();
  750. if (!hpet_virt_address)
  751. return 0;
  752. /* Validate that the config register is working */
  753. if (!hpet_cfg_working())
  754. goto out_nohpet;
  755. /*
  756. * Read the period and check for a sane value:
  757. */
  758. hpet_period = hpet_readl(HPET_PERIOD);
  759. if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
  760. goto out_nohpet;
  761. /* The period is a femtoseconds value. Convert it to a frequency. */
  762. freq = FSEC_PER_SEC;
  763. do_div(freq, hpet_period);
  764. hpet_freq = freq;
  765. /*
  766. * Read the HPET ID register to retrieve the IRQ routing
  767. * information and the number of channels
  768. */
  769. id = hpet_readl(HPET_ID);
  770. hpet_print_config();
  771. /* This is the HPET channel number which is zero based */
  772. channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
  773. /*
  774. * The legacy routing mode needs at least two channels, tick timer
  775. * and the rtc emulation channel.
  776. */
  777. if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC) && channels < 2)
  778. goto out_nohpet;
  779. hc = kcalloc(channels, sizeof(*hc), GFP_KERNEL);
  780. if (!hc) {
  781. pr_warn("Disabling HPET.\n");
  782. goto out_nohpet;
  783. }
  784. hpet_base.channels = hc;
  785. hpet_base.nr_channels = channels;
  786. /* Read, store and sanitize the global configuration */
  787. cfg = hpet_readl(HPET_CFG);
  788. hpet_base.boot_cfg = cfg;
  789. cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
  790. hpet_writel(cfg, HPET_CFG);
  791. if (cfg)
  792. pr_warn("Global config: Unknown bits %#x\n", cfg);
  793. /* Read, store and sanitize the per channel configuration */
  794. for (i = 0; i < channels; i++, hc++) {
  795. hc->num = i;
  796. cfg = hpet_readl(HPET_Tn_CFG(i));
  797. hc->boot_cfg = cfg;
  798. irq = (cfg & Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
  799. hc->irq = irq;
  800. cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
  801. hpet_writel(cfg, HPET_Tn_CFG(i));
  802. cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
  803. | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
  804. | HPET_TN_FSB | HPET_TN_FSB_CAP);
  805. if (cfg)
  806. pr_warn("Channel #%u config: Unknown bits %#x\n", i, cfg);
  807. }
  808. hpet_print_config();
  809. /*
  810. * Validate that the counter is counting. This needs to be done
  811. * after sanitizing the config registers to properly deal with
  812. * force enabled HPETs.
  813. */
  814. if (!hpet_counting())
  815. goto out_nohpet;
  816. clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
  817. if (id & HPET_ID_LEGSUP) {
  818. hpet_legacy_clockevent_register(&hpet_base.channels[0]);
  819. hpet_base.channels[0].mode = HPET_MODE_LEGACY;
  820. if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC))
  821. hpet_base.channels[1].mode = HPET_MODE_LEGACY;
  822. return 1;
  823. }
  824. return 0;
  825. out_nohpet:
  826. kfree(hpet_base.channels);
  827. hpet_base.channels = NULL;
  828. hpet_base.nr_channels = 0;
  829. hpet_clear_mapping();
  830. hpet_address = 0;
  831. return 0;
  832. }
  833. /*
  834. * The late initialization runs after the PCI quirks have been invoked
  835. * which might have detected a system on which the HPET can be enforced.
  836. *
  837. * Also, the MSI machinery is not working yet when the HPET is initialized
  838. * early.
  839. *
  840. * If the HPET is enabled, then:
  841. *
  842. * 1) Reserve one channel for /dev/hpet if CONFIG_HPET=y
  843. * 2) Reserve up to num_possible_cpus() channels as per CPU clockevents
  844. * 3) Setup /dev/hpet if CONFIG_HPET=y
  845. * 4) Register hotplug callbacks when clockevents are available
  846. */
  847. static __init int hpet_late_init(void)
  848. {
  849. int ret;
  850. if (!hpet_address) {
  851. if (!force_hpet_address)
  852. return -ENODEV;
  853. hpet_address = force_hpet_address;
  854. hpet_enable();
  855. }
  856. if (!hpet_virt_address)
  857. return -ENODEV;
  858. hpet_select_device_channel();
  859. hpet_select_clockevents();
  860. hpet_reserve_platform_timers();
  861. hpet_print_config();
  862. if (!hpet_base.nr_clockevents)
  863. return 0;
  864. ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online",
  865. hpet_cpuhp_online, NULL);
  866. if (ret)
  867. return ret;
  868. ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL,
  869. hpet_cpuhp_dead);
  870. if (ret)
  871. goto err_cpuhp;
  872. return 0;
  873. err_cpuhp:
  874. cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
  875. return ret;
  876. }
  877. fs_initcall(hpet_late_init);
  878. void hpet_disable(void)
  879. {
  880. unsigned int i;
  881. u32 cfg;
  882. if (!is_hpet_capable() || !hpet_virt_address)
  883. return;
  884. /* Restore boot configuration with the enable bit cleared */
  885. cfg = hpet_base.boot_cfg;
  886. cfg &= ~HPET_CFG_ENABLE;
  887. hpet_writel(cfg, HPET_CFG);
  888. /* Restore the channel boot configuration */
  889. for (i = 0; i < hpet_base.nr_channels; i++)
  890. hpet_writel(hpet_base.channels[i].boot_cfg, HPET_Tn_CFG(i));
  891. /* If the HPET was enabled at boot time, reenable it */
  892. if (hpet_base.boot_cfg & HPET_CFG_ENABLE)
  893. hpet_writel(hpet_base.boot_cfg, HPET_CFG);
  894. }
  895. #ifdef CONFIG_HPET_EMULATE_RTC
  896. /*
  897. * HPET in LegacyReplacement mode eats up the RTC interrupt line. When HPET
  898. * is enabled, we support RTC interrupt functionality in software.
  899. *
  900. * RTC has 3 kinds of interrupts:
  901. *
  902. * 1) Update Interrupt - generate an interrupt, every second, when the
  903. * RTC clock is updated
  904. * 2) Alarm Interrupt - generate an interrupt at a specific time of day
  905. * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
  906. * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all frequencies in powers of 2)
  907. *
  908. * (1) and (2) above are implemented using polling at a frequency of 64 Hz:
  909. * DEFAULT_RTC_INT_FREQ.
  910. *
  911. * The exact frequency is a tradeoff between accuracy and interrupt overhead.
  912. *
  913. * For (3), we use interrupts at 64 Hz, or the user specified periodic frequency,
  914. * if it's higher.
  915. */
  916. #include <linux/mc146818rtc.h>
  917. #include <linux/rtc.h>
  918. #define DEFAULT_RTC_INT_FREQ 64
  919. #define DEFAULT_RTC_SHIFT 6
  920. #define RTC_NUM_INTS 1
  921. static unsigned long hpet_rtc_flags;
  922. static int hpet_prev_update_sec;
  923. static struct rtc_time hpet_alarm_time;
  924. static unsigned long hpet_pie_count;
  925. static u32 hpet_t1_cmp;
  926. static u32 hpet_default_delta;
  927. static u32 hpet_pie_delta;
  928. static unsigned long hpet_pie_limit;
  929. static rtc_irq_handler irq_handler;
  930. /*
  931. * Check that the HPET counter c1 is ahead of c2
  932. */
  933. static inline int hpet_cnt_ahead(u32 c1, u32 c2)
  934. {
  935. return (s32)(c2 - c1) < 0;
  936. }
  937. /*
  938. * Registers a IRQ handler.
  939. */
  940. int hpet_register_irq_handler(rtc_irq_handler handler)
  941. {
  942. if (!is_hpet_enabled())
  943. return -ENODEV;
  944. if (irq_handler)
  945. return -EBUSY;
  946. irq_handler = handler;
  947. return 0;
  948. }
  949. EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
  950. /*
  951. * Deregisters the IRQ handler registered with hpet_register_irq_handler()
  952. * and does cleanup.
  953. */
  954. void hpet_unregister_irq_handler(rtc_irq_handler handler)
  955. {
  956. if (!is_hpet_enabled())
  957. return;
  958. irq_handler = NULL;
  959. hpet_rtc_flags = 0;
  960. }
  961. EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
  962. /*
  963. * Channel 1 for RTC emulation. We use one shot mode, as periodic mode
  964. * is not supported by all HPET implementations for channel 1.
  965. *
  966. * hpet_rtc_timer_init() is called when the rtc is initialized.
  967. */
  968. int hpet_rtc_timer_init(void)
  969. {
  970. unsigned int cfg, cnt, delta;
  971. unsigned long flags;
  972. if (!is_hpet_enabled())
  973. return 0;
  974. if (!hpet_default_delta) {
  975. struct clock_event_device *evt = &hpet_base.channels[0].evt;
  976. uint64_t clc;
  977. clc = (uint64_t) evt->mult * NSEC_PER_SEC;
  978. clc >>= evt->shift + DEFAULT_RTC_SHIFT;
  979. hpet_default_delta = clc;
  980. }
  981. if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
  982. delta = hpet_default_delta;
  983. else
  984. delta = hpet_pie_delta;
  985. local_irq_save(flags);
  986. cnt = delta + hpet_readl(HPET_COUNTER);
  987. hpet_writel(cnt, HPET_T1_CMP);
  988. hpet_t1_cmp = cnt;
  989. cfg = hpet_readl(HPET_T1_CFG);
  990. cfg &= ~HPET_TN_PERIODIC;
  991. cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
  992. hpet_writel(cfg, HPET_T1_CFG);
  993. local_irq_restore(flags);
  994. return 1;
  995. }
  996. EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
  997. static void hpet_disable_rtc_channel(void)
  998. {
  999. u32 cfg = hpet_readl(HPET_T1_CFG);
  1000. cfg &= ~HPET_TN_ENABLE;
  1001. hpet_writel(cfg, HPET_T1_CFG);
  1002. }
  1003. /*
  1004. * The functions below are called from rtc driver.
  1005. * Return 0 if HPET is not being used.
  1006. * Otherwise do the necessary changes and return 1.
  1007. */
  1008. int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
  1009. {
  1010. if (!is_hpet_enabled())
  1011. return 0;
  1012. hpet_rtc_flags &= ~bit_mask;
  1013. if (unlikely(!hpet_rtc_flags))
  1014. hpet_disable_rtc_channel();
  1015. return 1;
  1016. }
  1017. EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
  1018. int hpet_set_rtc_irq_bit(unsigned long bit_mask)
  1019. {
  1020. unsigned long oldbits = hpet_rtc_flags;
  1021. if (!is_hpet_enabled())
  1022. return 0;
  1023. hpet_rtc_flags |= bit_mask;
  1024. if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
  1025. hpet_prev_update_sec = -1;
  1026. if (!oldbits)
  1027. hpet_rtc_timer_init();
  1028. return 1;
  1029. }
  1030. EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
  1031. int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
  1032. {
  1033. if (!is_hpet_enabled())
  1034. return 0;
  1035. hpet_alarm_time.tm_hour = hrs;
  1036. hpet_alarm_time.tm_min = min;
  1037. hpet_alarm_time.tm_sec = sec;
  1038. return 1;
  1039. }
  1040. EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
  1041. int hpet_set_periodic_freq(unsigned long freq)
  1042. {
  1043. uint64_t clc;
  1044. if (!is_hpet_enabled())
  1045. return 0;
  1046. if (freq <= DEFAULT_RTC_INT_FREQ) {
  1047. hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
  1048. } else {
  1049. struct clock_event_device *evt = &hpet_base.channels[0].evt;
  1050. clc = (uint64_t) evt->mult * NSEC_PER_SEC;
  1051. do_div(clc, freq);
  1052. clc >>= evt->shift;
  1053. hpet_pie_delta = clc;
  1054. hpet_pie_limit = 0;
  1055. }
  1056. return 1;
  1057. }
  1058. EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
  1059. int hpet_rtc_dropped_irq(void)
  1060. {
  1061. return is_hpet_enabled();
  1062. }
  1063. EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
  1064. static void hpet_rtc_timer_reinit(void)
  1065. {
  1066. unsigned int delta;
  1067. int lost_ints = -1;
  1068. if (unlikely(!hpet_rtc_flags))
  1069. hpet_disable_rtc_channel();
  1070. if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
  1071. delta = hpet_default_delta;
  1072. else
  1073. delta = hpet_pie_delta;
  1074. /*
  1075. * Increment the comparator value until we are ahead of the
  1076. * current count.
  1077. */
  1078. do {
  1079. hpet_t1_cmp += delta;
  1080. hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
  1081. lost_ints++;
  1082. } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
  1083. if (lost_ints) {
  1084. if (hpet_rtc_flags & RTC_PIE)
  1085. hpet_pie_count += lost_ints;
  1086. if (printk_ratelimit())
  1087. pr_warn("Lost %d RTC interrupts\n", lost_ints);
  1088. }
  1089. }
  1090. irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
  1091. {
  1092. struct rtc_time curr_time;
  1093. unsigned long rtc_int_flag = 0;
  1094. hpet_rtc_timer_reinit();
  1095. memset(&curr_time, 0, sizeof(struct rtc_time));
  1096. if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
  1097. mc146818_get_time(&curr_time);
  1098. if (hpet_rtc_flags & RTC_UIE &&
  1099. curr_time.tm_sec != hpet_prev_update_sec) {
  1100. if (hpet_prev_update_sec >= 0)
  1101. rtc_int_flag = RTC_UF;
  1102. hpet_prev_update_sec = curr_time.tm_sec;
  1103. }
  1104. if (hpet_rtc_flags & RTC_PIE && ++hpet_pie_count >= hpet_pie_limit) {
  1105. rtc_int_flag |= RTC_PF;
  1106. hpet_pie_count = 0;
  1107. }
  1108. if (hpet_rtc_flags & RTC_AIE &&
  1109. (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
  1110. (curr_time.tm_min == hpet_alarm_time.tm_min) &&
  1111. (curr_time.tm_hour == hpet_alarm_time.tm_hour))
  1112. rtc_int_flag |= RTC_AF;
  1113. if (rtc_int_flag) {
  1114. rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
  1115. if (irq_handler)
  1116. irq_handler(rtc_int_flag, dev_id);
  1117. }
  1118. return IRQ_HANDLED;
  1119. }
  1120. EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
  1121. #endif