head_64.S 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
  4. *
  5. * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
  6. * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
  7. * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
  8. * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
  9. * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
  10. */
  11. #include <linux/linkage.h>
  12. #include <linux/threads.h>
  13. #include <linux/init.h>
  14. #include <linux/pgtable.h>
  15. #include <asm/segment.h>
  16. #include <asm/page.h>
  17. #include <asm/msr.h>
  18. #include <asm/cache.h>
  19. #include <asm/processor-flags.h>
  20. #include <asm/percpu.h>
  21. #include <asm/nops.h>
  22. #include "../entry/calling.h"
  23. #include <asm/export.h>
  24. #include <asm/nospec-branch.h>
  25. #include <asm/fixmap.h>
  26. #ifdef CONFIG_PARAVIRT_XXL
  27. #include <asm/asm-offsets.h>
  28. #include <asm/paravirt.h>
  29. #define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg
  30. #else
  31. #define INTERRUPT_RETURN iretq
  32. #define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg
  33. #endif
  34. /*
  35. * We are not able to switch in one step to the final KERNEL ADDRESS SPACE
  36. * because we need identity-mapped pages.
  37. */
  38. #define l4_index(x) (((x) >> 39) & 511)
  39. #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
  40. L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
  41. L4_START_KERNEL = l4_index(__START_KERNEL_map)
  42. L3_START_KERNEL = pud_index(__START_KERNEL_map)
  43. .text
  44. __HEAD
  45. .code64
  46. SYM_CODE_START_NOALIGN(startup_64)
  47. UNWIND_HINT_EMPTY
  48. /*
  49. * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
  50. * and someone has loaded an identity mapped page table
  51. * for us. These identity mapped page tables map all of the
  52. * kernel pages and possibly all of memory.
  53. *
  54. * %rsi holds a physical pointer to real_mode_data.
  55. *
  56. * We come here either directly from a 64bit bootloader, or from
  57. * arch/x86/boot/compressed/head_64.S.
  58. *
  59. * We only come here initially at boot nothing else comes here.
  60. *
  61. * Since we may be loaded at an address different from what we were
  62. * compiled to run at we first fixup the physical addresses in our page
  63. * tables and then reload them.
  64. */
  65. /* Set up the stack for verify_cpu(), similar to initial_stack below */
  66. leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp
  67. leaq _text(%rip), %rdi
  68. pushq %rsi
  69. call startup_64_setup_env
  70. popq %rsi
  71. /* Now switch to __KERNEL_CS so IRET works reliably */
  72. pushq $__KERNEL_CS
  73. leaq .Lon_kernel_cs(%rip), %rax
  74. pushq %rax
  75. lretq
  76. .Lon_kernel_cs:
  77. UNWIND_HINT_EMPTY
  78. /* Sanitize CPU configuration */
  79. call verify_cpu
  80. /*
  81. * Perform pagetable fixups. Additionally, if SME is active, encrypt
  82. * the kernel and retrieve the modifier (SME encryption mask if SME
  83. * is active) to be added to the initial pgdir entry that will be
  84. * programmed into CR3.
  85. */
  86. leaq _text(%rip), %rdi
  87. pushq %rsi
  88. call __startup_64
  89. popq %rsi
  90. /* Form the CR3 value being sure to include the CR3 modifier */
  91. addq $(early_top_pgt - __START_KERNEL_map), %rax
  92. jmp 1f
  93. SYM_CODE_END(startup_64)
  94. SYM_CODE_START(secondary_startup_64)
  95. UNWIND_HINT_EMPTY
  96. /*
  97. * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
  98. * and someone has loaded a mapped page table.
  99. *
  100. * %rsi holds a physical pointer to real_mode_data.
  101. *
  102. * We come here either from startup_64 (using physical addresses)
  103. * or from trampoline.S (using virtual addresses).
  104. *
  105. * Using virtual addresses from trampoline.S removes the need
  106. * to have any identity mapped pages in the kernel page table
  107. * after the boot processor executes this code.
  108. */
  109. /* Sanitize CPU configuration */
  110. call verify_cpu
  111. /*
  112. * The secondary_startup_64_no_verify entry point is only used by
  113. * SEV-ES guests. In those guests the call to verify_cpu() would cause
  114. * #VC exceptions which can not be handled at this stage of secondary
  115. * CPU bringup.
  116. *
  117. * All non SEV-ES systems, especially Intel systems, need to execute
  118. * verify_cpu() above to make sure NX is enabled.
  119. */
  120. SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
  121. UNWIND_HINT_EMPTY
  122. /*
  123. * Retrieve the modifier (SME encryption mask if SME is active) to be
  124. * added to the initial pgdir entry that will be programmed into CR3.
  125. */
  126. pushq %rsi
  127. call __startup_secondary_64
  128. popq %rsi
  129. /* Form the CR3 value being sure to include the CR3 modifier */
  130. addq $(init_top_pgt - __START_KERNEL_map), %rax
  131. 1:
  132. /* Enable PAE mode, PGE and LA57 */
  133. movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
  134. #ifdef CONFIG_X86_5LEVEL
  135. testl $1, __pgtable_l5_enabled(%rip)
  136. jz 1f
  137. orl $X86_CR4_LA57, %ecx
  138. 1:
  139. #endif
  140. movq %rcx, %cr4
  141. /* Setup early boot stage 4-/5-level pagetables. */
  142. addq phys_base(%rip), %rax
  143. /*
  144. * For SEV guests: Verify that the C-bit is correct. A malicious
  145. * hypervisor could lie about the C-bit position to perform a ROP
  146. * attack on the guest by writing to the unencrypted stack and wait for
  147. * the next RET instruction.
  148. * %rsi carries pointer to realmode data and is callee-clobbered. Save
  149. * and restore it.
  150. */
  151. pushq %rsi
  152. movq %rax, %rdi
  153. call sev_verify_cbit
  154. popq %rsi
  155. /* Switch to new page-table */
  156. movq %rax, %cr3
  157. /* Ensure I am executing from virtual addresses */
  158. movq $1f, %rax
  159. ANNOTATE_RETPOLINE_SAFE
  160. jmp *%rax
  161. 1:
  162. UNWIND_HINT_EMPTY
  163. /*
  164. * We must switch to a new descriptor in kernel space for the GDT
  165. * because soon the kernel won't have access anymore to the userspace
  166. * addresses where we're currently running on. We have to do that here
  167. * because in 32bit we couldn't load a 64bit linear address.
  168. */
  169. lgdt early_gdt_descr(%rip)
  170. /* set up data segments */
  171. xorl %eax,%eax
  172. movl %eax,%ds
  173. movl %eax,%ss
  174. movl %eax,%es
  175. /*
  176. * We don't really need to load %fs or %gs, but load them anyway
  177. * to kill any stale realmode selectors. This allows execution
  178. * under VT hardware.
  179. */
  180. movl %eax,%fs
  181. movl %eax,%gs
  182. /* Set up %gs.
  183. *
  184. * The base of %gs always points to fixed_percpu_data. If the
  185. * stack protector canary is enabled, it is located at %gs:40.
  186. * Note that, on SMP, the boot cpu uses init data section until
  187. * the per cpu areas are set up.
  188. */
  189. movl $MSR_GS_BASE,%ecx
  190. movl initial_gs(%rip),%eax
  191. movl initial_gs+4(%rip),%edx
  192. wrmsr
  193. /*
  194. * Setup a boot time stack - Any secondary CPU will have lost its stack
  195. * by now because the cr3-switch above unmaps the real-mode stack
  196. */
  197. movq initial_stack(%rip), %rsp
  198. /* Setup and Load IDT */
  199. pushq %rsi
  200. call early_setup_idt
  201. popq %rsi
  202. /* Check if nx is implemented */
  203. movl $0x80000001, %eax
  204. cpuid
  205. movl %edx,%edi
  206. /* Setup EFER (Extended Feature Enable Register) */
  207. movl $MSR_EFER, %ecx
  208. rdmsr
  209. btsl $_EFER_SCE, %eax /* Enable System Call */
  210. btl $20,%edi /* No Execute supported? */
  211. jnc 1f
  212. btsl $_EFER_NX, %eax
  213. btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
  214. 1: wrmsr /* Make changes effective */
  215. /* Setup cr0 */
  216. movl $CR0_STATE, %eax
  217. /* Make changes effective */
  218. movq %rax, %cr0
  219. /* zero EFLAGS after setting rsp */
  220. pushq $0
  221. popfq
  222. /* rsi is pointer to real mode structure with interesting info.
  223. pass it to C */
  224. movq %rsi, %rdi
  225. .Ljump_to_C_code:
  226. /*
  227. * Jump to run C code and to be on a real kernel address.
  228. * Since we are running on identity-mapped space we have to jump
  229. * to the full 64bit address, this is only possible as indirect
  230. * jump. In addition we need to ensure %cs is set so we make this
  231. * a far return.
  232. *
  233. * Note: do not change to far jump indirect with 64bit offset.
  234. *
  235. * AMD does not support far jump indirect with 64bit offset.
  236. * AMD64 Architecture Programmer's Manual, Volume 3: states only
  237. * JMP FAR mem16:16 FF /5 Far jump indirect,
  238. * with the target specified by a far pointer in memory.
  239. * JMP FAR mem16:32 FF /5 Far jump indirect,
  240. * with the target specified by a far pointer in memory.
  241. *
  242. * Intel64 does support 64bit offset.
  243. * Software Developer Manual Vol 2: states:
  244. * FF /5 JMP m16:16 Jump far, absolute indirect,
  245. * address given in m16:16
  246. * FF /5 JMP m16:32 Jump far, absolute indirect,
  247. * address given in m16:32.
  248. * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
  249. * address given in m16:64.
  250. */
  251. pushq $.Lafter_lret # put return address on stack for unwinder
  252. xorl %ebp, %ebp # clear frame pointer
  253. movq initial_code(%rip), %rax
  254. pushq $__KERNEL_CS # set correct cs
  255. pushq %rax # target address in negative space
  256. lretq
  257. .Lafter_lret:
  258. SYM_CODE_END(secondary_startup_64)
  259. #include "verify_cpu.S"
  260. #include "sev_verify_cbit.S"
  261. #ifdef CONFIG_HOTPLUG_CPU
  262. /*
  263. * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
  264. * up already except stack. We just set up stack here. Then call
  265. * start_secondary() via .Ljump_to_C_code.
  266. */
  267. SYM_CODE_START(start_cpu0)
  268. UNWIND_HINT_EMPTY
  269. movq initial_stack(%rip), %rsp
  270. jmp .Ljump_to_C_code
  271. SYM_CODE_END(start_cpu0)
  272. #endif
  273. #ifdef CONFIG_AMD_MEM_ENCRYPT
  274. /*
  275. * VC Exception handler used during early boot when running on kernel
  276. * addresses, but before the switch to the idt_table can be made.
  277. * The early_idt_handler_array can't be used here because it calls into a lot
  278. * of __init code and this handler is also used during CPU offlining/onlining.
  279. * Therefore this handler ends up in the .text section so that it stays around
  280. * when .init.text is freed.
  281. */
  282. SYM_CODE_START_NOALIGN(vc_boot_ghcb)
  283. UNWIND_HINT_IRET_REGS offset=8
  284. /* Build pt_regs */
  285. PUSH_AND_CLEAR_REGS
  286. /* Call C handler */
  287. movq %rsp, %rdi
  288. movq ORIG_RAX(%rsp), %rsi
  289. movq initial_vc_handler(%rip), %rax
  290. ANNOTATE_RETPOLINE_SAFE
  291. call *%rax
  292. /* Unwind pt_regs */
  293. POP_REGS
  294. /* Remove Error Code */
  295. addq $8, %rsp
  296. /* Pure iret required here - don't use INTERRUPT_RETURN */
  297. iretq
  298. SYM_CODE_END(vc_boot_ghcb)
  299. #endif
  300. /* Both SMP bootup and ACPI suspend change these variables */
  301. __REFDATA
  302. .balign 8
  303. SYM_DATA(initial_code, .quad x86_64_start_kernel)
  304. SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data))
  305. #ifdef CONFIG_AMD_MEM_ENCRYPT
  306. SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb)
  307. #endif
  308. /*
  309. * The SIZEOF_PTREGS gap is a convention which helps the in-kernel unwinder
  310. * reliably detect the end of the stack.
  311. */
  312. SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS)
  313. __FINITDATA
  314. __INIT
  315. SYM_CODE_START(early_idt_handler_array)
  316. i = 0
  317. .rept NUM_EXCEPTION_VECTORS
  318. .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
  319. UNWIND_HINT_IRET_REGS
  320. pushq $0 # Dummy error code, to make stack frame uniform
  321. .else
  322. UNWIND_HINT_IRET_REGS offset=8
  323. .endif
  324. pushq $i # 72(%rsp) Vector number
  325. jmp early_idt_handler_common
  326. UNWIND_HINT_IRET_REGS
  327. i = i + 1
  328. .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
  329. .endr
  330. UNWIND_HINT_IRET_REGS offset=16
  331. SYM_CODE_END(early_idt_handler_array)
  332. SYM_CODE_START_LOCAL(early_idt_handler_common)
  333. /*
  334. * The stack is the hardware frame, an error code or zero, and the
  335. * vector number.
  336. */
  337. cld
  338. incl early_recursion_flag(%rip)
  339. /* The vector number is currently in the pt_regs->di slot. */
  340. pushq %rsi /* pt_regs->si */
  341. movq 8(%rsp), %rsi /* RSI = vector number */
  342. movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
  343. pushq %rdx /* pt_regs->dx */
  344. pushq %rcx /* pt_regs->cx */
  345. pushq %rax /* pt_regs->ax */
  346. pushq %r8 /* pt_regs->r8 */
  347. pushq %r9 /* pt_regs->r9 */
  348. pushq %r10 /* pt_regs->r10 */
  349. pushq %r11 /* pt_regs->r11 */
  350. pushq %rbx /* pt_regs->bx */
  351. pushq %rbp /* pt_regs->bp */
  352. pushq %r12 /* pt_regs->r12 */
  353. pushq %r13 /* pt_regs->r13 */
  354. pushq %r14 /* pt_regs->r14 */
  355. pushq %r15 /* pt_regs->r15 */
  356. UNWIND_HINT_REGS
  357. movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
  358. call do_early_exception
  359. decl early_recursion_flag(%rip)
  360. jmp restore_regs_and_return_to_kernel
  361. SYM_CODE_END(early_idt_handler_common)
  362. #ifdef CONFIG_AMD_MEM_ENCRYPT
  363. /*
  364. * VC Exception handler used during very early boot. The
  365. * early_idt_handler_array can't be used because it returns via the
  366. * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early.
  367. *
  368. * This handler will end up in the .init.text section and not be
  369. * available to boot secondary CPUs.
  370. */
  371. SYM_CODE_START_NOALIGN(vc_no_ghcb)
  372. UNWIND_HINT_IRET_REGS offset=8
  373. /* Build pt_regs */
  374. PUSH_AND_CLEAR_REGS
  375. /* Call C handler */
  376. movq %rsp, %rdi
  377. movq ORIG_RAX(%rsp), %rsi
  378. call do_vc_no_ghcb
  379. /* Unwind pt_regs */
  380. POP_REGS
  381. /* Remove Error Code */
  382. addq $8, %rsp
  383. /* Pure iret required here - don't use INTERRUPT_RETURN */
  384. iretq
  385. SYM_CODE_END(vc_no_ghcb)
  386. #endif
  387. #define SYM_DATA_START_PAGE_ALIGNED(name) \
  388. SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE)
  389. #ifdef CONFIG_PAGE_TABLE_ISOLATION
  390. /*
  391. * Each PGD needs to be 8k long and 8k aligned. We do not
  392. * ever go out to userspace with these, so we do not
  393. * strictly *need* the second page, but this allows us to
  394. * have a single set_pgd() implementation that does not
  395. * need to worry about whether it has 4k or 8k to work
  396. * with.
  397. *
  398. * This ensures PGDs are 8k long:
  399. */
  400. #define PTI_USER_PGD_FILL 512
  401. /* This ensures they are 8k-aligned: */
  402. #define SYM_DATA_START_PTI_ALIGNED(name) \
  403. SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE)
  404. #else
  405. #define SYM_DATA_START_PTI_ALIGNED(name) \
  406. SYM_DATA_START_PAGE_ALIGNED(name)
  407. #define PTI_USER_PGD_FILL 0
  408. #endif
  409. /* Automate the creation of 1 to 1 mapping pmd entries */
  410. #define PMDS(START, PERM, COUNT) \
  411. i = 0 ; \
  412. .rept (COUNT) ; \
  413. .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
  414. i = i + 1 ; \
  415. .endr
  416. __INITDATA
  417. .balign 4
  418. SYM_DATA_START_PTI_ALIGNED(early_top_pgt)
  419. .fill 512,8,0
  420. .fill PTI_USER_PGD_FILL,8,0
  421. SYM_DATA_END(early_top_pgt)
  422. SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts)
  423. .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
  424. SYM_DATA_END(early_dynamic_pgts)
  425. SYM_DATA(early_recursion_flag, .long 0)
  426. .data
  427. #if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH)
  428. SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
  429. .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
  430. .org init_top_pgt + L4_PAGE_OFFSET*8, 0
  431. .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
  432. .org init_top_pgt + L4_START_KERNEL*8, 0
  433. /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
  434. .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
  435. .fill PTI_USER_PGD_FILL,8,0
  436. SYM_DATA_END(init_top_pgt)
  437. SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt)
  438. .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
  439. .fill 511, 8, 0
  440. SYM_DATA_END(level3_ident_pgt)
  441. SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt)
  442. /*
  443. * Since I easily can, map the first 1G.
  444. * Don't set NX because code runs from these pages.
  445. *
  446. * Note: This sets _PAGE_GLOBAL despite whether
  447. * the CPU supports it or it is enabled. But,
  448. * the CPU should ignore the bit.
  449. */
  450. PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
  451. SYM_DATA_END(level2_ident_pgt)
  452. #else
  453. SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
  454. .fill 512,8,0
  455. .fill PTI_USER_PGD_FILL,8,0
  456. SYM_DATA_END(init_top_pgt)
  457. #endif
  458. #ifdef CONFIG_X86_5LEVEL
  459. SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt)
  460. .fill 511,8,0
  461. .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
  462. SYM_DATA_END(level4_kernel_pgt)
  463. #endif
  464. SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt)
  465. .fill L3_START_KERNEL,8,0
  466. /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
  467. .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
  468. .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
  469. SYM_DATA_END(level3_kernel_pgt)
  470. SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt)
  471. /*
  472. * 512 MB kernel mapping. We spend a full page on this pagetable
  473. * anyway.
  474. *
  475. * The kernel code+data+bss must not be bigger than that.
  476. *
  477. * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
  478. * If you want to increase this then increase MODULES_VADDR
  479. * too.)
  480. *
  481. * This table is eventually used by the kernel during normal
  482. * runtime. Care must be taken to clear out undesired bits
  483. * later, like _PAGE_RW or _PAGE_GLOBAL in some cases.
  484. */
  485. PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
  486. KERNEL_IMAGE_SIZE/PMD_SIZE)
  487. SYM_DATA_END(level2_kernel_pgt)
  488. SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt)
  489. .fill (512 - 4 - FIXMAP_PMD_NUM),8,0
  490. pgtno = 0
  491. .rept (FIXMAP_PMD_NUM)
  492. .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
  493. + _PAGE_TABLE_NOENC;
  494. pgtno = pgtno + 1
  495. .endr
  496. /* 6 MB reserved space + a 2MB hole */
  497. .fill 4,8,0
  498. SYM_DATA_END(level2_fixmap_pgt)
  499. SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt)
  500. .rept (FIXMAP_PMD_NUM)
  501. .fill 512,8,0
  502. .endr
  503. SYM_DATA_END(level1_fixmap_pgt)
  504. #undef PMDS
  505. .data
  506. .align 16
  507. SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1)
  508. SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page))
  509. .align 16
  510. /* This must match the first entry in level2_kernel_pgt */
  511. SYM_DATA(phys_base, .quad 0x0)
  512. EXPORT_SYMBOL(phys_base)
  513. #include "../../x86/xen/xen-head.S"
  514. __PAGE_ALIGNED_BSS
  515. SYM_DATA_START_PAGE_ALIGNED(empty_zero_page)
  516. .skip PAGE_SIZE
  517. SYM_DATA_END(empty_zero_page)
  518. EXPORT_SYMBOL(empty_zero_page)