early-quirks.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806
  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Various workarounds for chipset bugs.
  3. This code runs very early and can't use the regular PCI subsystem
  4. The entries are keyed to PCI bridges which usually identify chipsets
  5. uniquely.
  6. This is only for whole classes of chipsets with specific problems which
  7. need early invasive action (e.g. before the timers are initialized).
  8. Most PCI device specific workarounds can be done later and should be
  9. in standard PCI quirks
  10. Mainboard specific bugs should be handled by DMI entries.
  11. CPU specific bugs in setup.c */
  12. #include <linux/pci.h>
  13. #include <linux/acpi.h>
  14. #include <linux/delay.h>
  15. #include <linux/pci_ids.h>
  16. #include <linux/bcma/bcma.h>
  17. #include <linux/bcma/bcma_regs.h>
  18. #include <linux/platform_data/x86/apple.h>
  19. #include <drm/i915_drm.h>
  20. #include <asm/pci-direct.h>
  21. #include <asm/dma.h>
  22. #include <asm/io_apic.h>
  23. #include <asm/apic.h>
  24. #include <asm/hpet.h>
  25. #include <asm/iommu.h>
  26. #include <asm/gart.h>
  27. #include <asm/irq_remapping.h>
  28. #include <asm/early_ioremap.h>
  29. static void __init fix_hypertransport_config(int num, int slot, int func)
  30. {
  31. u32 htcfg;
  32. /*
  33. * we found a hypertransport bus
  34. * make sure that we are broadcasting
  35. * interrupts to all cpus on the ht bus
  36. * if we're using extended apic ids
  37. */
  38. htcfg = read_pci_config(num, slot, func, 0x68);
  39. if (htcfg & (1 << 18)) {
  40. printk(KERN_INFO "Detected use of extended apic ids "
  41. "on hypertransport bus\n");
  42. if ((htcfg & (1 << 17)) == 0) {
  43. printk(KERN_INFO "Enabling hypertransport extended "
  44. "apic interrupt broadcast\n");
  45. printk(KERN_INFO "Note this is a bios bug, "
  46. "please contact your hw vendor\n");
  47. htcfg |= (1 << 17);
  48. write_pci_config(num, slot, func, 0x68, htcfg);
  49. }
  50. }
  51. }
  52. static void __init via_bugs(int num, int slot, int func)
  53. {
  54. #ifdef CONFIG_GART_IOMMU
  55. if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
  56. !gart_iommu_aperture_allowed) {
  57. printk(KERN_INFO
  58. "Looks like a VIA chipset. Disabling IOMMU."
  59. " Override with iommu=allowed\n");
  60. gart_iommu_aperture_disabled = 1;
  61. }
  62. #endif
  63. }
  64. #ifdef CONFIG_ACPI
  65. #ifdef CONFIG_X86_IO_APIC
  66. static int __init nvidia_hpet_check(struct acpi_table_header *header)
  67. {
  68. return 0;
  69. }
  70. #endif /* CONFIG_X86_IO_APIC */
  71. #endif /* CONFIG_ACPI */
  72. static void __init nvidia_bugs(int num, int slot, int func)
  73. {
  74. #ifdef CONFIG_ACPI
  75. #ifdef CONFIG_X86_IO_APIC
  76. /*
  77. * Only applies to Nvidia root ports (bus 0) and not to
  78. * Nvidia graphics cards with PCI ports on secondary buses.
  79. */
  80. if (num)
  81. return;
  82. /*
  83. * All timer overrides on Nvidia are
  84. * wrong unless HPET is enabled.
  85. * Unfortunately that's not true on many Asus boards.
  86. * We don't know yet how to detect this automatically, but
  87. * at least allow a command line override.
  88. */
  89. if (acpi_use_timer_override)
  90. return;
  91. if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
  92. acpi_skip_timer_override = 1;
  93. printk(KERN_INFO "Nvidia board "
  94. "detected. Ignoring ACPI "
  95. "timer override.\n");
  96. printk(KERN_INFO "If you got timer trouble "
  97. "try acpi_use_timer_override\n");
  98. }
  99. #endif
  100. #endif
  101. /* RED-PEN skip them on mptables too? */
  102. }
  103. #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
  104. static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
  105. {
  106. u32 d;
  107. u8 b;
  108. b = read_pci_config_byte(num, slot, func, 0xac);
  109. b &= ~(1<<5);
  110. write_pci_config_byte(num, slot, func, 0xac, b);
  111. d = read_pci_config(num, slot, func, 0x70);
  112. d |= 1<<8;
  113. write_pci_config(num, slot, func, 0x70, d);
  114. d = read_pci_config(num, slot, func, 0x8);
  115. d &= 0xff;
  116. return d;
  117. }
  118. static void __init ati_bugs(int num, int slot, int func)
  119. {
  120. u32 d;
  121. u8 b;
  122. if (acpi_use_timer_override)
  123. return;
  124. d = ati_ixp4x0_rev(num, slot, func);
  125. if (d < 0x82)
  126. acpi_skip_timer_override = 1;
  127. else {
  128. /* check for IRQ0 interrupt swap */
  129. outb(0x72, 0xcd6); b = inb(0xcd7);
  130. if (!(b & 0x2))
  131. acpi_skip_timer_override = 1;
  132. }
  133. if (acpi_skip_timer_override) {
  134. printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
  135. printk(KERN_INFO "Ignoring ACPI timer override.\n");
  136. printk(KERN_INFO "If you got timer trouble "
  137. "try acpi_use_timer_override\n");
  138. }
  139. }
  140. static u32 __init ati_sbx00_rev(int num, int slot, int func)
  141. {
  142. u32 d;
  143. d = read_pci_config(num, slot, func, 0x8);
  144. d &= 0xff;
  145. return d;
  146. }
  147. static void __init ati_bugs_contd(int num, int slot, int func)
  148. {
  149. u32 d, rev;
  150. rev = ati_sbx00_rev(num, slot, func);
  151. if (rev >= 0x40)
  152. acpi_fix_pin2_polarity = 1;
  153. /*
  154. * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
  155. * SB700: revisions 0x39, 0x3a, ...
  156. * SB800: revisions 0x40, 0x41, ...
  157. */
  158. if (rev >= 0x39)
  159. return;
  160. if (acpi_use_timer_override)
  161. return;
  162. /* check for IRQ0 interrupt swap */
  163. d = read_pci_config(num, slot, func, 0x64);
  164. if (!(d & (1<<14)))
  165. acpi_skip_timer_override = 1;
  166. if (acpi_skip_timer_override) {
  167. printk(KERN_INFO "SB600 revision 0x%x\n", rev);
  168. printk(KERN_INFO "Ignoring ACPI timer override.\n");
  169. printk(KERN_INFO "If you got timer trouble "
  170. "try acpi_use_timer_override\n");
  171. }
  172. }
  173. #else
  174. static void __init ati_bugs(int num, int slot, int func)
  175. {
  176. }
  177. static void __init ati_bugs_contd(int num, int slot, int func)
  178. {
  179. }
  180. #endif
  181. static void __init intel_remapping_check(int num, int slot, int func)
  182. {
  183. u8 revision;
  184. u16 device;
  185. device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
  186. revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
  187. /*
  188. * Revision <= 13 of all triggering devices id in this quirk
  189. * have a problem draining interrupts when irq remapping is
  190. * enabled, and should be flagged as broken. Additionally
  191. * revision 0x22 of device id 0x3405 has this problem.
  192. */
  193. if (revision <= 0x13)
  194. set_irq_remapping_broken();
  195. else if (device == 0x3405 && revision == 0x22)
  196. set_irq_remapping_broken();
  197. }
  198. /*
  199. * Systems with Intel graphics controllers set aside memory exclusively
  200. * for gfx driver use. This memory is not marked in the E820 as reserved
  201. * or as RAM, and so is subject to overlap from E820 manipulation later
  202. * in the boot process. On some systems, MMIO space is allocated on top,
  203. * despite the efforts of the "RAM buffer" approach, which simply rounds
  204. * memory boundaries up to 64M to try to catch space that may decode
  205. * as RAM and so is not suitable for MMIO.
  206. */
  207. #define KB(x) ((x) * 1024UL)
  208. #define MB(x) (KB (KB (x)))
  209. static resource_size_t __init i830_tseg_size(void)
  210. {
  211. u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
  212. if (!(esmramc & TSEG_ENABLE))
  213. return 0;
  214. if (esmramc & I830_TSEG_SIZE_1M)
  215. return MB(1);
  216. else
  217. return KB(512);
  218. }
  219. static resource_size_t __init i845_tseg_size(void)
  220. {
  221. u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
  222. u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
  223. if (!(esmramc & TSEG_ENABLE))
  224. return 0;
  225. switch (tseg_size) {
  226. case I845_TSEG_SIZE_512K: return KB(512);
  227. case I845_TSEG_SIZE_1M: return MB(1);
  228. default:
  229. WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc);
  230. }
  231. return 0;
  232. }
  233. static resource_size_t __init i85x_tseg_size(void)
  234. {
  235. u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
  236. if (!(esmramc & TSEG_ENABLE))
  237. return 0;
  238. return MB(1);
  239. }
  240. static resource_size_t __init i830_mem_size(void)
  241. {
  242. return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
  243. }
  244. static resource_size_t __init i85x_mem_size(void)
  245. {
  246. return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
  247. }
  248. /*
  249. * On 830/845/85x the stolen memory base isn't available in any
  250. * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
  251. */
  252. static resource_size_t __init i830_stolen_base(int num, int slot, int func,
  253. resource_size_t stolen_size)
  254. {
  255. return i830_mem_size() - i830_tseg_size() - stolen_size;
  256. }
  257. static resource_size_t __init i845_stolen_base(int num, int slot, int func,
  258. resource_size_t stolen_size)
  259. {
  260. return i830_mem_size() - i845_tseg_size() - stolen_size;
  261. }
  262. static resource_size_t __init i85x_stolen_base(int num, int slot, int func,
  263. resource_size_t stolen_size)
  264. {
  265. return i85x_mem_size() - i85x_tseg_size() - stolen_size;
  266. }
  267. static resource_size_t __init i865_stolen_base(int num, int slot, int func,
  268. resource_size_t stolen_size)
  269. {
  270. u16 toud = 0;
  271. toud = read_pci_config_16(0, 0, 0, I865_TOUD);
  272. return toud * KB(64) + i845_tseg_size();
  273. }
  274. static resource_size_t __init gen3_stolen_base(int num, int slot, int func,
  275. resource_size_t stolen_size)
  276. {
  277. u32 bsm;
  278. /* Almost universally we can find the Graphics Base of Stolen Memory
  279. * at register BSM (0x5c) in the igfx configuration space. On a few
  280. * (desktop) machines this is also mirrored in the bridge device at
  281. * different locations, or in the MCHBAR.
  282. */
  283. bsm = read_pci_config(num, slot, func, INTEL_BSM);
  284. return bsm & INTEL_BSM_MASK;
  285. }
  286. static resource_size_t __init gen11_stolen_base(int num, int slot, int func,
  287. resource_size_t stolen_size)
  288. {
  289. u64 bsm;
  290. bsm = read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW0);
  291. bsm &= INTEL_BSM_MASK;
  292. bsm |= (u64)read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW1) << 32;
  293. return bsm;
  294. }
  295. static resource_size_t __init i830_stolen_size(int num, int slot, int func)
  296. {
  297. u16 gmch_ctrl;
  298. u16 gms;
  299. gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
  300. gms = gmch_ctrl & I830_GMCH_GMS_MASK;
  301. switch (gms) {
  302. case I830_GMCH_GMS_STOLEN_512: return KB(512);
  303. case I830_GMCH_GMS_STOLEN_1024: return MB(1);
  304. case I830_GMCH_GMS_STOLEN_8192: return MB(8);
  305. /* local memory isn't part of the normal address space */
  306. case I830_GMCH_GMS_LOCAL: return 0;
  307. default:
  308. WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
  309. }
  310. return 0;
  311. }
  312. static resource_size_t __init gen3_stolen_size(int num, int slot, int func)
  313. {
  314. u16 gmch_ctrl;
  315. u16 gms;
  316. gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
  317. gms = gmch_ctrl & I855_GMCH_GMS_MASK;
  318. switch (gms) {
  319. case I855_GMCH_GMS_STOLEN_1M: return MB(1);
  320. case I855_GMCH_GMS_STOLEN_4M: return MB(4);
  321. case I855_GMCH_GMS_STOLEN_8M: return MB(8);
  322. case I855_GMCH_GMS_STOLEN_16M: return MB(16);
  323. case I855_GMCH_GMS_STOLEN_32M: return MB(32);
  324. case I915_GMCH_GMS_STOLEN_48M: return MB(48);
  325. case I915_GMCH_GMS_STOLEN_64M: return MB(64);
  326. case G33_GMCH_GMS_STOLEN_128M: return MB(128);
  327. case G33_GMCH_GMS_STOLEN_256M: return MB(256);
  328. case INTEL_GMCH_GMS_STOLEN_96M: return MB(96);
  329. case INTEL_GMCH_GMS_STOLEN_160M:return MB(160);
  330. case INTEL_GMCH_GMS_STOLEN_224M:return MB(224);
  331. case INTEL_GMCH_GMS_STOLEN_352M:return MB(352);
  332. default:
  333. WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
  334. }
  335. return 0;
  336. }
  337. static resource_size_t __init gen6_stolen_size(int num, int slot, int func)
  338. {
  339. u16 gmch_ctrl;
  340. u16 gms;
  341. gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
  342. gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
  343. return gms * MB(32);
  344. }
  345. static resource_size_t __init gen8_stolen_size(int num, int slot, int func)
  346. {
  347. u16 gmch_ctrl;
  348. u16 gms;
  349. gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
  350. gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
  351. return gms * MB(32);
  352. }
  353. static resource_size_t __init chv_stolen_size(int num, int slot, int func)
  354. {
  355. u16 gmch_ctrl;
  356. u16 gms;
  357. gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
  358. gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
  359. /*
  360. * 0x0 to 0x10: 32MB increments starting at 0MB
  361. * 0x11 to 0x16: 4MB increments starting at 8MB
  362. * 0x17 to 0x1d: 4MB increments start at 36MB
  363. */
  364. if (gms < 0x11)
  365. return gms * MB(32);
  366. else if (gms < 0x17)
  367. return (gms - 0x11) * MB(4) + MB(8);
  368. else
  369. return (gms - 0x17) * MB(4) + MB(36);
  370. }
  371. static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
  372. {
  373. u16 gmch_ctrl;
  374. u16 gms;
  375. gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
  376. gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
  377. /* 0x0 to 0xef: 32MB increments starting at 0MB */
  378. /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
  379. if (gms < 0xf0)
  380. return gms * MB(32);
  381. else
  382. return (gms - 0xf0) * MB(4) + MB(4);
  383. }
  384. struct intel_early_ops {
  385. resource_size_t (*stolen_size)(int num, int slot, int func);
  386. resource_size_t (*stolen_base)(int num, int slot, int func,
  387. resource_size_t size);
  388. };
  389. static const struct intel_early_ops i830_early_ops __initconst = {
  390. .stolen_base = i830_stolen_base,
  391. .stolen_size = i830_stolen_size,
  392. };
  393. static const struct intel_early_ops i845_early_ops __initconst = {
  394. .stolen_base = i845_stolen_base,
  395. .stolen_size = i830_stolen_size,
  396. };
  397. static const struct intel_early_ops i85x_early_ops __initconst = {
  398. .stolen_base = i85x_stolen_base,
  399. .stolen_size = gen3_stolen_size,
  400. };
  401. static const struct intel_early_ops i865_early_ops __initconst = {
  402. .stolen_base = i865_stolen_base,
  403. .stolen_size = gen3_stolen_size,
  404. };
  405. static const struct intel_early_ops gen3_early_ops __initconst = {
  406. .stolen_base = gen3_stolen_base,
  407. .stolen_size = gen3_stolen_size,
  408. };
  409. static const struct intel_early_ops gen6_early_ops __initconst = {
  410. .stolen_base = gen3_stolen_base,
  411. .stolen_size = gen6_stolen_size,
  412. };
  413. static const struct intel_early_ops gen8_early_ops __initconst = {
  414. .stolen_base = gen3_stolen_base,
  415. .stolen_size = gen8_stolen_size,
  416. };
  417. static const struct intel_early_ops gen9_early_ops __initconst = {
  418. .stolen_base = gen3_stolen_base,
  419. .stolen_size = gen9_stolen_size,
  420. };
  421. static const struct intel_early_ops chv_early_ops __initconst = {
  422. .stolen_base = gen3_stolen_base,
  423. .stolen_size = chv_stolen_size,
  424. };
  425. static const struct intel_early_ops gen11_early_ops __initconst = {
  426. .stolen_base = gen11_stolen_base,
  427. .stolen_size = gen9_stolen_size,
  428. };
  429. /* Intel integrated GPUs for which we need to reserve "stolen memory" */
  430. static const struct pci_device_id intel_early_ids[] __initconst = {
  431. INTEL_I830_IDS(&i830_early_ops),
  432. INTEL_I845G_IDS(&i845_early_ops),
  433. INTEL_I85X_IDS(&i85x_early_ops),
  434. INTEL_I865G_IDS(&i865_early_ops),
  435. INTEL_I915G_IDS(&gen3_early_ops),
  436. INTEL_I915GM_IDS(&gen3_early_ops),
  437. INTEL_I945G_IDS(&gen3_early_ops),
  438. INTEL_I945GM_IDS(&gen3_early_ops),
  439. INTEL_VLV_IDS(&gen6_early_ops),
  440. INTEL_PINEVIEW_G_IDS(&gen3_early_ops),
  441. INTEL_PINEVIEW_M_IDS(&gen3_early_ops),
  442. INTEL_I965G_IDS(&gen3_early_ops),
  443. INTEL_G33_IDS(&gen3_early_ops),
  444. INTEL_I965GM_IDS(&gen3_early_ops),
  445. INTEL_GM45_IDS(&gen3_early_ops),
  446. INTEL_G45_IDS(&gen3_early_ops),
  447. INTEL_IRONLAKE_D_IDS(&gen3_early_ops),
  448. INTEL_IRONLAKE_M_IDS(&gen3_early_ops),
  449. INTEL_SNB_D_IDS(&gen6_early_ops),
  450. INTEL_SNB_M_IDS(&gen6_early_ops),
  451. INTEL_IVB_M_IDS(&gen6_early_ops),
  452. INTEL_IVB_D_IDS(&gen6_early_ops),
  453. INTEL_HSW_IDS(&gen6_early_ops),
  454. INTEL_BDW_IDS(&gen8_early_ops),
  455. INTEL_CHV_IDS(&chv_early_ops),
  456. INTEL_SKL_IDS(&gen9_early_ops),
  457. INTEL_BXT_IDS(&gen9_early_ops),
  458. INTEL_KBL_IDS(&gen9_early_ops),
  459. INTEL_CFL_IDS(&gen9_early_ops),
  460. INTEL_GLK_IDS(&gen9_early_ops),
  461. INTEL_CNL_IDS(&gen9_early_ops),
  462. INTEL_ICL_11_IDS(&gen11_early_ops),
  463. INTEL_EHL_IDS(&gen11_early_ops),
  464. INTEL_TGL_12_IDS(&gen11_early_ops),
  465. INTEL_RKL_IDS(&gen11_early_ops),
  466. };
  467. struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
  468. EXPORT_SYMBOL(intel_graphics_stolen_res);
  469. static void __init
  470. intel_graphics_stolen(int num, int slot, int func,
  471. const struct intel_early_ops *early_ops)
  472. {
  473. resource_size_t base, size;
  474. resource_size_t end;
  475. size = early_ops->stolen_size(num, slot, func);
  476. base = early_ops->stolen_base(num, slot, func, size);
  477. if (!size || !base)
  478. return;
  479. end = base + size - 1;
  480. intel_graphics_stolen_res.start = base;
  481. intel_graphics_stolen_res.end = end;
  482. printk(KERN_INFO "Reserving Intel graphics memory at %pR\n",
  483. &intel_graphics_stolen_res);
  484. /* Mark this space as reserved */
  485. e820__range_add(base, size, E820_TYPE_RESERVED);
  486. e820__update_table(e820_table);
  487. }
  488. static void __init intel_graphics_quirks(int num, int slot, int func)
  489. {
  490. const struct intel_early_ops *early_ops;
  491. u16 device;
  492. int i;
  493. /*
  494. * Reserve "stolen memory" for an integrated GPU. If we've already
  495. * found one, there's nothing to do for other (discrete) GPUs.
  496. */
  497. if (resource_size(&intel_graphics_stolen_res))
  498. return;
  499. device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
  500. for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) {
  501. kernel_ulong_t driver_data = intel_early_ids[i].driver_data;
  502. if (intel_early_ids[i].device != device)
  503. continue;
  504. early_ops = (typeof(early_ops))driver_data;
  505. intel_graphics_stolen(num, slot, func, early_ops);
  506. return;
  507. }
  508. }
  509. static void __init force_disable_hpet(int num, int slot, int func)
  510. {
  511. #ifdef CONFIG_HPET_TIMER
  512. boot_hpet_disable = true;
  513. pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
  514. #endif
  515. }
  516. #define BCM4331_MMIO_SIZE 16384
  517. #define BCM4331_PM_CAP 0x40
  518. #define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
  519. #define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
  520. static void __init apple_airport_reset(int bus, int slot, int func)
  521. {
  522. void __iomem *mmio;
  523. u16 pmcsr;
  524. u64 addr;
  525. int i;
  526. if (!x86_apple_machine)
  527. return;
  528. /* Card may have been put into PCI_D3hot by grub quirk */
  529. pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
  530. if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
  531. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  532. write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);
  533. mdelay(10);
  534. pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
  535. if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
  536. pr_err("pci 0000:%02x:%02x.%d: Cannot power up Apple AirPort card\n",
  537. bus, slot, func);
  538. return;
  539. }
  540. }
  541. addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
  542. addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;
  543. addr &= PCI_BASE_ADDRESS_MEM_MASK;
  544. mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
  545. if (!mmio) {
  546. pr_err("pci 0000:%02x:%02x.%d: Cannot iomap Apple AirPort card\n",
  547. bus, slot, func);
  548. return;
  549. }
  550. pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");
  551. for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)
  552. udelay(10);
  553. bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
  554. bcma_aread32(BCMA_RESET_CTL);
  555. udelay(1);
  556. bcma_awrite32(BCMA_RESET_CTL, 0);
  557. bcma_aread32(BCMA_RESET_CTL);
  558. udelay(10);
  559. early_iounmap(mmio, BCM4331_MMIO_SIZE);
  560. }
  561. #define QFLAG_APPLY_ONCE 0x1
  562. #define QFLAG_APPLIED 0x2
  563. #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
  564. struct chipset {
  565. u32 vendor;
  566. u32 device;
  567. u32 class;
  568. u32 class_mask;
  569. u32 flags;
  570. void (*f)(int num, int slot, int func);
  571. };
  572. static struct chipset early_qrk[] __initdata = {
  573. { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
  574. PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
  575. { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
  576. PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
  577. { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
  578. PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
  579. { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
  580. PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
  581. { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
  582. PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
  583. { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
  584. PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
  585. { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
  586. PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
  587. { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
  588. PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
  589. { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
  590. 0, intel_graphics_quirks },
  591. /*
  592. * HPET on the current version of the Baytrail platform has accuracy
  593. * problems: it will halt in deep idle state - so we disable it.
  594. *
  595. * More details can be found in section 18.10.1.3 of the datasheet:
  596. *
  597. * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
  598. */
  599. { PCI_VENDOR_ID_INTEL, 0x0f00,
  600. PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
  601. { PCI_VENDOR_ID_BROADCOM, 0x4331,
  602. PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
  603. {}
  604. };
  605. static void __init early_pci_scan_bus(int bus);
  606. /**
  607. * check_dev_quirk - apply early quirks to a given PCI device
  608. * @num: bus number
  609. * @slot: slot number
  610. * @func: PCI function
  611. *
  612. * Check the vendor & device ID against the early quirks table.
  613. *
  614. * If the device is single function, let early_pci_scan_bus() know so we don't
  615. * poke at this device again.
  616. */
  617. static int __init check_dev_quirk(int num, int slot, int func)
  618. {
  619. u16 class;
  620. u16 vendor;
  621. u16 device;
  622. u8 type;
  623. u8 sec;
  624. int i;
  625. class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
  626. if (class == 0xffff)
  627. return -1; /* no class, treat as single function */
  628. vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
  629. device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
  630. for (i = 0; early_qrk[i].f != NULL; i++) {
  631. if (((early_qrk[i].vendor == PCI_ANY_ID) ||
  632. (early_qrk[i].vendor == vendor)) &&
  633. ((early_qrk[i].device == PCI_ANY_ID) ||
  634. (early_qrk[i].device == device)) &&
  635. (!((early_qrk[i].class ^ class) &
  636. early_qrk[i].class_mask))) {
  637. if ((early_qrk[i].flags &
  638. QFLAG_DONE) != QFLAG_DONE)
  639. early_qrk[i].f(num, slot, func);
  640. early_qrk[i].flags |= QFLAG_APPLIED;
  641. }
  642. }
  643. type = read_pci_config_byte(num, slot, func,
  644. PCI_HEADER_TYPE);
  645. if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
  646. sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
  647. if (sec > num)
  648. early_pci_scan_bus(sec);
  649. }
  650. if (!(type & 0x80))
  651. return -1;
  652. return 0;
  653. }
  654. static void __init early_pci_scan_bus(int bus)
  655. {
  656. int slot, func;
  657. /* Poor man's PCI discovery */
  658. for (slot = 0; slot < 32; slot++)
  659. for (func = 0; func < 8; func++) {
  660. /* Only probe function 0 on single fn devices */
  661. if (check_dev_quirk(bus, slot, func))
  662. break;
  663. }
  664. }
  665. void __init early_quirks(void)
  666. {
  667. if (!early_pci_allowed())
  668. return;
  669. early_pci_scan_bus(0);
  670. }