devicetree.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Architecture specific OF callbacks.
  4. */
  5. #include <linux/export.h>
  6. #include <linux/io.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/list.h>
  9. #include <linux/of.h>
  10. #include <linux/of_fdt.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/libfdt.h>
  15. #include <linux/slab.h>
  16. #include <linux/pci.h>
  17. #include <linux/of_pci.h>
  18. #include <linux/initrd.h>
  19. #include <asm/irqdomain.h>
  20. #include <asm/hpet.h>
  21. #include <asm/apic.h>
  22. #include <asm/io_apic.h>
  23. #include <asm/pci_x86.h>
  24. #include <asm/setup.h>
  25. #include <asm/i8259.h>
  26. #include <asm/prom.h>
  27. __initdata u64 initial_dtb;
  28. char __initdata cmd_line[COMMAND_LINE_SIZE];
  29. int __initdata of_ioapic;
  30. void __init early_init_dt_scan_chosen_arch(unsigned long node)
  31. {
  32. BUG();
  33. }
  34. void __init early_init_dt_add_memory_arch(u64 base, u64 size)
  35. {
  36. BUG();
  37. }
  38. void __init add_dtb(u64 data)
  39. {
  40. initial_dtb = data + offsetof(struct setup_data, data);
  41. }
  42. /*
  43. * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
  44. */
  45. static struct of_device_id __initdata ce4100_ids[] = {
  46. { .compatible = "intel,ce4100-cp", },
  47. { .compatible = "isa", },
  48. { .compatible = "pci", },
  49. {},
  50. };
  51. static int __init add_bus_probe(void)
  52. {
  53. if (!of_have_populated_dt())
  54. return 0;
  55. return of_platform_bus_probe(NULL, ce4100_ids, NULL);
  56. }
  57. device_initcall(add_bus_probe);
  58. #ifdef CONFIG_PCI
  59. struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
  60. {
  61. struct device_node *np;
  62. for_each_node_by_type(np, "pci") {
  63. const void *prop;
  64. unsigned int bus_min;
  65. prop = of_get_property(np, "bus-range", NULL);
  66. if (!prop)
  67. continue;
  68. bus_min = be32_to_cpup(prop);
  69. if (bus->number == bus_min)
  70. return np;
  71. }
  72. return NULL;
  73. }
  74. static int x86_of_pci_irq_enable(struct pci_dev *dev)
  75. {
  76. u32 virq;
  77. int ret;
  78. u8 pin;
  79. ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
  80. if (ret)
  81. return ret;
  82. if (!pin)
  83. return 0;
  84. virq = of_irq_parse_and_map_pci(dev, 0, 0);
  85. if (virq == 0)
  86. return -EINVAL;
  87. dev->irq = virq;
  88. return 0;
  89. }
  90. static void x86_of_pci_irq_disable(struct pci_dev *dev)
  91. {
  92. }
  93. void x86_of_pci_init(void)
  94. {
  95. pcibios_enable_irq = x86_of_pci_irq_enable;
  96. pcibios_disable_irq = x86_of_pci_irq_disable;
  97. }
  98. #endif
  99. static void __init dtb_setup_hpet(void)
  100. {
  101. #ifdef CONFIG_HPET_TIMER
  102. struct device_node *dn;
  103. struct resource r;
  104. int ret;
  105. dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
  106. if (!dn)
  107. return;
  108. ret = of_address_to_resource(dn, 0, &r);
  109. if (ret) {
  110. WARN_ON(1);
  111. return;
  112. }
  113. hpet_address = r.start;
  114. #endif
  115. }
  116. #ifdef CONFIG_X86_LOCAL_APIC
  117. static void __init dtb_cpu_setup(void)
  118. {
  119. struct device_node *dn;
  120. u32 apic_id, version;
  121. int ret;
  122. version = GET_APIC_VERSION(apic_read(APIC_LVR));
  123. for_each_of_cpu_node(dn) {
  124. ret = of_property_read_u32(dn, "reg", &apic_id);
  125. if (ret < 0) {
  126. pr_warn("%pOF: missing local APIC ID\n", dn);
  127. continue;
  128. }
  129. generic_processor_info(apic_id, version);
  130. }
  131. }
  132. static void __init dtb_lapic_setup(void)
  133. {
  134. struct device_node *dn;
  135. struct resource r;
  136. unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
  137. int ret;
  138. dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
  139. if (dn) {
  140. ret = of_address_to_resource(dn, 0, &r);
  141. if (WARN_ON(ret))
  142. return;
  143. lapic_addr = r.start;
  144. }
  145. /* Did the boot loader setup the local APIC ? */
  146. if (!boot_cpu_has(X86_FEATURE_APIC)) {
  147. if (apic_force_enable(lapic_addr))
  148. return;
  149. }
  150. smp_found_config = 1;
  151. pic_mode = 1;
  152. register_lapic_address(lapic_addr);
  153. }
  154. #endif /* CONFIG_X86_LOCAL_APIC */
  155. #ifdef CONFIG_X86_IO_APIC
  156. static unsigned int ioapic_id;
  157. struct of_ioapic_type {
  158. u32 out_type;
  159. u32 trigger;
  160. u32 polarity;
  161. };
  162. static struct of_ioapic_type of_ioapic_type[] =
  163. {
  164. {
  165. .out_type = IRQ_TYPE_EDGE_RISING,
  166. .trigger = IOAPIC_EDGE,
  167. .polarity = 1,
  168. },
  169. {
  170. .out_type = IRQ_TYPE_LEVEL_LOW,
  171. .trigger = IOAPIC_LEVEL,
  172. .polarity = 0,
  173. },
  174. {
  175. .out_type = IRQ_TYPE_LEVEL_HIGH,
  176. .trigger = IOAPIC_LEVEL,
  177. .polarity = 1,
  178. },
  179. {
  180. .out_type = IRQ_TYPE_EDGE_FALLING,
  181. .trigger = IOAPIC_EDGE,
  182. .polarity = 0,
  183. },
  184. };
  185. static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
  186. unsigned int nr_irqs, void *arg)
  187. {
  188. struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
  189. struct of_ioapic_type *it;
  190. struct irq_alloc_info tmp;
  191. int type_index;
  192. if (WARN_ON(fwspec->param_count < 2))
  193. return -EINVAL;
  194. type_index = fwspec->param[1];
  195. if (type_index >= ARRAY_SIZE(of_ioapic_type))
  196. return -EINVAL;
  197. it = &of_ioapic_type[type_index];
  198. ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
  199. tmp.devid = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
  200. tmp.ioapic.pin = fwspec->param[0];
  201. return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
  202. }
  203. static const struct irq_domain_ops ioapic_irq_domain_ops = {
  204. .alloc = dt_irqdomain_alloc,
  205. .free = mp_irqdomain_free,
  206. .activate = mp_irqdomain_activate,
  207. .deactivate = mp_irqdomain_deactivate,
  208. };
  209. static void __init dtb_add_ioapic(struct device_node *dn)
  210. {
  211. struct resource r;
  212. int ret;
  213. struct ioapic_domain_cfg cfg = {
  214. .type = IOAPIC_DOMAIN_DYNAMIC,
  215. .ops = &ioapic_irq_domain_ops,
  216. .dev = dn,
  217. };
  218. ret = of_address_to_resource(dn, 0, &r);
  219. if (ret) {
  220. printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn);
  221. return;
  222. }
  223. mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
  224. }
  225. static void __init dtb_ioapic_setup(void)
  226. {
  227. struct device_node *dn;
  228. for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
  229. dtb_add_ioapic(dn);
  230. if (nr_ioapics) {
  231. of_ioapic = 1;
  232. return;
  233. }
  234. printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
  235. }
  236. #else
  237. static void __init dtb_ioapic_setup(void) {}
  238. #endif
  239. static void __init dtb_apic_setup(void)
  240. {
  241. #ifdef CONFIG_X86_LOCAL_APIC
  242. dtb_lapic_setup();
  243. dtb_cpu_setup();
  244. #endif
  245. dtb_ioapic_setup();
  246. }
  247. #ifdef CONFIG_OF_EARLY_FLATTREE
  248. static void __init x86_flattree_get_config(void)
  249. {
  250. u32 size, map_len;
  251. void *dt;
  252. if (!initial_dtb)
  253. return;
  254. map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
  255. dt = early_memremap(initial_dtb, map_len);
  256. size = fdt_totalsize(dt);
  257. if (map_len < size) {
  258. early_memunmap(dt, map_len);
  259. dt = early_memremap(initial_dtb, size);
  260. map_len = size;
  261. }
  262. early_init_dt_verify(dt);
  263. unflatten_and_copy_device_tree();
  264. early_memunmap(dt, map_len);
  265. }
  266. #else
  267. static inline void x86_flattree_get_config(void) { }
  268. #endif
  269. void __init x86_dtb_init(void)
  270. {
  271. x86_flattree_get_config();
  272. if (!of_have_populated_dt())
  273. return;
  274. dtb_setup_hpet();
  275. dtb_apic_setup();
  276. }