aperture_64.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Firmware replacement code.
  4. *
  5. * Work around broken BIOSes that don't set an aperture, only set the
  6. * aperture in the AGP bridge, or set too small aperture.
  7. *
  8. * If all fails map the aperture over some low memory. This is cheaper than
  9. * doing bounce buffering. The memory is lost. This is done at early boot
  10. * because only the bootmem allocator can allocate 32+MB.
  11. *
  12. * Copyright 2002 Andi Kleen, SuSE Labs.
  13. */
  14. #define pr_fmt(fmt) "AGP: " fmt
  15. #include <linux/kernel.h>
  16. #include <linux/kcore.h>
  17. #include <linux/types.h>
  18. #include <linux/init.h>
  19. #include <linux/memblock.h>
  20. #include <linux/mmzone.h>
  21. #include <linux/pci_ids.h>
  22. #include <linux/pci.h>
  23. #include <linux/bitops.h>
  24. #include <linux/suspend.h>
  25. #include <asm/e820/api.h>
  26. #include <asm/io.h>
  27. #include <asm/iommu.h>
  28. #include <asm/gart.h>
  29. #include <asm/pci-direct.h>
  30. #include <asm/dma.h>
  31. #include <asm/amd_nb.h>
  32. #include <asm/x86_init.h>
  33. #include <linux/crash_dump.h>
  34. /*
  35. * Using 512M as goal, in case kexec will load kernel_big
  36. * that will do the on-position decompress, and could overlap with
  37. * with the gart aperture that is used.
  38. * Sequence:
  39. * kernel_small
  40. * ==> kexec (with kdump trigger path or gart still enabled)
  41. * ==> kernel_small (gart area become e820_reserved)
  42. * ==> kexec (with kdump trigger path or gart still enabled)
  43. * ==> kerne_big (uncompressed size will be big than 64M or 128M)
  44. * So don't use 512M below as gart iommu, leave the space for kernel
  45. * code for safe.
  46. */
  47. #define GART_MIN_ADDR (512ULL << 20)
  48. #define GART_MAX_ADDR (1ULL << 32)
  49. int gart_iommu_aperture;
  50. int gart_iommu_aperture_disabled __initdata;
  51. int gart_iommu_aperture_allowed __initdata;
  52. int fallback_aper_order __initdata = 1; /* 64MB */
  53. int fallback_aper_force __initdata;
  54. int fix_aperture __initdata = 1;
  55. #if defined(CONFIG_PROC_VMCORE) || defined(CONFIG_PROC_KCORE)
  56. /*
  57. * If the first kernel maps the aperture over e820 RAM, the kdump kernel will
  58. * use the same range because it will remain configured in the northbridge.
  59. * Trying to dump this area via /proc/vmcore may crash the machine, so exclude
  60. * it from vmcore.
  61. */
  62. static unsigned long aperture_pfn_start, aperture_page_count;
  63. static int gart_mem_pfn_is_ram(unsigned long pfn)
  64. {
  65. return likely((pfn < aperture_pfn_start) ||
  66. (pfn >= aperture_pfn_start + aperture_page_count));
  67. }
  68. static void __init exclude_from_core(u64 aper_base, u32 aper_order)
  69. {
  70. aperture_pfn_start = aper_base >> PAGE_SHIFT;
  71. aperture_page_count = (32 * 1024 * 1024) << aper_order >> PAGE_SHIFT;
  72. #ifdef CONFIG_PROC_VMCORE
  73. WARN_ON(register_oldmem_pfn_is_ram(&gart_mem_pfn_is_ram));
  74. #endif
  75. #ifdef CONFIG_PROC_KCORE
  76. WARN_ON(register_mem_pfn_is_ram(&gart_mem_pfn_is_ram));
  77. #endif
  78. }
  79. #else
  80. static void exclude_from_core(u64 aper_base, u32 aper_order)
  81. {
  82. }
  83. #endif
  84. /* This code runs before the PCI subsystem is initialized, so just
  85. access the northbridge directly. */
  86. static u32 __init allocate_aperture(void)
  87. {
  88. u32 aper_size;
  89. unsigned long addr;
  90. /* aper_size should <= 1G */
  91. if (fallback_aper_order > 5)
  92. fallback_aper_order = 5;
  93. aper_size = (32 * 1024 * 1024) << fallback_aper_order;
  94. /*
  95. * Aperture has to be naturally aligned. This means a 2GB aperture
  96. * won't have much chance of finding a place in the lower 4GB of
  97. * memory. Unfortunately we cannot move it up because that would
  98. * make the IOMMU useless.
  99. */
  100. addr = memblock_find_in_range(GART_MIN_ADDR, GART_MAX_ADDR,
  101. aper_size, aper_size);
  102. if (!addr) {
  103. pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n",
  104. addr, addr + aper_size - 1, aper_size >> 10);
  105. return 0;
  106. }
  107. memblock_reserve(addr, aper_size);
  108. pr_info("Mapping aperture over RAM [mem %#010lx-%#010lx] (%uKB)\n",
  109. addr, addr + aper_size - 1, aper_size >> 10);
  110. register_nosave_region(addr >> PAGE_SHIFT,
  111. (addr+aper_size) >> PAGE_SHIFT);
  112. return (u32)addr;
  113. }
  114. /* Find a PCI capability */
  115. static u32 __init find_cap(int bus, int slot, int func, int cap)
  116. {
  117. int bytes;
  118. u8 pos;
  119. if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
  120. PCI_STATUS_CAP_LIST))
  121. return 0;
  122. pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
  123. for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
  124. u8 id;
  125. pos &= ~3;
  126. id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
  127. if (id == 0xff)
  128. break;
  129. if (id == cap)
  130. return pos;
  131. pos = read_pci_config_byte(bus, slot, func,
  132. pos+PCI_CAP_LIST_NEXT);
  133. }
  134. return 0;
  135. }
  136. /* Read a standard AGPv3 bridge header */
  137. static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
  138. {
  139. u32 apsize;
  140. u32 apsizereg;
  141. int nbits;
  142. u32 aper_low, aper_hi;
  143. u64 aper;
  144. u32 old_order;
  145. pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func);
  146. apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
  147. if (apsizereg == 0xffffffff) {
  148. pr_err("pci 0000:%02x:%02x.%d: APSIZE unreadable\n",
  149. bus, slot, func);
  150. return 0;
  151. }
  152. /* old_order could be the value from NB gart setting */
  153. old_order = *order;
  154. apsize = apsizereg & 0xfff;
  155. /* Some BIOS use weird encodings not in the AGPv3 table. */
  156. if (apsize & 0xff)
  157. apsize |= 0xf00;
  158. nbits = hweight16(apsize);
  159. *order = 7 - nbits;
  160. if ((int)*order < 0) /* < 32MB */
  161. *order = 0;
  162. aper_low = read_pci_config(bus, slot, func, 0x10);
  163. aper_hi = read_pci_config(bus, slot, func, 0x14);
  164. aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
  165. /*
  166. * On some sick chips, APSIZE is 0. It means it wants 4G
  167. * so let double check that order, and lets trust AMD NB settings:
  168. */
  169. pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (old size %uMB)\n",
  170. bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1,
  171. 32 << old_order);
  172. if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
  173. pr_info("pci 0000:%02x:%02x.%d: AGP aperture size %uMB (APSIZE %#x) is not right, using settings from NB\n",
  174. bus, slot, func, 32 << *order, apsizereg);
  175. *order = old_order;
  176. }
  177. pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (%uMB, APSIZE %#x)\n",
  178. bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1,
  179. 32 << *order, apsizereg);
  180. if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
  181. return 0;
  182. return (u32)aper;
  183. }
  184. /*
  185. * Look for an AGP bridge. Windows only expects the aperture in the
  186. * AGP bridge and some BIOS forget to initialize the Northbridge too.
  187. * Work around this here.
  188. *
  189. * Do an PCI bus scan by hand because we're running before the PCI
  190. * subsystem.
  191. *
  192. * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
  193. * generically. It's probably overkill to always scan all slots because
  194. * the AGP bridges should be always an own bus on the HT hierarchy,
  195. * but do it here for future safety.
  196. */
  197. static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
  198. {
  199. int bus, slot, func;
  200. /* Poor man's PCI discovery */
  201. for (bus = 0; bus < 256; bus++) {
  202. for (slot = 0; slot < 32; slot++) {
  203. for (func = 0; func < 8; func++) {
  204. u32 class, cap;
  205. u8 type;
  206. class = read_pci_config(bus, slot, func,
  207. PCI_CLASS_REVISION);
  208. if (class == 0xffffffff)
  209. break;
  210. switch (class >> 16) {
  211. case PCI_CLASS_BRIDGE_HOST:
  212. case PCI_CLASS_BRIDGE_OTHER: /* needed? */
  213. /* AGP bridge? */
  214. cap = find_cap(bus, slot, func,
  215. PCI_CAP_ID_AGP);
  216. if (!cap)
  217. break;
  218. *valid_agp = 1;
  219. return read_agp(bus, slot, func, cap,
  220. order);
  221. }
  222. /* No multi-function device? */
  223. type = read_pci_config_byte(bus, slot, func,
  224. PCI_HEADER_TYPE);
  225. if (!(type & 0x80))
  226. break;
  227. }
  228. }
  229. }
  230. pr_info("No AGP bridge found\n");
  231. return 0;
  232. }
  233. static bool gart_fix_e820 __initdata = true;
  234. static int __init parse_gart_mem(char *p)
  235. {
  236. return kstrtobool(p, &gart_fix_e820);
  237. }
  238. early_param("gart_fix_e820", parse_gart_mem);
  239. /*
  240. * With kexec/kdump, if the first kernel doesn't shut down the GART and the
  241. * second kernel allocates a different GART region, there might be two
  242. * overlapping GART regions present:
  243. *
  244. * - the first still used by the GART initialized in the first kernel.
  245. * - (sub-)set of it used as normal RAM by the second kernel.
  246. *
  247. * which leads to memory corruptions and a kernel panic eventually.
  248. *
  249. * This can also happen if the BIOS has forgotten to mark the GART region
  250. * as reserved.
  251. *
  252. * Try to update the e820 map to mark that new region as reserved.
  253. */
  254. void __init early_gart_iommu_check(void)
  255. {
  256. u32 agp_aper_order = 0;
  257. int i, fix, slot, valid_agp = 0;
  258. u32 ctl;
  259. u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
  260. u64 aper_base = 0, last_aper_base = 0;
  261. int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
  262. if (!amd_gart_present())
  263. return;
  264. if (!early_pci_allowed())
  265. return;
  266. /* This is mostly duplicate of iommu_hole_init */
  267. search_agp_bridge(&agp_aper_order, &valid_agp);
  268. fix = 0;
  269. for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
  270. int bus;
  271. int dev_base, dev_limit;
  272. bus = amd_nb_bus_dev_ranges[i].bus;
  273. dev_base = amd_nb_bus_dev_ranges[i].dev_base;
  274. dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
  275. for (slot = dev_base; slot < dev_limit; slot++) {
  276. if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
  277. continue;
  278. ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
  279. aper_enabled = ctl & GARTEN;
  280. aper_order = (ctl >> 1) & 7;
  281. aper_size = (32 * 1024 * 1024) << aper_order;
  282. aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
  283. aper_base <<= 25;
  284. if (last_valid) {
  285. if ((aper_order != last_aper_order) ||
  286. (aper_base != last_aper_base) ||
  287. (aper_enabled != last_aper_enabled)) {
  288. fix = 1;
  289. break;
  290. }
  291. }
  292. last_aper_order = aper_order;
  293. last_aper_base = aper_base;
  294. last_aper_enabled = aper_enabled;
  295. last_valid = 1;
  296. }
  297. }
  298. if (!fix && !aper_enabled)
  299. return;
  300. if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
  301. fix = 1;
  302. if (gart_fix_e820 && !fix && aper_enabled) {
  303. if (e820__mapped_any(aper_base, aper_base + aper_size,
  304. E820_TYPE_RAM)) {
  305. /* reserve it, so we can reuse it in second kernel */
  306. pr_info("e820: reserve [mem %#010Lx-%#010Lx] for GART\n",
  307. aper_base, aper_base + aper_size - 1);
  308. e820__range_add(aper_base, aper_size, E820_TYPE_RESERVED);
  309. e820__update_table_print();
  310. }
  311. }
  312. if (valid_agp)
  313. return;
  314. /* disable them all at first */
  315. for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
  316. int bus;
  317. int dev_base, dev_limit;
  318. bus = amd_nb_bus_dev_ranges[i].bus;
  319. dev_base = amd_nb_bus_dev_ranges[i].dev_base;
  320. dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
  321. for (slot = dev_base; slot < dev_limit; slot++) {
  322. if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
  323. continue;
  324. ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
  325. ctl &= ~GARTEN;
  326. write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
  327. }
  328. }
  329. }
  330. static int __initdata printed_gart_size_msg;
  331. int __init gart_iommu_hole_init(void)
  332. {
  333. u32 agp_aper_base = 0, agp_aper_order = 0;
  334. u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
  335. u64 aper_base, last_aper_base = 0;
  336. int fix, slot, valid_agp = 0;
  337. int i, node;
  338. if (!amd_gart_present())
  339. return -ENODEV;
  340. if (gart_iommu_aperture_disabled || !fix_aperture ||
  341. !early_pci_allowed())
  342. return -ENODEV;
  343. pr_info("Checking aperture...\n");
  344. if (!fallback_aper_force)
  345. agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
  346. fix = 0;
  347. node = 0;
  348. for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
  349. int bus;
  350. int dev_base, dev_limit;
  351. u32 ctl;
  352. bus = amd_nb_bus_dev_ranges[i].bus;
  353. dev_base = amd_nb_bus_dev_ranges[i].dev_base;
  354. dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
  355. for (slot = dev_base; slot < dev_limit; slot++) {
  356. if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
  357. continue;
  358. iommu_detected = 1;
  359. gart_iommu_aperture = 1;
  360. x86_init.iommu.iommu_init = gart_iommu_init;
  361. ctl = read_pci_config(bus, slot, 3,
  362. AMD64_GARTAPERTURECTL);
  363. /*
  364. * Before we do anything else disable the GART. It may
  365. * still be enabled if we boot into a crash-kernel here.
  366. * Reconfiguring the GART while it is enabled could have
  367. * unknown side-effects.
  368. */
  369. ctl &= ~GARTEN;
  370. write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
  371. aper_order = (ctl >> 1) & 7;
  372. aper_size = (32 * 1024 * 1024) << aper_order;
  373. aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
  374. aper_base <<= 25;
  375. pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n",
  376. node, aper_base, aper_base + aper_size - 1,
  377. aper_size >> 20);
  378. node++;
  379. if (!aperture_valid(aper_base, aper_size, 64<<20)) {
  380. if (valid_agp && agp_aper_base &&
  381. agp_aper_base == aper_base &&
  382. agp_aper_order == aper_order) {
  383. /* the same between two setting from NB and agp */
  384. if (!no_iommu &&
  385. max_pfn > MAX_DMA32_PFN &&
  386. !printed_gart_size_msg) {
  387. pr_err("you are using iommu with agp, but GART size is less than 64MB\n");
  388. pr_err("please increase GART size in your BIOS setup\n");
  389. pr_err("if BIOS doesn't have that option, contact your HW vendor!\n");
  390. printed_gart_size_msg = 1;
  391. }
  392. } else {
  393. fix = 1;
  394. goto out;
  395. }
  396. }
  397. if ((last_aper_order && aper_order != last_aper_order) ||
  398. (last_aper_base && aper_base != last_aper_base)) {
  399. fix = 1;
  400. goto out;
  401. }
  402. last_aper_order = aper_order;
  403. last_aper_base = aper_base;
  404. }
  405. }
  406. out:
  407. if (!fix && !fallback_aper_force) {
  408. if (last_aper_base) {
  409. /*
  410. * If this is the kdump kernel, the first kernel
  411. * may have allocated the range over its e820 RAM
  412. * and fixed up the northbridge
  413. */
  414. exclude_from_core(last_aper_base, last_aper_order);
  415. return 1;
  416. }
  417. return 0;
  418. }
  419. if (!fallback_aper_force) {
  420. aper_alloc = agp_aper_base;
  421. aper_order = agp_aper_order;
  422. }
  423. if (aper_alloc) {
  424. /* Got the aperture from the AGP bridge */
  425. } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
  426. force_iommu ||
  427. valid_agp ||
  428. fallback_aper_force) {
  429. pr_info("Your BIOS doesn't leave an aperture memory hole\n");
  430. pr_info("Please enable the IOMMU option in the BIOS setup\n");
  431. pr_info("This costs you %dMB of RAM\n",
  432. 32 << fallback_aper_order);
  433. aper_order = fallback_aper_order;
  434. aper_alloc = allocate_aperture();
  435. if (!aper_alloc) {
  436. /*
  437. * Could disable AGP and IOMMU here, but it's
  438. * probably not worth it. But the later users
  439. * cannot deal with bad apertures and turning
  440. * on the aperture over memory causes very
  441. * strange problems, so it's better to panic
  442. * early.
  443. */
  444. panic("Not enough memory for aperture");
  445. }
  446. } else {
  447. return 0;
  448. }
  449. /*
  450. * If this is the kdump kernel _and_ the first kernel did not
  451. * configure the aperture in the northbridge, this range may
  452. * overlap with the first kernel's memory. We can't access the
  453. * range through vmcore even though it should be part of the dump.
  454. */
  455. exclude_from_core(aper_alloc, aper_order);
  456. /* Fix up the north bridges */
  457. for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
  458. int bus, dev_base, dev_limit;
  459. /*
  460. * Don't enable translation yet but enable GART IO and CPU
  461. * accesses and set DISTLBWALKPRB since GART table memory is UC.
  462. */
  463. u32 ctl = aper_order << 1;
  464. bus = amd_nb_bus_dev_ranges[i].bus;
  465. dev_base = amd_nb_bus_dev_ranges[i].dev_base;
  466. dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
  467. for (slot = dev_base; slot < dev_limit; slot++) {
  468. if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
  469. continue;
  470. write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
  471. write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
  472. }
  473. }
  474. set_up_gart_resume(aper_order, aper_alloc);
  475. return 1;
  476. }