apb_timer.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * apb_timer.c: Driver for Langwell APB timers
  4. *
  5. * (C) Copyright 2009 Intel Corporation
  6. * Author: Jacob Pan (jacob.jun.pan@intel.com)
  7. *
  8. * Note:
  9. * Langwell is the south complex of Intel Moorestown MID platform. There are
  10. * eight external timers in total that can be used by the operating system.
  11. * The timer information, such as frequency and addresses, is provided to the
  12. * OS via SFI tables.
  13. * Timer interrupts are routed via FW/HW emulated IOAPIC independently via
  14. * individual redirection table entries (RTE).
  15. * Unlike HPET, there is no master counter, therefore one of the timers are
  16. * used as clocksource. The overall allocation looks like:
  17. * - timer 0 - NR_CPUs for per cpu timer
  18. * - one timer for clocksource
  19. * - one timer for watchdog driver.
  20. * It is also worth notice that APB timer does not support true one-shot mode,
  21. * free-running mode will be used here to emulate one-shot mode.
  22. * APB timer can also be used as broadcast timer along with per cpu local APIC
  23. * timer, but by default APB timer has higher rating than local APIC timers.
  24. */
  25. #include <linux/delay.h>
  26. #include <linux/dw_apb_timer.h>
  27. #include <linux/errno.h>
  28. #include <linux/init.h>
  29. #include <linux/slab.h>
  30. #include <linux/pm.h>
  31. #include <linux/sfi.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/cpu.h>
  34. #include <linux/irq.h>
  35. #include <asm/fixmap.h>
  36. #include <asm/apb_timer.h>
  37. #include <asm/intel-mid.h>
  38. #include <asm/time.h>
  39. #define APBT_CLOCKEVENT_RATING 110
  40. #define APBT_CLOCKSOURCE_RATING 250
  41. #define APBT_CLOCKEVENT0_NUM (0)
  42. #define APBT_CLOCKSOURCE_NUM (2)
  43. static phys_addr_t apbt_address;
  44. static int apb_timer_block_enabled;
  45. static void __iomem *apbt_virt_address;
  46. /*
  47. * Common DW APB timer info
  48. */
  49. static unsigned long apbt_freq;
  50. struct apbt_dev {
  51. struct dw_apb_clock_event_device *timer;
  52. unsigned int num;
  53. int cpu;
  54. unsigned int irq;
  55. char name[10];
  56. };
  57. static struct dw_apb_clocksource *clocksource_apbt;
  58. static inline void __iomem *adev_virt_addr(struct apbt_dev *adev)
  59. {
  60. return apbt_virt_address + adev->num * APBTMRS_REG_SIZE;
  61. }
  62. static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
  63. #ifdef CONFIG_SMP
  64. static unsigned int apbt_num_timers_used;
  65. #endif
  66. static inline void apbt_set_mapping(void)
  67. {
  68. struct sfi_timer_table_entry *mtmr;
  69. int phy_cs_timer_id = 0;
  70. if (apbt_virt_address) {
  71. pr_debug("APBT base already mapped\n");
  72. return;
  73. }
  74. mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
  75. if (mtmr == NULL) {
  76. printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
  77. APBT_CLOCKEVENT0_NUM);
  78. return;
  79. }
  80. apbt_address = (phys_addr_t)mtmr->phys_addr;
  81. if (!apbt_address) {
  82. printk(KERN_WARNING "No timer base from SFI, use default\n");
  83. apbt_address = APBT_DEFAULT_BASE;
  84. }
  85. apbt_virt_address = ioremap(apbt_address, APBT_MMAP_SIZE);
  86. if (!apbt_virt_address) {
  87. pr_debug("Failed mapping APBT phy address at %lu\n",\
  88. (unsigned long)apbt_address);
  89. goto panic_noapbt;
  90. }
  91. apbt_freq = mtmr->freq_hz;
  92. sfi_free_mtmr(mtmr);
  93. /* Now figure out the physical timer id for clocksource device */
  94. mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
  95. if (mtmr == NULL)
  96. goto panic_noapbt;
  97. /* Now figure out the physical timer id */
  98. pr_debug("Use timer %d for clocksource\n",
  99. (int)(mtmr->phys_addr & 0xff) / APBTMRS_REG_SIZE);
  100. phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) /
  101. APBTMRS_REG_SIZE;
  102. clocksource_apbt = dw_apb_clocksource_init(APBT_CLOCKSOURCE_RATING,
  103. "apbt0", apbt_virt_address + phy_cs_timer_id *
  104. APBTMRS_REG_SIZE, apbt_freq);
  105. return;
  106. panic_noapbt:
  107. panic("Failed to setup APB system timer\n");
  108. }
  109. static inline void apbt_clear_mapping(void)
  110. {
  111. iounmap(apbt_virt_address);
  112. apbt_virt_address = NULL;
  113. }
  114. static int __init apbt_clockevent_register(void)
  115. {
  116. struct sfi_timer_table_entry *mtmr;
  117. struct apbt_dev *adev = this_cpu_ptr(&cpu_apbt_dev);
  118. mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
  119. if (mtmr == NULL) {
  120. printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
  121. APBT_CLOCKEVENT0_NUM);
  122. return -ENODEV;
  123. }
  124. adev->num = smp_processor_id();
  125. adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",
  126. intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ?
  127. APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,
  128. adev_virt_addr(adev), 0, apbt_freq);
  129. /* Firmware does EOI handling for us. */
  130. adev->timer->eoi = NULL;
  131. if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
  132. global_clock_event = &adev->timer->ced;
  133. printk(KERN_DEBUG "%s clockevent registered as global\n",
  134. global_clock_event->name);
  135. }
  136. dw_apb_clockevent_register(adev->timer);
  137. sfi_free_mtmr(mtmr);
  138. return 0;
  139. }
  140. #ifdef CONFIG_SMP
  141. static void apbt_setup_irq(struct apbt_dev *adev)
  142. {
  143. irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
  144. irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
  145. }
  146. /* Should be called with per cpu */
  147. void apbt_setup_secondary_clock(void)
  148. {
  149. struct apbt_dev *adev;
  150. int cpu;
  151. /* Don't register boot CPU clockevent */
  152. cpu = smp_processor_id();
  153. if (!cpu)
  154. return;
  155. adev = this_cpu_ptr(&cpu_apbt_dev);
  156. if (!adev->timer) {
  157. adev->timer = dw_apb_clockevent_init(cpu, adev->name,
  158. APBT_CLOCKEVENT_RATING, adev_virt_addr(adev),
  159. adev->irq, apbt_freq);
  160. adev->timer->eoi = NULL;
  161. } else {
  162. dw_apb_clockevent_resume(adev->timer);
  163. }
  164. printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n",
  165. cpu, adev->name, adev->cpu);
  166. apbt_setup_irq(adev);
  167. dw_apb_clockevent_register(adev->timer);
  168. return;
  169. }
  170. /*
  171. * this notify handler process CPU hotplug events. in case of S0i3, nonboot
  172. * cpus are disabled/enabled frequently, for performance reasons, we keep the
  173. * per cpu timer irq registered so that we do need to do free_irq/request_irq.
  174. *
  175. * TODO: it might be more reliable to directly disable percpu clockevent device
  176. * without the notifier chain. currently, cpu 0 may get interrupts from other
  177. * cpu timers during the offline process due to the ordering of notification.
  178. * the extra interrupt is harmless.
  179. */
  180. static int apbt_cpu_dead(unsigned int cpu)
  181. {
  182. struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
  183. dw_apb_clockevent_pause(adev->timer);
  184. if (system_state == SYSTEM_RUNNING) {
  185. pr_debug("skipping APBT CPU %u offline\n", cpu);
  186. } else {
  187. pr_debug("APBT clockevent for cpu %u offline\n", cpu);
  188. dw_apb_clockevent_stop(adev->timer);
  189. }
  190. return 0;
  191. }
  192. static __init int apbt_late_init(void)
  193. {
  194. if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ||
  195. !apb_timer_block_enabled)
  196. return 0;
  197. return cpuhp_setup_state(CPUHP_X86_APB_DEAD, "x86/apb:dead", NULL,
  198. apbt_cpu_dead);
  199. }
  200. fs_initcall(apbt_late_init);
  201. #else
  202. void apbt_setup_secondary_clock(void) {}
  203. #endif /* CONFIG_SMP */
  204. static int apbt_clocksource_register(void)
  205. {
  206. u64 start, now;
  207. u64 t1;
  208. /* Start the counter, use timer 2 as source, timer 0/1 for event */
  209. dw_apb_clocksource_start(clocksource_apbt);
  210. /* Verify whether apbt counter works */
  211. t1 = dw_apb_clocksource_read(clocksource_apbt);
  212. start = rdtsc();
  213. /*
  214. * We don't know the TSC frequency yet, but waiting for
  215. * 200000 TSC cycles is safe:
  216. * 4 GHz == 50us
  217. * 1 GHz == 200us
  218. */
  219. do {
  220. rep_nop();
  221. now = rdtsc();
  222. } while ((now - start) < 200000UL);
  223. /* APBT is the only always on clocksource, it has to work! */
  224. if (t1 == dw_apb_clocksource_read(clocksource_apbt))
  225. panic("APBT counter not counting. APBT disabled\n");
  226. dw_apb_clocksource_register(clocksource_apbt);
  227. return 0;
  228. }
  229. /*
  230. * Early setup the APBT timer, only use timer 0 for booting then switch to
  231. * per CPU timer if possible.
  232. * returns 1 if per cpu apbt is setup
  233. * returns 0 if no per cpu apbt is chosen
  234. * panic if set up failed, this is the only platform timer on Moorestown.
  235. */
  236. void __init apbt_time_init(void)
  237. {
  238. #ifdef CONFIG_SMP
  239. int i;
  240. struct sfi_timer_table_entry *p_mtmr;
  241. struct apbt_dev *adev;
  242. #endif
  243. if (apb_timer_block_enabled)
  244. return;
  245. apbt_set_mapping();
  246. if (!apbt_virt_address)
  247. goto out_noapbt;
  248. /*
  249. * Read the frequency and check for a sane value, for ESL model
  250. * we extend the possible clock range to allow time scaling.
  251. */
  252. if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
  253. pr_debug("APBT has invalid freq 0x%lx\n", apbt_freq);
  254. goto out_noapbt;
  255. }
  256. if (apbt_clocksource_register()) {
  257. pr_debug("APBT has failed to register clocksource\n");
  258. goto out_noapbt;
  259. }
  260. if (!apbt_clockevent_register())
  261. apb_timer_block_enabled = 1;
  262. else {
  263. pr_debug("APBT has failed to register clockevent\n");
  264. goto out_noapbt;
  265. }
  266. #ifdef CONFIG_SMP
  267. /* kernel cmdline disable apb timer, so we will use lapic timers */
  268. if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
  269. printk(KERN_INFO "apbt: disabled per cpu timer\n");
  270. return;
  271. }
  272. pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
  273. if (num_possible_cpus() <= sfi_mtimer_num)
  274. apbt_num_timers_used = num_possible_cpus();
  275. else
  276. apbt_num_timers_used = 1;
  277. pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
  278. /* here we set up per CPU timer data structure */
  279. for (i = 0; i < apbt_num_timers_used; i++) {
  280. adev = &per_cpu(cpu_apbt_dev, i);
  281. adev->num = i;
  282. adev->cpu = i;
  283. p_mtmr = sfi_get_mtmr(i);
  284. if (p_mtmr)
  285. adev->irq = p_mtmr->irq;
  286. else
  287. printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
  288. snprintf(adev->name, sizeof(adev->name) - 1, "apbt%d", i);
  289. }
  290. #endif
  291. return;
  292. out_noapbt:
  293. apbt_clear_mapping();
  294. apb_timer_block_enabled = 0;
  295. panic("failed to enable APB timer\n");
  296. }