swift.S 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * swift.S: MicroSparc-II mmu/cache operations.
  4. *
  5. * Copyright (C) 1999 David S. Miller (davem@redhat.com)
  6. */
  7. #include <asm/psr.h>
  8. #include <asm/asi.h>
  9. #include <asm/page.h>
  10. #include <asm/pgtsrmmu.h>
  11. #include <asm/asm-offsets.h>
  12. .text
  13. .align 4
  14. #if 1 /* XXX screw this, I can't get the VAC flushes working
  15. * XXX reliably... -DaveM
  16. */
  17. .globl swift_flush_cache_all, swift_flush_cache_mm
  18. .globl swift_flush_cache_range, swift_flush_cache_page
  19. .globl swift_flush_page_for_dma
  20. .globl swift_flush_page_to_ram
  21. swift_flush_cache_all:
  22. swift_flush_cache_mm:
  23. swift_flush_cache_range:
  24. swift_flush_cache_page:
  25. swift_flush_page_for_dma:
  26. swift_flush_page_to_ram:
  27. sethi %hi(0x2000), %o0
  28. 1: subcc %o0, 0x10, %o0
  29. add %o0, %o0, %o1
  30. sta %g0, [%o0] ASI_M_DATAC_TAG
  31. bne 1b
  32. sta %g0, [%o1] ASI_M_TXTC_TAG
  33. retl
  34. nop
  35. #else
  36. .globl swift_flush_cache_all
  37. swift_flush_cache_all:
  38. WINDOW_FLUSH(%g4, %g5)
  39. /* Just clear out all the tags. */
  40. sethi %hi(16 * 1024), %o0
  41. 1: subcc %o0, 16, %o0
  42. sta %g0, [%o0] ASI_M_TXTC_TAG
  43. bne 1b
  44. sta %g0, [%o0] ASI_M_DATAC_TAG
  45. retl
  46. nop
  47. .globl swift_flush_cache_mm
  48. swift_flush_cache_mm:
  49. ld [%o0 + AOFF_mm_context], %g2
  50. cmp %g2, -1
  51. be swift_flush_cache_mm_out
  52. WINDOW_FLUSH(%g4, %g5)
  53. rd %psr, %g1
  54. andn %g1, PSR_ET, %g3
  55. wr %g3, 0x0, %psr
  56. nop
  57. nop
  58. mov SRMMU_CTX_REG, %g7
  59. lda [%g7] ASI_M_MMUREGS, %g5
  60. sta %g2, [%g7] ASI_M_MMUREGS
  61. #if 1
  62. sethi %hi(0x2000), %o0
  63. 1: subcc %o0, 0x10, %o0
  64. sta %g0, [%o0] ASI_M_FLUSH_CTX
  65. bne 1b
  66. nop
  67. #else
  68. clr %o0
  69. or %g0, 2048, %g7
  70. or %g0, 2048, %o1
  71. add %o1, 2048, %o2
  72. add %o2, 2048, %o3
  73. mov 16, %o4
  74. add %o4, 2048, %o5
  75. add %o5, 2048, %g2
  76. add %g2, 2048, %g3
  77. 1: sta %g0, [%o0 ] ASI_M_FLUSH_CTX
  78. sta %g0, [%o0 + %o1] ASI_M_FLUSH_CTX
  79. sta %g0, [%o0 + %o2] ASI_M_FLUSH_CTX
  80. sta %g0, [%o0 + %o3] ASI_M_FLUSH_CTX
  81. sta %g0, [%o0 + %o4] ASI_M_FLUSH_CTX
  82. sta %g0, [%o0 + %o5] ASI_M_FLUSH_CTX
  83. sta %g0, [%o0 + %g2] ASI_M_FLUSH_CTX
  84. sta %g0, [%o0 + %g3] ASI_M_FLUSH_CTX
  85. subcc %g7, 32, %g7
  86. bne 1b
  87. add %o0, 32, %o0
  88. #endif
  89. mov SRMMU_CTX_REG, %g7
  90. sta %g5, [%g7] ASI_M_MMUREGS
  91. wr %g1, 0x0, %psr
  92. nop
  93. nop
  94. swift_flush_cache_mm_out:
  95. retl
  96. nop
  97. .globl swift_flush_cache_range
  98. swift_flush_cache_range:
  99. ld [%o0 + VMA_VM_MM], %o0
  100. sub %o2, %o1, %o2
  101. sethi %hi(4096), %o3
  102. cmp %o2, %o3
  103. bgu swift_flush_cache_mm
  104. nop
  105. b 70f
  106. nop
  107. .globl swift_flush_cache_page
  108. swift_flush_cache_page:
  109. ld [%o0 + VMA_VM_MM], %o0
  110. 70:
  111. ld [%o0 + AOFF_mm_context], %g2
  112. cmp %g2, -1
  113. be swift_flush_cache_page_out
  114. WINDOW_FLUSH(%g4, %g5)
  115. rd %psr, %g1
  116. andn %g1, PSR_ET, %g3
  117. wr %g3, 0x0, %psr
  118. nop
  119. nop
  120. mov SRMMU_CTX_REG, %g7
  121. lda [%g7] ASI_M_MMUREGS, %g5
  122. sta %g2, [%g7] ASI_M_MMUREGS
  123. andn %o1, (PAGE_SIZE - 1), %o1
  124. #if 1
  125. sethi %hi(0x1000), %o0
  126. 1: subcc %o0, 0x10, %o0
  127. sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
  128. bne 1b
  129. nop
  130. #else
  131. or %g0, 512, %g7
  132. or %g0, 512, %o0
  133. add %o0, 512, %o2
  134. add %o2, 512, %o3
  135. add %o3, 512, %o4
  136. add %o4, 512, %o5
  137. add %o5, 512, %g3
  138. add %g3, 512, %g4
  139. 1: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
  140. sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
  141. sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
  142. sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
  143. sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
  144. sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
  145. sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
  146. sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
  147. subcc %g7, 16, %g7
  148. bne 1b
  149. add %o1, 16, %o1
  150. #endif
  151. mov SRMMU_CTX_REG, %g7
  152. sta %g5, [%g7] ASI_M_MMUREGS
  153. wr %g1, 0x0, %psr
  154. nop
  155. nop
  156. swift_flush_cache_page_out:
  157. retl
  158. nop
  159. /* Swift is write-thru, however it is not
  160. * I/O nor TLB-walk coherent. Also it has
  161. * caches which are virtually indexed and tagged.
  162. */
  163. .globl swift_flush_page_for_dma
  164. .globl swift_flush_page_to_ram
  165. swift_flush_page_for_dma:
  166. swift_flush_page_to_ram:
  167. andn %o0, (PAGE_SIZE - 1), %o1
  168. #if 1
  169. sethi %hi(0x1000), %o0
  170. 1: subcc %o0, 0x10, %o0
  171. sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
  172. bne 1b
  173. nop
  174. #else
  175. or %g0, 512, %g7
  176. or %g0, 512, %o0
  177. add %o0, 512, %o2
  178. add %o2, 512, %o3
  179. add %o3, 512, %o4
  180. add %o4, 512, %o5
  181. add %o5, 512, %g3
  182. add %g3, 512, %g4
  183. 1: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
  184. sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
  185. sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
  186. sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
  187. sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
  188. sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
  189. sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
  190. sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
  191. subcc %g7, 16, %g7
  192. bne 1b
  193. add %o1, 16, %o1
  194. #endif
  195. retl
  196. nop
  197. #endif
  198. .globl swift_flush_sig_insns
  199. swift_flush_sig_insns:
  200. flush %o1
  201. retl
  202. flush %o1 + 4
  203. .globl swift_flush_tlb_mm
  204. .globl swift_flush_tlb_range
  205. .globl swift_flush_tlb_all
  206. swift_flush_tlb_range:
  207. ld [%o0 + VMA_VM_MM], %o0
  208. swift_flush_tlb_mm:
  209. ld [%o0 + AOFF_mm_context], %g2
  210. cmp %g2, -1
  211. be swift_flush_tlb_all_out
  212. swift_flush_tlb_all:
  213. mov 0x400, %o1
  214. sta %g0, [%o1] ASI_M_FLUSH_PROBE
  215. swift_flush_tlb_all_out:
  216. retl
  217. nop
  218. .globl swift_flush_tlb_page
  219. swift_flush_tlb_page:
  220. ld [%o0 + VMA_VM_MM], %o0
  221. mov SRMMU_CTX_REG, %g1
  222. ld [%o0 + AOFF_mm_context], %o3
  223. andn %o1, (PAGE_SIZE - 1), %o1
  224. cmp %o3, -1
  225. be swift_flush_tlb_page_out
  226. nop
  227. #if 1
  228. mov 0x400, %o1
  229. sta %g0, [%o1] ASI_M_FLUSH_PROBE
  230. #else
  231. lda [%g1] ASI_M_MMUREGS, %g5
  232. sta %o3, [%g1] ASI_M_MMUREGS
  233. sta %g0, [%o1] ASI_M_FLUSH_PAGE /* rem. virt. cache. prot. */
  234. sta %g0, [%o1] ASI_M_FLUSH_PROBE
  235. sta %g5, [%g1] ASI_M_MMUREGS
  236. #endif
  237. swift_flush_tlb_page_out:
  238. retl
  239. nop