init_64.c 77 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * arch/sparc64/mm/init.c
  4. *
  5. * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
  6. * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  7. */
  8. #include <linux/extable.h>
  9. #include <linux/kernel.h>
  10. #include <linux/sched.h>
  11. #include <linux/string.h>
  12. #include <linux/init.h>
  13. #include <linux/memblock.h>
  14. #include <linux/mm.h>
  15. #include <linux/hugetlb.h>
  16. #include <linux/initrd.h>
  17. #include <linux/swap.h>
  18. #include <linux/pagemap.h>
  19. #include <linux/poison.h>
  20. #include <linux/fs.h>
  21. #include <linux/seq_file.h>
  22. #include <linux/kprobes.h>
  23. #include <linux/cache.h>
  24. #include <linux/sort.h>
  25. #include <linux/ioport.h>
  26. #include <linux/percpu.h>
  27. #include <linux/mmzone.h>
  28. #include <linux/gfp.h>
  29. #include <asm/head.h>
  30. #include <asm/page.h>
  31. #include <asm/pgalloc.h>
  32. #include <asm/oplib.h>
  33. #include <asm/iommu.h>
  34. #include <asm/io.h>
  35. #include <linux/uaccess.h>
  36. #include <asm/mmu_context.h>
  37. #include <asm/tlbflush.h>
  38. #include <asm/dma.h>
  39. #include <asm/starfire.h>
  40. #include <asm/tlb.h>
  41. #include <asm/spitfire.h>
  42. #include <asm/sections.h>
  43. #include <asm/tsb.h>
  44. #include <asm/hypervisor.h>
  45. #include <asm/prom.h>
  46. #include <asm/mdesc.h>
  47. #include <asm/cpudata.h>
  48. #include <asm/setup.h>
  49. #include <asm/irq.h>
  50. #include "init_64.h"
  51. unsigned long kern_linear_pte_xor[4] __read_mostly;
  52. static unsigned long page_cache4v_flag;
  53. /* A bitmap, two bits for every 256MB of physical memory. These two
  54. * bits determine what page size we use for kernel linear
  55. * translations. They form an index into kern_linear_pte_xor[]. The
  56. * value in the indexed slot is XOR'd with the TLB miss virtual
  57. * address to form the resulting TTE. The mapping is:
  58. *
  59. * 0 ==> 4MB
  60. * 1 ==> 256MB
  61. * 2 ==> 2GB
  62. * 3 ==> 16GB
  63. *
  64. * All sun4v chips support 256MB pages. Only SPARC-T4 and later
  65. * support 2GB pages, and hopefully future cpus will support the 16GB
  66. * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
  67. * if these larger page sizes are not supported by the cpu.
  68. *
  69. * It would be nice to determine this from the machine description
  70. * 'cpu' properties, but we need to have this table setup before the
  71. * MDESC is initialized.
  72. */
  73. #ifndef CONFIG_DEBUG_PAGEALLOC
  74. /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
  75. * Space is allocated for this right after the trap table in
  76. * arch/sparc64/kernel/head.S
  77. */
  78. extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  79. #endif
  80. extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
  81. static unsigned long cpu_pgsz_mask;
  82. #define MAX_BANKS 1024
  83. static struct linux_prom64_registers pavail[MAX_BANKS];
  84. static int pavail_ents;
  85. u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
  86. static int cmp_p64(const void *a, const void *b)
  87. {
  88. const struct linux_prom64_registers *x = a, *y = b;
  89. if (x->phys_addr > y->phys_addr)
  90. return 1;
  91. if (x->phys_addr < y->phys_addr)
  92. return -1;
  93. return 0;
  94. }
  95. static void __init read_obp_memory(const char *property,
  96. struct linux_prom64_registers *regs,
  97. int *num_ents)
  98. {
  99. phandle node = prom_finddevice("/memory");
  100. int prop_size = prom_getproplen(node, property);
  101. int ents, ret, i;
  102. ents = prop_size / sizeof(struct linux_prom64_registers);
  103. if (ents > MAX_BANKS) {
  104. prom_printf("The machine has more %s property entries than "
  105. "this kernel can support (%d).\n",
  106. property, MAX_BANKS);
  107. prom_halt();
  108. }
  109. ret = prom_getproperty(node, property, (char *) regs, prop_size);
  110. if (ret == -1) {
  111. prom_printf("Couldn't get %s property from /memory.\n",
  112. property);
  113. prom_halt();
  114. }
  115. /* Sanitize what we got from the firmware, by page aligning
  116. * everything.
  117. */
  118. for (i = 0; i < ents; i++) {
  119. unsigned long base, size;
  120. base = regs[i].phys_addr;
  121. size = regs[i].reg_size;
  122. size &= PAGE_MASK;
  123. if (base & ~PAGE_MASK) {
  124. unsigned long new_base = PAGE_ALIGN(base);
  125. size -= new_base - base;
  126. if ((long) size < 0L)
  127. size = 0UL;
  128. base = new_base;
  129. }
  130. if (size == 0UL) {
  131. /* If it is empty, simply get rid of it.
  132. * This simplifies the logic of the other
  133. * functions that process these arrays.
  134. */
  135. memmove(&regs[i], &regs[i + 1],
  136. (ents - i - 1) * sizeof(regs[0]));
  137. i--;
  138. ents--;
  139. continue;
  140. }
  141. regs[i].phys_addr = base;
  142. regs[i].reg_size = size;
  143. }
  144. *num_ents = ents;
  145. sort(regs, ents, sizeof(struct linux_prom64_registers),
  146. cmp_p64, NULL);
  147. }
  148. /* Kernel physical address base and size in bytes. */
  149. unsigned long kern_base __read_mostly;
  150. unsigned long kern_size __read_mostly;
  151. /* Initial ramdisk setup */
  152. extern unsigned long sparc_ramdisk_image64;
  153. extern unsigned int sparc_ramdisk_image;
  154. extern unsigned int sparc_ramdisk_size;
  155. struct page *mem_map_zero __read_mostly;
  156. EXPORT_SYMBOL(mem_map_zero);
  157. unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
  158. unsigned long sparc64_kern_pri_context __read_mostly;
  159. unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
  160. unsigned long sparc64_kern_sec_context __read_mostly;
  161. int num_kernel_image_mappings;
  162. #ifdef CONFIG_DEBUG_DCFLUSH
  163. atomic_t dcpage_flushes = ATOMIC_INIT(0);
  164. #ifdef CONFIG_SMP
  165. atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
  166. #endif
  167. #endif
  168. inline void flush_dcache_page_impl(struct page *page)
  169. {
  170. BUG_ON(tlb_type == hypervisor);
  171. #ifdef CONFIG_DEBUG_DCFLUSH
  172. atomic_inc(&dcpage_flushes);
  173. #endif
  174. #ifdef DCACHE_ALIASING_POSSIBLE
  175. __flush_dcache_page(page_address(page),
  176. ((tlb_type == spitfire) &&
  177. page_mapping_file(page) != NULL));
  178. #else
  179. if (page_mapping_file(page) != NULL &&
  180. tlb_type == spitfire)
  181. __flush_icache_page(__pa(page_address(page)));
  182. #endif
  183. }
  184. #define PG_dcache_dirty PG_arch_1
  185. #define PG_dcache_cpu_shift 32UL
  186. #define PG_dcache_cpu_mask \
  187. ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
  188. #define dcache_dirty_cpu(page) \
  189. (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
  190. static inline void set_dcache_dirty(struct page *page, int this_cpu)
  191. {
  192. unsigned long mask = this_cpu;
  193. unsigned long non_cpu_bits;
  194. non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
  195. mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
  196. __asm__ __volatile__("1:\n\t"
  197. "ldx [%2], %%g7\n\t"
  198. "and %%g7, %1, %%g1\n\t"
  199. "or %%g1, %0, %%g1\n\t"
  200. "casx [%2], %%g7, %%g1\n\t"
  201. "cmp %%g7, %%g1\n\t"
  202. "bne,pn %%xcc, 1b\n\t"
  203. " nop"
  204. : /* no outputs */
  205. : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
  206. : "g1", "g7");
  207. }
  208. static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
  209. {
  210. unsigned long mask = (1UL << PG_dcache_dirty);
  211. __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
  212. "1:\n\t"
  213. "ldx [%2], %%g7\n\t"
  214. "srlx %%g7, %4, %%g1\n\t"
  215. "and %%g1, %3, %%g1\n\t"
  216. "cmp %%g1, %0\n\t"
  217. "bne,pn %%icc, 2f\n\t"
  218. " andn %%g7, %1, %%g1\n\t"
  219. "casx [%2], %%g7, %%g1\n\t"
  220. "cmp %%g7, %%g1\n\t"
  221. "bne,pn %%xcc, 1b\n\t"
  222. " nop\n"
  223. "2:"
  224. : /* no outputs */
  225. : "r" (cpu), "r" (mask), "r" (&page->flags),
  226. "i" (PG_dcache_cpu_mask),
  227. "i" (PG_dcache_cpu_shift)
  228. : "g1", "g7");
  229. }
  230. static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
  231. {
  232. unsigned long tsb_addr = (unsigned long) ent;
  233. if (tlb_type == cheetah_plus || tlb_type == hypervisor)
  234. tsb_addr = __pa(tsb_addr);
  235. __tsb_insert(tsb_addr, tag, pte);
  236. }
  237. unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
  238. static void flush_dcache(unsigned long pfn)
  239. {
  240. struct page *page;
  241. page = pfn_to_page(pfn);
  242. if (page) {
  243. unsigned long pg_flags;
  244. pg_flags = page->flags;
  245. if (pg_flags & (1UL << PG_dcache_dirty)) {
  246. int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
  247. PG_dcache_cpu_mask);
  248. int this_cpu = get_cpu();
  249. /* This is just to optimize away some function calls
  250. * in the SMP case.
  251. */
  252. if (cpu == this_cpu)
  253. flush_dcache_page_impl(page);
  254. else
  255. smp_flush_dcache_page_impl(page, cpu);
  256. clear_dcache_dirty_cpu(page, cpu);
  257. put_cpu();
  258. }
  259. }
  260. }
  261. /* mm->context.lock must be held */
  262. static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
  263. unsigned long tsb_hash_shift, unsigned long address,
  264. unsigned long tte)
  265. {
  266. struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
  267. unsigned long tag;
  268. if (unlikely(!tsb))
  269. return;
  270. tsb += ((address >> tsb_hash_shift) &
  271. (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
  272. tag = (address >> 22UL);
  273. tsb_insert(tsb, tag, tte);
  274. }
  275. #ifdef CONFIG_HUGETLB_PAGE
  276. static int __init hugetlbpage_init(void)
  277. {
  278. hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT);
  279. hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT);
  280. hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT);
  281. hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT);
  282. return 0;
  283. }
  284. arch_initcall(hugetlbpage_init);
  285. static void __init pud_huge_patch(void)
  286. {
  287. struct pud_huge_patch_entry *p;
  288. unsigned long addr;
  289. p = &__pud_huge_patch;
  290. addr = p->addr;
  291. *(unsigned int *)addr = p->insn;
  292. __asm__ __volatile__("flush %0" : : "r" (addr));
  293. }
  294. bool __init arch_hugetlb_valid_size(unsigned long size)
  295. {
  296. unsigned int hugepage_shift = ilog2(size);
  297. unsigned short hv_pgsz_idx;
  298. unsigned int hv_pgsz_mask;
  299. switch (hugepage_shift) {
  300. case HPAGE_16GB_SHIFT:
  301. hv_pgsz_mask = HV_PGSZ_MASK_16GB;
  302. hv_pgsz_idx = HV_PGSZ_IDX_16GB;
  303. pud_huge_patch();
  304. break;
  305. case HPAGE_2GB_SHIFT:
  306. hv_pgsz_mask = HV_PGSZ_MASK_2GB;
  307. hv_pgsz_idx = HV_PGSZ_IDX_2GB;
  308. break;
  309. case HPAGE_256MB_SHIFT:
  310. hv_pgsz_mask = HV_PGSZ_MASK_256MB;
  311. hv_pgsz_idx = HV_PGSZ_IDX_256MB;
  312. break;
  313. case HPAGE_SHIFT:
  314. hv_pgsz_mask = HV_PGSZ_MASK_4MB;
  315. hv_pgsz_idx = HV_PGSZ_IDX_4MB;
  316. break;
  317. case HPAGE_64K_SHIFT:
  318. hv_pgsz_mask = HV_PGSZ_MASK_64K;
  319. hv_pgsz_idx = HV_PGSZ_IDX_64K;
  320. break;
  321. default:
  322. hv_pgsz_mask = 0;
  323. }
  324. if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
  325. return false;
  326. return true;
  327. }
  328. #endif /* CONFIG_HUGETLB_PAGE */
  329. void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
  330. {
  331. struct mm_struct *mm;
  332. unsigned long flags;
  333. bool is_huge_tsb;
  334. pte_t pte = *ptep;
  335. if (tlb_type != hypervisor) {
  336. unsigned long pfn = pte_pfn(pte);
  337. if (pfn_valid(pfn))
  338. flush_dcache(pfn);
  339. }
  340. mm = vma->vm_mm;
  341. /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
  342. if (!pte_accessible(mm, pte))
  343. return;
  344. spin_lock_irqsave(&mm->context.lock, flags);
  345. is_huge_tsb = false;
  346. #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
  347. if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
  348. unsigned long hugepage_size = PAGE_SIZE;
  349. if (is_vm_hugetlb_page(vma))
  350. hugepage_size = huge_page_size(hstate_vma(vma));
  351. if (hugepage_size >= PUD_SIZE) {
  352. unsigned long mask = 0x1ffc00000UL;
  353. /* Transfer bits [32:22] from address to resolve
  354. * at 4M granularity.
  355. */
  356. pte_val(pte) &= ~mask;
  357. pte_val(pte) |= (address & mask);
  358. } else if (hugepage_size >= PMD_SIZE) {
  359. /* We are fabricating 8MB pages using 4MB
  360. * real hw pages.
  361. */
  362. pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
  363. }
  364. if (hugepage_size >= PMD_SIZE) {
  365. __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
  366. REAL_HPAGE_SHIFT, address, pte_val(pte));
  367. is_huge_tsb = true;
  368. }
  369. }
  370. #endif
  371. if (!is_huge_tsb)
  372. __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
  373. address, pte_val(pte));
  374. spin_unlock_irqrestore(&mm->context.lock, flags);
  375. }
  376. void flush_dcache_page(struct page *page)
  377. {
  378. struct address_space *mapping;
  379. int this_cpu;
  380. if (tlb_type == hypervisor)
  381. return;
  382. /* Do not bother with the expensive D-cache flush if it
  383. * is merely the zero page. The 'bigcore' testcase in GDB
  384. * causes this case to run millions of times.
  385. */
  386. if (page == ZERO_PAGE(0))
  387. return;
  388. this_cpu = get_cpu();
  389. mapping = page_mapping_file(page);
  390. if (mapping && !mapping_mapped(mapping)) {
  391. int dirty = test_bit(PG_dcache_dirty, &page->flags);
  392. if (dirty) {
  393. int dirty_cpu = dcache_dirty_cpu(page);
  394. if (dirty_cpu == this_cpu)
  395. goto out;
  396. smp_flush_dcache_page_impl(page, dirty_cpu);
  397. }
  398. set_dcache_dirty(page, this_cpu);
  399. } else {
  400. /* We could delay the flush for the !page_mapping
  401. * case too. But that case is for exec env/arg
  402. * pages and those are %99 certainly going to get
  403. * faulted into the tlb (and thus flushed) anyways.
  404. */
  405. flush_dcache_page_impl(page);
  406. }
  407. out:
  408. put_cpu();
  409. }
  410. EXPORT_SYMBOL(flush_dcache_page);
  411. void __kprobes flush_icache_range(unsigned long start, unsigned long end)
  412. {
  413. /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
  414. if (tlb_type == spitfire) {
  415. unsigned long kaddr;
  416. /* This code only runs on Spitfire cpus so this is
  417. * why we can assume _PAGE_PADDR_4U.
  418. */
  419. for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
  420. unsigned long paddr, mask = _PAGE_PADDR_4U;
  421. if (kaddr >= PAGE_OFFSET)
  422. paddr = kaddr & mask;
  423. else {
  424. pte_t *ptep = virt_to_kpte(kaddr);
  425. paddr = pte_val(*ptep) & mask;
  426. }
  427. __flush_icache_page(paddr);
  428. }
  429. }
  430. }
  431. EXPORT_SYMBOL(flush_icache_range);
  432. void mmu_info(struct seq_file *m)
  433. {
  434. static const char *pgsz_strings[] = {
  435. "8K", "64K", "512K", "4MB", "32MB",
  436. "256MB", "2GB", "16GB",
  437. };
  438. int i, printed;
  439. if (tlb_type == cheetah)
  440. seq_printf(m, "MMU Type\t: Cheetah\n");
  441. else if (tlb_type == cheetah_plus)
  442. seq_printf(m, "MMU Type\t: Cheetah+\n");
  443. else if (tlb_type == spitfire)
  444. seq_printf(m, "MMU Type\t: Spitfire\n");
  445. else if (tlb_type == hypervisor)
  446. seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
  447. else
  448. seq_printf(m, "MMU Type\t: ???\n");
  449. seq_printf(m, "MMU PGSZs\t: ");
  450. printed = 0;
  451. for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
  452. if (cpu_pgsz_mask & (1UL << i)) {
  453. seq_printf(m, "%s%s",
  454. printed ? "," : "", pgsz_strings[i]);
  455. printed++;
  456. }
  457. }
  458. seq_putc(m, '\n');
  459. #ifdef CONFIG_DEBUG_DCFLUSH
  460. seq_printf(m, "DCPageFlushes\t: %d\n",
  461. atomic_read(&dcpage_flushes));
  462. #ifdef CONFIG_SMP
  463. seq_printf(m, "DCPageFlushesXC\t: %d\n",
  464. atomic_read(&dcpage_flushes_xcall));
  465. #endif /* CONFIG_SMP */
  466. #endif /* CONFIG_DEBUG_DCFLUSH */
  467. }
  468. struct linux_prom_translation prom_trans[512] __read_mostly;
  469. unsigned int prom_trans_ents __read_mostly;
  470. unsigned long kern_locked_tte_data;
  471. /* The obp translations are saved based on 8k pagesize, since obp can
  472. * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
  473. * HI_OBP_ADDRESS range are handled in ktlb.S.
  474. */
  475. static inline int in_obp_range(unsigned long vaddr)
  476. {
  477. return (vaddr >= LOW_OBP_ADDRESS &&
  478. vaddr < HI_OBP_ADDRESS);
  479. }
  480. static int cmp_ptrans(const void *a, const void *b)
  481. {
  482. const struct linux_prom_translation *x = a, *y = b;
  483. if (x->virt > y->virt)
  484. return 1;
  485. if (x->virt < y->virt)
  486. return -1;
  487. return 0;
  488. }
  489. /* Read OBP translations property into 'prom_trans[]'. */
  490. static void __init read_obp_translations(void)
  491. {
  492. int n, node, ents, first, last, i;
  493. node = prom_finddevice("/virtual-memory");
  494. n = prom_getproplen(node, "translations");
  495. if (unlikely(n == 0 || n == -1)) {
  496. prom_printf("prom_mappings: Couldn't get size.\n");
  497. prom_halt();
  498. }
  499. if (unlikely(n > sizeof(prom_trans))) {
  500. prom_printf("prom_mappings: Size %d is too big.\n", n);
  501. prom_halt();
  502. }
  503. if ((n = prom_getproperty(node, "translations",
  504. (char *)&prom_trans[0],
  505. sizeof(prom_trans))) == -1) {
  506. prom_printf("prom_mappings: Couldn't get property.\n");
  507. prom_halt();
  508. }
  509. n = n / sizeof(struct linux_prom_translation);
  510. ents = n;
  511. sort(prom_trans, ents, sizeof(struct linux_prom_translation),
  512. cmp_ptrans, NULL);
  513. /* Now kick out all the non-OBP entries. */
  514. for (i = 0; i < ents; i++) {
  515. if (in_obp_range(prom_trans[i].virt))
  516. break;
  517. }
  518. first = i;
  519. for (; i < ents; i++) {
  520. if (!in_obp_range(prom_trans[i].virt))
  521. break;
  522. }
  523. last = i;
  524. for (i = 0; i < (last - first); i++) {
  525. struct linux_prom_translation *src = &prom_trans[i + first];
  526. struct linux_prom_translation *dest = &prom_trans[i];
  527. *dest = *src;
  528. }
  529. for (; i < ents; i++) {
  530. struct linux_prom_translation *dest = &prom_trans[i];
  531. dest->virt = dest->size = dest->data = 0x0UL;
  532. }
  533. prom_trans_ents = last - first;
  534. if (tlb_type == spitfire) {
  535. /* Clear diag TTE bits. */
  536. for (i = 0; i < prom_trans_ents; i++)
  537. prom_trans[i].data &= ~0x0003fe0000000000UL;
  538. }
  539. /* Force execute bit on. */
  540. for (i = 0; i < prom_trans_ents; i++)
  541. prom_trans[i].data |= (tlb_type == hypervisor ?
  542. _PAGE_EXEC_4V : _PAGE_EXEC_4U);
  543. }
  544. static void __init hypervisor_tlb_lock(unsigned long vaddr,
  545. unsigned long pte,
  546. unsigned long mmu)
  547. {
  548. unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
  549. if (ret != 0) {
  550. prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
  551. "errors with %lx\n", vaddr, 0, pte, mmu, ret);
  552. prom_halt();
  553. }
  554. }
  555. static unsigned long kern_large_tte(unsigned long paddr);
  556. static void __init remap_kernel(void)
  557. {
  558. unsigned long phys_page, tte_vaddr, tte_data;
  559. int i, tlb_ent = sparc64_highest_locked_tlbent();
  560. tte_vaddr = (unsigned long) KERNBASE;
  561. phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
  562. tte_data = kern_large_tte(phys_page);
  563. kern_locked_tte_data = tte_data;
  564. /* Now lock us into the TLBs via Hypervisor or OBP. */
  565. if (tlb_type == hypervisor) {
  566. for (i = 0; i < num_kernel_image_mappings; i++) {
  567. hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
  568. hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
  569. tte_vaddr += 0x400000;
  570. tte_data += 0x400000;
  571. }
  572. } else {
  573. for (i = 0; i < num_kernel_image_mappings; i++) {
  574. prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
  575. prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
  576. tte_vaddr += 0x400000;
  577. tte_data += 0x400000;
  578. }
  579. sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
  580. }
  581. if (tlb_type == cheetah_plus) {
  582. sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
  583. CTX_CHEETAH_PLUS_NUC);
  584. sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
  585. sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
  586. }
  587. }
  588. static void __init inherit_prom_mappings(void)
  589. {
  590. /* Now fixup OBP's idea about where we really are mapped. */
  591. printk("Remapping the kernel... ");
  592. remap_kernel();
  593. printk("done.\n");
  594. }
  595. void prom_world(int enter)
  596. {
  597. if (!enter)
  598. set_fs(get_fs());
  599. __asm__ __volatile__("flushw");
  600. }
  601. void __flush_dcache_range(unsigned long start, unsigned long end)
  602. {
  603. unsigned long va;
  604. if (tlb_type == spitfire) {
  605. int n = 0;
  606. for (va = start; va < end; va += 32) {
  607. spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
  608. if (++n >= 512)
  609. break;
  610. }
  611. } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
  612. start = __pa(start);
  613. end = __pa(end);
  614. for (va = start; va < end; va += 32)
  615. __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
  616. "membar #Sync"
  617. : /* no outputs */
  618. : "r" (va),
  619. "i" (ASI_DCACHE_INVALIDATE));
  620. }
  621. }
  622. EXPORT_SYMBOL(__flush_dcache_range);
  623. /* get_new_mmu_context() uses "cache + 1". */
  624. DEFINE_SPINLOCK(ctx_alloc_lock);
  625. unsigned long tlb_context_cache = CTX_FIRST_VERSION;
  626. #define MAX_CTX_NR (1UL << CTX_NR_BITS)
  627. #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
  628. DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
  629. DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
  630. static void mmu_context_wrap(void)
  631. {
  632. unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
  633. unsigned long new_ver, new_ctx, old_ctx;
  634. struct mm_struct *mm;
  635. int cpu;
  636. bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
  637. /* Reserve kernel context */
  638. set_bit(0, mmu_context_bmap);
  639. new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
  640. if (unlikely(new_ver == 0))
  641. new_ver = CTX_FIRST_VERSION;
  642. tlb_context_cache = new_ver;
  643. /*
  644. * Make sure that any new mm that are added into per_cpu_secondary_mm,
  645. * are going to go through get_new_mmu_context() path.
  646. */
  647. mb();
  648. /*
  649. * Updated versions to current on those CPUs that had valid secondary
  650. * contexts
  651. */
  652. for_each_online_cpu(cpu) {
  653. /*
  654. * If a new mm is stored after we took this mm from the array,
  655. * it will go into get_new_mmu_context() path, because we
  656. * already bumped the version in tlb_context_cache.
  657. */
  658. mm = per_cpu(per_cpu_secondary_mm, cpu);
  659. if (unlikely(!mm || mm == &init_mm))
  660. continue;
  661. old_ctx = mm->context.sparc64_ctx_val;
  662. if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
  663. new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
  664. set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
  665. mm->context.sparc64_ctx_val = new_ctx;
  666. }
  667. }
  668. }
  669. /* Caller does TLB context flushing on local CPU if necessary.
  670. * The caller also ensures that CTX_VALID(mm->context) is false.
  671. *
  672. * We must be careful about boundary cases so that we never
  673. * let the user have CTX 0 (nucleus) or we ever use a CTX
  674. * version of zero (and thus NO_CONTEXT would not be caught
  675. * by version mis-match tests in mmu_context.h).
  676. *
  677. * Always invoked with interrupts disabled.
  678. */
  679. void get_new_mmu_context(struct mm_struct *mm)
  680. {
  681. unsigned long ctx, new_ctx;
  682. unsigned long orig_pgsz_bits;
  683. spin_lock(&ctx_alloc_lock);
  684. retry:
  685. /* wrap might have happened, test again if our context became valid */
  686. if (unlikely(CTX_VALID(mm->context)))
  687. goto out;
  688. orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
  689. ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
  690. new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
  691. if (new_ctx >= (1 << CTX_NR_BITS)) {
  692. new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
  693. if (new_ctx >= ctx) {
  694. mmu_context_wrap();
  695. goto retry;
  696. }
  697. }
  698. if (mm->context.sparc64_ctx_val)
  699. cpumask_clear(mm_cpumask(mm));
  700. mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
  701. new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
  702. tlb_context_cache = new_ctx;
  703. mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
  704. out:
  705. spin_unlock(&ctx_alloc_lock);
  706. }
  707. static int numa_enabled = 1;
  708. static int numa_debug;
  709. static int __init early_numa(char *p)
  710. {
  711. if (!p)
  712. return 0;
  713. if (strstr(p, "off"))
  714. numa_enabled = 0;
  715. if (strstr(p, "debug"))
  716. numa_debug = 1;
  717. return 0;
  718. }
  719. early_param("numa", early_numa);
  720. #define numadbg(f, a...) \
  721. do { if (numa_debug) \
  722. printk(KERN_INFO f, ## a); \
  723. } while (0)
  724. static void __init find_ramdisk(unsigned long phys_base)
  725. {
  726. #ifdef CONFIG_BLK_DEV_INITRD
  727. if (sparc_ramdisk_image || sparc_ramdisk_image64) {
  728. unsigned long ramdisk_image;
  729. /* Older versions of the bootloader only supported a
  730. * 32-bit physical address for the ramdisk image
  731. * location, stored at sparc_ramdisk_image. Newer
  732. * SILO versions set sparc_ramdisk_image to zero and
  733. * provide a full 64-bit physical address at
  734. * sparc_ramdisk_image64.
  735. */
  736. ramdisk_image = sparc_ramdisk_image;
  737. if (!ramdisk_image)
  738. ramdisk_image = sparc_ramdisk_image64;
  739. /* Another bootloader quirk. The bootloader normalizes
  740. * the physical address to KERNBASE, so we have to
  741. * factor that back out and add in the lowest valid
  742. * physical page address to get the true physical address.
  743. */
  744. ramdisk_image -= KERNBASE;
  745. ramdisk_image += phys_base;
  746. numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
  747. ramdisk_image, sparc_ramdisk_size);
  748. initrd_start = ramdisk_image;
  749. initrd_end = ramdisk_image + sparc_ramdisk_size;
  750. memblock_reserve(initrd_start, sparc_ramdisk_size);
  751. initrd_start += PAGE_OFFSET;
  752. initrd_end += PAGE_OFFSET;
  753. }
  754. #endif
  755. }
  756. struct node_mem_mask {
  757. unsigned long mask;
  758. unsigned long match;
  759. };
  760. static struct node_mem_mask node_masks[MAX_NUMNODES];
  761. static int num_node_masks;
  762. #ifdef CONFIG_NEED_MULTIPLE_NODES
  763. struct mdesc_mlgroup {
  764. u64 node;
  765. u64 latency;
  766. u64 match;
  767. u64 mask;
  768. };
  769. static struct mdesc_mlgroup *mlgroups;
  770. static int num_mlgroups;
  771. int numa_cpu_lookup_table[NR_CPUS];
  772. cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
  773. struct mdesc_mblock {
  774. u64 base;
  775. u64 size;
  776. u64 offset; /* RA-to-PA */
  777. };
  778. static struct mdesc_mblock *mblocks;
  779. static int num_mblocks;
  780. static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
  781. {
  782. struct mdesc_mblock *m = NULL;
  783. int i;
  784. for (i = 0; i < num_mblocks; i++) {
  785. m = &mblocks[i];
  786. if (addr >= m->base &&
  787. addr < (m->base + m->size)) {
  788. break;
  789. }
  790. }
  791. return m;
  792. }
  793. static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
  794. {
  795. int prev_nid, new_nid;
  796. prev_nid = NUMA_NO_NODE;
  797. for ( ; start < end; start += PAGE_SIZE) {
  798. for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
  799. struct node_mem_mask *p = &node_masks[new_nid];
  800. if ((start & p->mask) == p->match) {
  801. if (prev_nid == NUMA_NO_NODE)
  802. prev_nid = new_nid;
  803. break;
  804. }
  805. }
  806. if (new_nid == num_node_masks) {
  807. prev_nid = 0;
  808. WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
  809. start);
  810. break;
  811. }
  812. if (prev_nid != new_nid)
  813. break;
  814. }
  815. *nid = prev_nid;
  816. return start > end ? end : start;
  817. }
  818. static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
  819. {
  820. u64 ret_end, pa_start, m_mask, m_match, m_end;
  821. struct mdesc_mblock *mblock;
  822. int _nid, i;
  823. if (tlb_type != hypervisor)
  824. return memblock_nid_range_sun4u(start, end, nid);
  825. mblock = addr_to_mblock(start);
  826. if (!mblock) {
  827. WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
  828. start);
  829. _nid = 0;
  830. ret_end = end;
  831. goto done;
  832. }
  833. pa_start = start + mblock->offset;
  834. m_match = 0;
  835. m_mask = 0;
  836. for (_nid = 0; _nid < num_node_masks; _nid++) {
  837. struct node_mem_mask *const m = &node_masks[_nid];
  838. if ((pa_start & m->mask) == m->match) {
  839. m_match = m->match;
  840. m_mask = m->mask;
  841. break;
  842. }
  843. }
  844. if (num_node_masks == _nid) {
  845. /* We could not find NUMA group, so default to 0, but lets
  846. * search for latency group, so we could calculate the correct
  847. * end address that we return
  848. */
  849. _nid = 0;
  850. for (i = 0; i < num_mlgroups; i++) {
  851. struct mdesc_mlgroup *const m = &mlgroups[i];
  852. if ((pa_start & m->mask) == m->match) {
  853. m_match = m->match;
  854. m_mask = m->mask;
  855. break;
  856. }
  857. }
  858. if (i == num_mlgroups) {
  859. WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
  860. start);
  861. ret_end = end;
  862. goto done;
  863. }
  864. }
  865. /*
  866. * Each latency group has match and mask, and each memory block has an
  867. * offset. An address belongs to a latency group if its address matches
  868. * the following formula: ((addr + offset) & mask) == match
  869. * It is, however, slow to check every single page if it matches a
  870. * particular latency group. As optimization we calculate end value by
  871. * using bit arithmetics.
  872. */
  873. m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
  874. m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
  875. ret_end = m_end > end ? end : m_end;
  876. done:
  877. *nid = _nid;
  878. return ret_end;
  879. }
  880. #endif
  881. /* This must be invoked after performing all of the necessary
  882. * memblock_set_node() calls for 'nid'. We need to be able to get
  883. * correct data from get_pfn_range_for_nid().
  884. */
  885. static void __init allocate_node_data(int nid)
  886. {
  887. struct pglist_data *p;
  888. unsigned long start_pfn, end_pfn;
  889. #ifdef CONFIG_NEED_MULTIPLE_NODES
  890. NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
  891. SMP_CACHE_BYTES, nid);
  892. if (!NODE_DATA(nid)) {
  893. prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
  894. prom_halt();
  895. }
  896. NODE_DATA(nid)->node_id = nid;
  897. #endif
  898. p = NODE_DATA(nid);
  899. get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
  900. p->node_start_pfn = start_pfn;
  901. p->node_spanned_pages = end_pfn - start_pfn;
  902. }
  903. static void init_node_masks_nonnuma(void)
  904. {
  905. #ifdef CONFIG_NEED_MULTIPLE_NODES
  906. int i;
  907. #endif
  908. numadbg("Initializing tables for non-numa.\n");
  909. node_masks[0].mask = 0;
  910. node_masks[0].match = 0;
  911. num_node_masks = 1;
  912. #ifdef CONFIG_NEED_MULTIPLE_NODES
  913. for (i = 0; i < NR_CPUS; i++)
  914. numa_cpu_lookup_table[i] = 0;
  915. cpumask_setall(&numa_cpumask_lookup_table[0]);
  916. #endif
  917. }
  918. #ifdef CONFIG_NEED_MULTIPLE_NODES
  919. struct pglist_data *node_data[MAX_NUMNODES];
  920. EXPORT_SYMBOL(numa_cpu_lookup_table);
  921. EXPORT_SYMBOL(numa_cpumask_lookup_table);
  922. EXPORT_SYMBOL(node_data);
  923. static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
  924. u32 cfg_handle)
  925. {
  926. u64 arc;
  927. mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
  928. u64 target = mdesc_arc_target(md, arc);
  929. const u64 *val;
  930. val = mdesc_get_property(md, target,
  931. "cfg-handle", NULL);
  932. if (val && *val == cfg_handle)
  933. return 0;
  934. }
  935. return -ENODEV;
  936. }
  937. static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
  938. u32 cfg_handle)
  939. {
  940. u64 arc, candidate, best_latency = ~(u64)0;
  941. candidate = MDESC_NODE_NULL;
  942. mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
  943. u64 target = mdesc_arc_target(md, arc);
  944. const char *name = mdesc_node_name(md, target);
  945. const u64 *val;
  946. if (strcmp(name, "pio-latency-group"))
  947. continue;
  948. val = mdesc_get_property(md, target, "latency", NULL);
  949. if (!val)
  950. continue;
  951. if (*val < best_latency) {
  952. candidate = target;
  953. best_latency = *val;
  954. }
  955. }
  956. if (candidate == MDESC_NODE_NULL)
  957. return -ENODEV;
  958. return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
  959. }
  960. int of_node_to_nid(struct device_node *dp)
  961. {
  962. const struct linux_prom64_registers *regs;
  963. struct mdesc_handle *md;
  964. u32 cfg_handle;
  965. int count, nid;
  966. u64 grp;
  967. /* This is the right thing to do on currently supported
  968. * SUN4U NUMA platforms as well, as the PCI controller does
  969. * not sit behind any particular memory controller.
  970. */
  971. if (!mlgroups)
  972. return -1;
  973. regs = of_get_property(dp, "reg", NULL);
  974. if (!regs)
  975. return -1;
  976. cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
  977. md = mdesc_grab();
  978. count = 0;
  979. nid = NUMA_NO_NODE;
  980. mdesc_for_each_node_by_name(md, grp, "group") {
  981. if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
  982. nid = count;
  983. break;
  984. }
  985. count++;
  986. }
  987. mdesc_release(md);
  988. return nid;
  989. }
  990. static void __init add_node_ranges(void)
  991. {
  992. phys_addr_t start, end;
  993. unsigned long prev_max;
  994. u64 i;
  995. memblock_resized:
  996. prev_max = memblock.memory.max;
  997. for_each_mem_range(i, &start, &end) {
  998. while (start < end) {
  999. unsigned long this_end;
  1000. int nid;
  1001. this_end = memblock_nid_range(start, end, &nid);
  1002. numadbg("Setting memblock NUMA node nid[%d] "
  1003. "start[%llx] end[%lx]\n",
  1004. nid, start, this_end);
  1005. memblock_set_node(start, this_end - start,
  1006. &memblock.memory, nid);
  1007. if (memblock.memory.max != prev_max)
  1008. goto memblock_resized;
  1009. start = this_end;
  1010. }
  1011. }
  1012. }
  1013. static int __init grab_mlgroups(struct mdesc_handle *md)
  1014. {
  1015. unsigned long paddr;
  1016. int count = 0;
  1017. u64 node;
  1018. mdesc_for_each_node_by_name(md, node, "memory-latency-group")
  1019. count++;
  1020. if (!count)
  1021. return -ENOENT;
  1022. paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
  1023. SMP_CACHE_BYTES);
  1024. if (!paddr)
  1025. return -ENOMEM;
  1026. mlgroups = __va(paddr);
  1027. num_mlgroups = count;
  1028. count = 0;
  1029. mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
  1030. struct mdesc_mlgroup *m = &mlgroups[count++];
  1031. const u64 *val;
  1032. m->node = node;
  1033. val = mdesc_get_property(md, node, "latency", NULL);
  1034. m->latency = *val;
  1035. val = mdesc_get_property(md, node, "address-match", NULL);
  1036. m->match = *val;
  1037. val = mdesc_get_property(md, node, "address-mask", NULL);
  1038. m->mask = *val;
  1039. numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
  1040. "match[%llx] mask[%llx]\n",
  1041. count - 1, m->node, m->latency, m->match, m->mask);
  1042. }
  1043. return 0;
  1044. }
  1045. static int __init grab_mblocks(struct mdesc_handle *md)
  1046. {
  1047. unsigned long paddr;
  1048. int count = 0;
  1049. u64 node;
  1050. mdesc_for_each_node_by_name(md, node, "mblock")
  1051. count++;
  1052. if (!count)
  1053. return -ENOENT;
  1054. paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
  1055. SMP_CACHE_BYTES);
  1056. if (!paddr)
  1057. return -ENOMEM;
  1058. mblocks = __va(paddr);
  1059. num_mblocks = count;
  1060. count = 0;
  1061. mdesc_for_each_node_by_name(md, node, "mblock") {
  1062. struct mdesc_mblock *m = &mblocks[count++];
  1063. const u64 *val;
  1064. val = mdesc_get_property(md, node, "base", NULL);
  1065. m->base = *val;
  1066. val = mdesc_get_property(md, node, "size", NULL);
  1067. m->size = *val;
  1068. val = mdesc_get_property(md, node,
  1069. "address-congruence-offset", NULL);
  1070. /* The address-congruence-offset property is optional.
  1071. * Explicity zero it be identifty this.
  1072. */
  1073. if (val)
  1074. m->offset = *val;
  1075. else
  1076. m->offset = 0UL;
  1077. numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
  1078. count - 1, m->base, m->size, m->offset);
  1079. }
  1080. return 0;
  1081. }
  1082. static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
  1083. u64 grp, cpumask_t *mask)
  1084. {
  1085. u64 arc;
  1086. cpumask_clear(mask);
  1087. mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
  1088. u64 target = mdesc_arc_target(md, arc);
  1089. const char *name = mdesc_node_name(md, target);
  1090. const u64 *id;
  1091. if (strcmp(name, "cpu"))
  1092. continue;
  1093. id = mdesc_get_property(md, target, "id", NULL);
  1094. if (*id < nr_cpu_ids)
  1095. cpumask_set_cpu(*id, mask);
  1096. }
  1097. }
  1098. static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
  1099. {
  1100. int i;
  1101. for (i = 0; i < num_mlgroups; i++) {
  1102. struct mdesc_mlgroup *m = &mlgroups[i];
  1103. if (m->node == node)
  1104. return m;
  1105. }
  1106. return NULL;
  1107. }
  1108. int __node_distance(int from, int to)
  1109. {
  1110. if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
  1111. pr_warn("Returning default NUMA distance value for %d->%d\n",
  1112. from, to);
  1113. return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
  1114. }
  1115. return numa_latency[from][to];
  1116. }
  1117. EXPORT_SYMBOL(__node_distance);
  1118. static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
  1119. {
  1120. int i;
  1121. for (i = 0; i < MAX_NUMNODES; i++) {
  1122. struct node_mem_mask *n = &node_masks[i];
  1123. if ((grp->mask == n->mask) && (grp->match == n->match))
  1124. break;
  1125. }
  1126. return i;
  1127. }
  1128. static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
  1129. u64 grp, int index)
  1130. {
  1131. u64 arc;
  1132. mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
  1133. int tnode;
  1134. u64 target = mdesc_arc_target(md, arc);
  1135. struct mdesc_mlgroup *m = find_mlgroup(target);
  1136. if (!m)
  1137. continue;
  1138. tnode = find_best_numa_node_for_mlgroup(m);
  1139. if (tnode == MAX_NUMNODES)
  1140. continue;
  1141. numa_latency[index][tnode] = m->latency;
  1142. }
  1143. }
  1144. static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
  1145. int index)
  1146. {
  1147. struct mdesc_mlgroup *candidate = NULL;
  1148. u64 arc, best_latency = ~(u64)0;
  1149. struct node_mem_mask *n;
  1150. mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
  1151. u64 target = mdesc_arc_target(md, arc);
  1152. struct mdesc_mlgroup *m = find_mlgroup(target);
  1153. if (!m)
  1154. continue;
  1155. if (m->latency < best_latency) {
  1156. candidate = m;
  1157. best_latency = m->latency;
  1158. }
  1159. }
  1160. if (!candidate)
  1161. return -ENOENT;
  1162. if (num_node_masks != index) {
  1163. printk(KERN_ERR "Inconsistent NUMA state, "
  1164. "index[%d] != num_node_masks[%d]\n",
  1165. index, num_node_masks);
  1166. return -EINVAL;
  1167. }
  1168. n = &node_masks[num_node_masks++];
  1169. n->mask = candidate->mask;
  1170. n->match = candidate->match;
  1171. numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
  1172. index, n->mask, n->match, candidate->latency);
  1173. return 0;
  1174. }
  1175. static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
  1176. int index)
  1177. {
  1178. cpumask_t mask;
  1179. int cpu;
  1180. numa_parse_mdesc_group_cpus(md, grp, &mask);
  1181. for_each_cpu(cpu, &mask)
  1182. numa_cpu_lookup_table[cpu] = index;
  1183. cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
  1184. if (numa_debug) {
  1185. printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
  1186. for_each_cpu(cpu, &mask)
  1187. printk("%d ", cpu);
  1188. printk("]\n");
  1189. }
  1190. return numa_attach_mlgroup(md, grp, index);
  1191. }
  1192. static int __init numa_parse_mdesc(void)
  1193. {
  1194. struct mdesc_handle *md = mdesc_grab();
  1195. int i, j, err, count;
  1196. u64 node;
  1197. node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
  1198. if (node == MDESC_NODE_NULL) {
  1199. mdesc_release(md);
  1200. return -ENOENT;
  1201. }
  1202. err = grab_mblocks(md);
  1203. if (err < 0)
  1204. goto out;
  1205. err = grab_mlgroups(md);
  1206. if (err < 0)
  1207. goto out;
  1208. count = 0;
  1209. mdesc_for_each_node_by_name(md, node, "group") {
  1210. err = numa_parse_mdesc_group(md, node, count);
  1211. if (err < 0)
  1212. break;
  1213. count++;
  1214. }
  1215. count = 0;
  1216. mdesc_for_each_node_by_name(md, node, "group") {
  1217. find_numa_latencies_for_group(md, node, count);
  1218. count++;
  1219. }
  1220. /* Normalize numa latency matrix according to ACPI SLIT spec. */
  1221. for (i = 0; i < MAX_NUMNODES; i++) {
  1222. u64 self_latency = numa_latency[i][i];
  1223. for (j = 0; j < MAX_NUMNODES; j++) {
  1224. numa_latency[i][j] =
  1225. (numa_latency[i][j] * LOCAL_DISTANCE) /
  1226. self_latency;
  1227. }
  1228. }
  1229. add_node_ranges();
  1230. for (i = 0; i < num_node_masks; i++) {
  1231. allocate_node_data(i);
  1232. node_set_online(i);
  1233. }
  1234. err = 0;
  1235. out:
  1236. mdesc_release(md);
  1237. return err;
  1238. }
  1239. static int __init numa_parse_jbus(void)
  1240. {
  1241. unsigned long cpu, index;
  1242. /* NUMA node id is encoded in bits 36 and higher, and there is
  1243. * a 1-to-1 mapping from CPU ID to NUMA node ID.
  1244. */
  1245. index = 0;
  1246. for_each_present_cpu(cpu) {
  1247. numa_cpu_lookup_table[cpu] = index;
  1248. cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
  1249. node_masks[index].mask = ~((1UL << 36UL) - 1UL);
  1250. node_masks[index].match = cpu << 36UL;
  1251. index++;
  1252. }
  1253. num_node_masks = index;
  1254. add_node_ranges();
  1255. for (index = 0; index < num_node_masks; index++) {
  1256. allocate_node_data(index);
  1257. node_set_online(index);
  1258. }
  1259. return 0;
  1260. }
  1261. static int __init numa_parse_sun4u(void)
  1262. {
  1263. if (tlb_type == cheetah || tlb_type == cheetah_plus) {
  1264. unsigned long ver;
  1265. __asm__ ("rdpr %%ver, %0" : "=r" (ver));
  1266. if ((ver >> 32UL) == __JALAPENO_ID ||
  1267. (ver >> 32UL) == __SERRANO_ID)
  1268. return numa_parse_jbus();
  1269. }
  1270. return -1;
  1271. }
  1272. static int __init bootmem_init_numa(void)
  1273. {
  1274. int i, j;
  1275. int err = -1;
  1276. numadbg("bootmem_init_numa()\n");
  1277. /* Some sane defaults for numa latency values */
  1278. for (i = 0; i < MAX_NUMNODES; i++) {
  1279. for (j = 0; j < MAX_NUMNODES; j++)
  1280. numa_latency[i][j] = (i == j) ?
  1281. LOCAL_DISTANCE : REMOTE_DISTANCE;
  1282. }
  1283. if (numa_enabled) {
  1284. if (tlb_type == hypervisor)
  1285. err = numa_parse_mdesc();
  1286. else
  1287. err = numa_parse_sun4u();
  1288. }
  1289. return err;
  1290. }
  1291. #else
  1292. static int bootmem_init_numa(void)
  1293. {
  1294. return -1;
  1295. }
  1296. #endif
  1297. static void __init bootmem_init_nonnuma(void)
  1298. {
  1299. unsigned long top_of_ram = memblock_end_of_DRAM();
  1300. unsigned long total_ram = memblock_phys_mem_size();
  1301. numadbg("bootmem_init_nonnuma()\n");
  1302. printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
  1303. top_of_ram, total_ram);
  1304. printk(KERN_INFO "Memory hole size: %ldMB\n",
  1305. (top_of_ram - total_ram) >> 20);
  1306. init_node_masks_nonnuma();
  1307. memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
  1308. allocate_node_data(0);
  1309. node_set_online(0);
  1310. }
  1311. static unsigned long __init bootmem_init(unsigned long phys_base)
  1312. {
  1313. unsigned long end_pfn;
  1314. end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
  1315. max_pfn = max_low_pfn = end_pfn;
  1316. min_low_pfn = (phys_base >> PAGE_SHIFT);
  1317. if (bootmem_init_numa() < 0)
  1318. bootmem_init_nonnuma();
  1319. /* Dump memblock with node info. */
  1320. memblock_dump_all();
  1321. /* XXX cpu notifier XXX */
  1322. sparse_init();
  1323. return end_pfn;
  1324. }
  1325. static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
  1326. static int pall_ents __initdata;
  1327. static unsigned long max_phys_bits = 40;
  1328. bool kern_addr_valid(unsigned long addr)
  1329. {
  1330. pgd_t *pgd;
  1331. p4d_t *p4d;
  1332. pud_t *pud;
  1333. pmd_t *pmd;
  1334. pte_t *pte;
  1335. if ((long)addr < 0L) {
  1336. unsigned long pa = __pa(addr);
  1337. if ((pa >> max_phys_bits) != 0UL)
  1338. return false;
  1339. return pfn_valid(pa >> PAGE_SHIFT);
  1340. }
  1341. if (addr >= (unsigned long) KERNBASE &&
  1342. addr < (unsigned long)&_end)
  1343. return true;
  1344. pgd = pgd_offset_k(addr);
  1345. if (pgd_none(*pgd))
  1346. return false;
  1347. p4d = p4d_offset(pgd, addr);
  1348. if (p4d_none(*p4d))
  1349. return false;
  1350. pud = pud_offset(p4d, addr);
  1351. if (pud_none(*pud))
  1352. return false;
  1353. if (pud_large(*pud))
  1354. return pfn_valid(pud_pfn(*pud));
  1355. pmd = pmd_offset(pud, addr);
  1356. if (pmd_none(*pmd))
  1357. return false;
  1358. if (pmd_large(*pmd))
  1359. return pfn_valid(pmd_pfn(*pmd));
  1360. pte = pte_offset_kernel(pmd, addr);
  1361. if (pte_none(*pte))
  1362. return false;
  1363. return pfn_valid(pte_pfn(*pte));
  1364. }
  1365. EXPORT_SYMBOL(kern_addr_valid);
  1366. static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
  1367. unsigned long vend,
  1368. pud_t *pud)
  1369. {
  1370. const unsigned long mask16gb = (1UL << 34) - 1UL;
  1371. u64 pte_val = vstart;
  1372. /* Each PUD is 8GB */
  1373. if ((vstart & mask16gb) ||
  1374. (vend - vstart <= mask16gb)) {
  1375. pte_val ^= kern_linear_pte_xor[2];
  1376. pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
  1377. return vstart + PUD_SIZE;
  1378. }
  1379. pte_val ^= kern_linear_pte_xor[3];
  1380. pte_val |= _PAGE_PUD_HUGE;
  1381. vend = vstart + mask16gb + 1UL;
  1382. while (vstart < vend) {
  1383. pud_val(*pud) = pte_val;
  1384. pte_val += PUD_SIZE;
  1385. vstart += PUD_SIZE;
  1386. pud++;
  1387. }
  1388. return vstart;
  1389. }
  1390. static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
  1391. bool guard)
  1392. {
  1393. if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
  1394. return true;
  1395. return false;
  1396. }
  1397. static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
  1398. unsigned long vend,
  1399. pmd_t *pmd)
  1400. {
  1401. const unsigned long mask256mb = (1UL << 28) - 1UL;
  1402. const unsigned long mask2gb = (1UL << 31) - 1UL;
  1403. u64 pte_val = vstart;
  1404. /* Each PMD is 8MB */
  1405. if ((vstart & mask256mb) ||
  1406. (vend - vstart <= mask256mb)) {
  1407. pte_val ^= kern_linear_pte_xor[0];
  1408. pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
  1409. return vstart + PMD_SIZE;
  1410. }
  1411. if ((vstart & mask2gb) ||
  1412. (vend - vstart <= mask2gb)) {
  1413. pte_val ^= kern_linear_pte_xor[1];
  1414. pte_val |= _PAGE_PMD_HUGE;
  1415. vend = vstart + mask256mb + 1UL;
  1416. } else {
  1417. pte_val ^= kern_linear_pte_xor[2];
  1418. pte_val |= _PAGE_PMD_HUGE;
  1419. vend = vstart + mask2gb + 1UL;
  1420. }
  1421. while (vstart < vend) {
  1422. pmd_val(*pmd) = pte_val;
  1423. pte_val += PMD_SIZE;
  1424. vstart += PMD_SIZE;
  1425. pmd++;
  1426. }
  1427. return vstart;
  1428. }
  1429. static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
  1430. bool guard)
  1431. {
  1432. if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
  1433. return true;
  1434. return false;
  1435. }
  1436. static unsigned long __ref kernel_map_range(unsigned long pstart,
  1437. unsigned long pend, pgprot_t prot,
  1438. bool use_huge)
  1439. {
  1440. unsigned long vstart = PAGE_OFFSET + pstart;
  1441. unsigned long vend = PAGE_OFFSET + pend;
  1442. unsigned long alloc_bytes = 0UL;
  1443. if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
  1444. prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
  1445. vstart, vend);
  1446. prom_halt();
  1447. }
  1448. while (vstart < vend) {
  1449. unsigned long this_end, paddr = __pa(vstart);
  1450. pgd_t *pgd = pgd_offset_k(vstart);
  1451. p4d_t *p4d;
  1452. pud_t *pud;
  1453. pmd_t *pmd;
  1454. pte_t *pte;
  1455. if (pgd_none(*pgd)) {
  1456. pud_t *new;
  1457. new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
  1458. PAGE_SIZE);
  1459. if (!new)
  1460. goto err_alloc;
  1461. alloc_bytes += PAGE_SIZE;
  1462. pgd_populate(&init_mm, pgd, new);
  1463. }
  1464. p4d = p4d_offset(pgd, vstart);
  1465. if (p4d_none(*p4d)) {
  1466. pud_t *new;
  1467. new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
  1468. PAGE_SIZE);
  1469. if (!new)
  1470. goto err_alloc;
  1471. alloc_bytes += PAGE_SIZE;
  1472. p4d_populate(&init_mm, p4d, new);
  1473. }
  1474. pud = pud_offset(p4d, vstart);
  1475. if (pud_none(*pud)) {
  1476. pmd_t *new;
  1477. if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
  1478. vstart = kernel_map_hugepud(vstart, vend, pud);
  1479. continue;
  1480. }
  1481. new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
  1482. PAGE_SIZE);
  1483. if (!new)
  1484. goto err_alloc;
  1485. alloc_bytes += PAGE_SIZE;
  1486. pud_populate(&init_mm, pud, new);
  1487. }
  1488. pmd = pmd_offset(pud, vstart);
  1489. if (pmd_none(*pmd)) {
  1490. pte_t *new;
  1491. if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
  1492. vstart = kernel_map_hugepmd(vstart, vend, pmd);
  1493. continue;
  1494. }
  1495. new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
  1496. PAGE_SIZE);
  1497. if (!new)
  1498. goto err_alloc;
  1499. alloc_bytes += PAGE_SIZE;
  1500. pmd_populate_kernel(&init_mm, pmd, new);
  1501. }
  1502. pte = pte_offset_kernel(pmd, vstart);
  1503. this_end = (vstart + PMD_SIZE) & PMD_MASK;
  1504. if (this_end > vend)
  1505. this_end = vend;
  1506. while (vstart < this_end) {
  1507. pte_val(*pte) = (paddr | pgprot_val(prot));
  1508. vstart += PAGE_SIZE;
  1509. paddr += PAGE_SIZE;
  1510. pte++;
  1511. }
  1512. }
  1513. return alloc_bytes;
  1514. err_alloc:
  1515. panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
  1516. __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
  1517. return -ENOMEM;
  1518. }
  1519. static void __init flush_all_kernel_tsbs(void)
  1520. {
  1521. int i;
  1522. for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
  1523. struct tsb *ent = &swapper_tsb[i];
  1524. ent->tag = (1UL << TSB_TAG_INVALID_BIT);
  1525. }
  1526. #ifndef CONFIG_DEBUG_PAGEALLOC
  1527. for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
  1528. struct tsb *ent = &swapper_4m_tsb[i];
  1529. ent->tag = (1UL << TSB_TAG_INVALID_BIT);
  1530. }
  1531. #endif
  1532. }
  1533. extern unsigned int kvmap_linear_patch[1];
  1534. static void __init kernel_physical_mapping_init(void)
  1535. {
  1536. unsigned long i, mem_alloced = 0UL;
  1537. bool use_huge = true;
  1538. #ifdef CONFIG_DEBUG_PAGEALLOC
  1539. use_huge = false;
  1540. #endif
  1541. for (i = 0; i < pall_ents; i++) {
  1542. unsigned long phys_start, phys_end;
  1543. phys_start = pall[i].phys_addr;
  1544. phys_end = phys_start + pall[i].reg_size;
  1545. mem_alloced += kernel_map_range(phys_start, phys_end,
  1546. PAGE_KERNEL, use_huge);
  1547. }
  1548. printk("Allocated %ld bytes for kernel page tables.\n",
  1549. mem_alloced);
  1550. kvmap_linear_patch[0] = 0x01000000; /* nop */
  1551. flushi(&kvmap_linear_patch[0]);
  1552. flush_all_kernel_tsbs();
  1553. __flush_tlb_all();
  1554. }
  1555. #ifdef CONFIG_DEBUG_PAGEALLOC
  1556. void __kernel_map_pages(struct page *page, int numpages, int enable)
  1557. {
  1558. unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
  1559. unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
  1560. kernel_map_range(phys_start, phys_end,
  1561. (enable ? PAGE_KERNEL : __pgprot(0)), false);
  1562. flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
  1563. PAGE_OFFSET + phys_end);
  1564. /* we should perform an IPI and flush all tlbs,
  1565. * but that can deadlock->flush only current cpu.
  1566. */
  1567. __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
  1568. PAGE_OFFSET + phys_end);
  1569. }
  1570. #endif
  1571. unsigned long __init find_ecache_flush_span(unsigned long size)
  1572. {
  1573. int i;
  1574. for (i = 0; i < pavail_ents; i++) {
  1575. if (pavail[i].reg_size >= size)
  1576. return pavail[i].phys_addr;
  1577. }
  1578. return ~0UL;
  1579. }
  1580. unsigned long PAGE_OFFSET;
  1581. EXPORT_SYMBOL(PAGE_OFFSET);
  1582. unsigned long VMALLOC_END = 0x0000010000000000UL;
  1583. EXPORT_SYMBOL(VMALLOC_END);
  1584. unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
  1585. unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
  1586. static void __init setup_page_offset(void)
  1587. {
  1588. if (tlb_type == cheetah || tlb_type == cheetah_plus) {
  1589. /* Cheetah/Panther support a full 64-bit virtual
  1590. * address, so we can use all that our page tables
  1591. * support.
  1592. */
  1593. sparc64_va_hole_top = 0xfff0000000000000UL;
  1594. sparc64_va_hole_bottom = 0x0010000000000000UL;
  1595. max_phys_bits = 42;
  1596. } else if (tlb_type == hypervisor) {
  1597. switch (sun4v_chip_type) {
  1598. case SUN4V_CHIP_NIAGARA1:
  1599. case SUN4V_CHIP_NIAGARA2:
  1600. /* T1 and T2 support 48-bit virtual addresses. */
  1601. sparc64_va_hole_top = 0xffff800000000000UL;
  1602. sparc64_va_hole_bottom = 0x0000800000000000UL;
  1603. max_phys_bits = 39;
  1604. break;
  1605. case SUN4V_CHIP_NIAGARA3:
  1606. /* T3 supports 48-bit virtual addresses. */
  1607. sparc64_va_hole_top = 0xffff800000000000UL;
  1608. sparc64_va_hole_bottom = 0x0000800000000000UL;
  1609. max_phys_bits = 43;
  1610. break;
  1611. case SUN4V_CHIP_NIAGARA4:
  1612. case SUN4V_CHIP_NIAGARA5:
  1613. case SUN4V_CHIP_SPARC64X:
  1614. case SUN4V_CHIP_SPARC_M6:
  1615. /* T4 and later support 52-bit virtual addresses. */
  1616. sparc64_va_hole_top = 0xfff8000000000000UL;
  1617. sparc64_va_hole_bottom = 0x0008000000000000UL;
  1618. max_phys_bits = 47;
  1619. break;
  1620. case SUN4V_CHIP_SPARC_M7:
  1621. case SUN4V_CHIP_SPARC_SN:
  1622. /* M7 and later support 52-bit virtual addresses. */
  1623. sparc64_va_hole_top = 0xfff8000000000000UL;
  1624. sparc64_va_hole_bottom = 0x0008000000000000UL;
  1625. max_phys_bits = 49;
  1626. break;
  1627. case SUN4V_CHIP_SPARC_M8:
  1628. default:
  1629. /* M8 and later support 54-bit virtual addresses.
  1630. * However, restricting M8 and above VA bits to 53
  1631. * as 4-level page table cannot support more than
  1632. * 53 VA bits.
  1633. */
  1634. sparc64_va_hole_top = 0xfff0000000000000UL;
  1635. sparc64_va_hole_bottom = 0x0010000000000000UL;
  1636. max_phys_bits = 51;
  1637. break;
  1638. }
  1639. }
  1640. if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
  1641. prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
  1642. max_phys_bits);
  1643. prom_halt();
  1644. }
  1645. PAGE_OFFSET = sparc64_va_hole_top;
  1646. VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
  1647. (sparc64_va_hole_bottom >> 2));
  1648. pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
  1649. PAGE_OFFSET, max_phys_bits);
  1650. pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
  1651. VMALLOC_START, VMALLOC_END);
  1652. pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
  1653. VMEMMAP_BASE, VMEMMAP_BASE << 1);
  1654. }
  1655. static void __init tsb_phys_patch(void)
  1656. {
  1657. struct tsb_ldquad_phys_patch_entry *pquad;
  1658. struct tsb_phys_patch_entry *p;
  1659. pquad = &__tsb_ldquad_phys_patch;
  1660. while (pquad < &__tsb_ldquad_phys_patch_end) {
  1661. unsigned long addr = pquad->addr;
  1662. if (tlb_type == hypervisor)
  1663. *(unsigned int *) addr = pquad->sun4v_insn;
  1664. else
  1665. *(unsigned int *) addr = pquad->sun4u_insn;
  1666. wmb();
  1667. __asm__ __volatile__("flush %0"
  1668. : /* no outputs */
  1669. : "r" (addr));
  1670. pquad++;
  1671. }
  1672. p = &__tsb_phys_patch;
  1673. while (p < &__tsb_phys_patch_end) {
  1674. unsigned long addr = p->addr;
  1675. *(unsigned int *) addr = p->insn;
  1676. wmb();
  1677. __asm__ __volatile__("flush %0"
  1678. : /* no outputs */
  1679. : "r" (addr));
  1680. p++;
  1681. }
  1682. }
  1683. /* Don't mark as init, we give this to the Hypervisor. */
  1684. #ifndef CONFIG_DEBUG_PAGEALLOC
  1685. #define NUM_KTSB_DESCR 2
  1686. #else
  1687. #define NUM_KTSB_DESCR 1
  1688. #endif
  1689. static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
  1690. /* The swapper TSBs are loaded with a base sequence of:
  1691. *
  1692. * sethi %uhi(SYMBOL), REG1
  1693. * sethi %hi(SYMBOL), REG2
  1694. * or REG1, %ulo(SYMBOL), REG1
  1695. * or REG2, %lo(SYMBOL), REG2
  1696. * sllx REG1, 32, REG1
  1697. * or REG1, REG2, REG1
  1698. *
  1699. * When we use physical addressing for the TSB accesses, we patch the
  1700. * first four instructions in the above sequence.
  1701. */
  1702. static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
  1703. {
  1704. unsigned long high_bits, low_bits;
  1705. high_bits = (pa >> 32) & 0xffffffff;
  1706. low_bits = (pa >> 0) & 0xffffffff;
  1707. while (start < end) {
  1708. unsigned int *ia = (unsigned int *)(unsigned long)*start;
  1709. ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
  1710. __asm__ __volatile__("flush %0" : : "r" (ia));
  1711. ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
  1712. __asm__ __volatile__("flush %0" : : "r" (ia + 1));
  1713. ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
  1714. __asm__ __volatile__("flush %0" : : "r" (ia + 2));
  1715. ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
  1716. __asm__ __volatile__("flush %0" : : "r" (ia + 3));
  1717. start++;
  1718. }
  1719. }
  1720. static void ktsb_phys_patch(void)
  1721. {
  1722. extern unsigned int __swapper_tsb_phys_patch;
  1723. extern unsigned int __swapper_tsb_phys_patch_end;
  1724. unsigned long ktsb_pa;
  1725. ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
  1726. patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
  1727. &__swapper_tsb_phys_patch_end, ktsb_pa);
  1728. #ifndef CONFIG_DEBUG_PAGEALLOC
  1729. {
  1730. extern unsigned int __swapper_4m_tsb_phys_patch;
  1731. extern unsigned int __swapper_4m_tsb_phys_patch_end;
  1732. ktsb_pa = (kern_base +
  1733. ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
  1734. patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
  1735. &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
  1736. }
  1737. #endif
  1738. }
  1739. static void __init sun4v_ktsb_init(void)
  1740. {
  1741. unsigned long ktsb_pa;
  1742. /* First KTSB for PAGE_SIZE mappings. */
  1743. ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
  1744. switch (PAGE_SIZE) {
  1745. case 8 * 1024:
  1746. default:
  1747. ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
  1748. ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
  1749. break;
  1750. case 64 * 1024:
  1751. ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
  1752. ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
  1753. break;
  1754. case 512 * 1024:
  1755. ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
  1756. ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
  1757. break;
  1758. case 4 * 1024 * 1024:
  1759. ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
  1760. ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
  1761. break;
  1762. }
  1763. ktsb_descr[0].assoc = 1;
  1764. ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
  1765. ktsb_descr[0].ctx_idx = 0;
  1766. ktsb_descr[0].tsb_base = ktsb_pa;
  1767. ktsb_descr[0].resv = 0;
  1768. #ifndef CONFIG_DEBUG_PAGEALLOC
  1769. /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
  1770. ktsb_pa = (kern_base +
  1771. ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
  1772. ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
  1773. ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
  1774. HV_PGSZ_MASK_256MB |
  1775. HV_PGSZ_MASK_2GB |
  1776. HV_PGSZ_MASK_16GB) &
  1777. cpu_pgsz_mask);
  1778. ktsb_descr[1].assoc = 1;
  1779. ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
  1780. ktsb_descr[1].ctx_idx = 0;
  1781. ktsb_descr[1].tsb_base = ktsb_pa;
  1782. ktsb_descr[1].resv = 0;
  1783. #endif
  1784. }
  1785. void sun4v_ktsb_register(void)
  1786. {
  1787. unsigned long pa, ret;
  1788. pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
  1789. ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
  1790. if (ret != 0) {
  1791. prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
  1792. "errors with %lx\n", pa, ret);
  1793. prom_halt();
  1794. }
  1795. }
  1796. static void __init sun4u_linear_pte_xor_finalize(void)
  1797. {
  1798. #ifndef CONFIG_DEBUG_PAGEALLOC
  1799. /* This is where we would add Panther support for
  1800. * 32MB and 256MB pages.
  1801. */
  1802. #endif
  1803. }
  1804. static void __init sun4v_linear_pte_xor_finalize(void)
  1805. {
  1806. unsigned long pagecv_flag;
  1807. /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
  1808. * enables MCD error. Do not set bit 9 on M7 processor.
  1809. */
  1810. switch (sun4v_chip_type) {
  1811. case SUN4V_CHIP_SPARC_M7:
  1812. case SUN4V_CHIP_SPARC_M8:
  1813. case SUN4V_CHIP_SPARC_SN:
  1814. pagecv_flag = 0x00;
  1815. break;
  1816. default:
  1817. pagecv_flag = _PAGE_CV_4V;
  1818. break;
  1819. }
  1820. #ifndef CONFIG_DEBUG_PAGEALLOC
  1821. if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
  1822. kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
  1823. PAGE_OFFSET;
  1824. kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
  1825. _PAGE_P_4V | _PAGE_W_4V);
  1826. } else {
  1827. kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
  1828. }
  1829. if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
  1830. kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
  1831. PAGE_OFFSET;
  1832. kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
  1833. _PAGE_P_4V | _PAGE_W_4V);
  1834. } else {
  1835. kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
  1836. }
  1837. if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
  1838. kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
  1839. PAGE_OFFSET;
  1840. kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
  1841. _PAGE_P_4V | _PAGE_W_4V);
  1842. } else {
  1843. kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
  1844. }
  1845. #endif
  1846. }
  1847. /* paging_init() sets up the page tables */
  1848. static unsigned long last_valid_pfn;
  1849. static void sun4u_pgprot_init(void);
  1850. static void sun4v_pgprot_init(void);
  1851. #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
  1852. #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
  1853. #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
  1854. #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
  1855. #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
  1856. #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
  1857. /* We need to exclude reserved regions. This exclusion will include
  1858. * vmlinux and initrd. To be more precise the initrd size could be used to
  1859. * compute a new lower limit because it is freed later during initialization.
  1860. */
  1861. static void __init reduce_memory(phys_addr_t limit_ram)
  1862. {
  1863. limit_ram += memblock_reserved_size();
  1864. memblock_enforce_memory_limit(limit_ram);
  1865. }
  1866. void __init paging_init(void)
  1867. {
  1868. unsigned long end_pfn, shift, phys_base;
  1869. unsigned long real_end, i;
  1870. setup_page_offset();
  1871. /* These build time checkes make sure that the dcache_dirty_cpu()
  1872. * page->flags usage will work.
  1873. *
  1874. * When a page gets marked as dcache-dirty, we store the
  1875. * cpu number starting at bit 32 in the page->flags. Also,
  1876. * functions like clear_dcache_dirty_cpu use the cpu mask
  1877. * in 13-bit signed-immediate instruction fields.
  1878. */
  1879. /*
  1880. * Page flags must not reach into upper 32 bits that are used
  1881. * for the cpu number
  1882. */
  1883. BUILD_BUG_ON(NR_PAGEFLAGS > 32);
  1884. /*
  1885. * The bit fields placed in the high range must not reach below
  1886. * the 32 bit boundary. Otherwise we cannot place the cpu field
  1887. * at the 32 bit boundary.
  1888. */
  1889. BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
  1890. ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
  1891. BUILD_BUG_ON(NR_CPUS > 4096);
  1892. kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
  1893. kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
  1894. /* Invalidate both kernel TSBs. */
  1895. memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
  1896. #ifndef CONFIG_DEBUG_PAGEALLOC
  1897. memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
  1898. #endif
  1899. /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
  1900. * bit on M7 processor. This is a conflicting usage of the same
  1901. * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
  1902. * Detection error on all pages and this will lead to problems
  1903. * later. Kernel does not run with MCD enabled and hence rest
  1904. * of the required steps to fully configure memory corruption
  1905. * detection are not taken. We need to ensure TTE.mcde is not
  1906. * set on M7 processor. Compute the value of cacheability
  1907. * flag for use later taking this into consideration.
  1908. */
  1909. switch (sun4v_chip_type) {
  1910. case SUN4V_CHIP_SPARC_M7:
  1911. case SUN4V_CHIP_SPARC_M8:
  1912. case SUN4V_CHIP_SPARC_SN:
  1913. page_cache4v_flag = _PAGE_CP_4V;
  1914. break;
  1915. default:
  1916. page_cache4v_flag = _PAGE_CACHE_4V;
  1917. break;
  1918. }
  1919. if (tlb_type == hypervisor)
  1920. sun4v_pgprot_init();
  1921. else
  1922. sun4u_pgprot_init();
  1923. if (tlb_type == cheetah_plus ||
  1924. tlb_type == hypervisor) {
  1925. tsb_phys_patch();
  1926. ktsb_phys_patch();
  1927. }
  1928. if (tlb_type == hypervisor)
  1929. sun4v_patch_tlb_handlers();
  1930. /* Find available physical memory...
  1931. *
  1932. * Read it twice in order to work around a bug in openfirmware.
  1933. * The call to grab this table itself can cause openfirmware to
  1934. * allocate memory, which in turn can take away some space from
  1935. * the list of available memory. Reading it twice makes sure
  1936. * we really do get the final value.
  1937. */
  1938. read_obp_translations();
  1939. read_obp_memory("reg", &pall[0], &pall_ents);
  1940. read_obp_memory("available", &pavail[0], &pavail_ents);
  1941. read_obp_memory("available", &pavail[0], &pavail_ents);
  1942. phys_base = 0xffffffffffffffffUL;
  1943. for (i = 0; i < pavail_ents; i++) {
  1944. phys_base = min(phys_base, pavail[i].phys_addr);
  1945. memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
  1946. }
  1947. memblock_reserve(kern_base, kern_size);
  1948. find_ramdisk(phys_base);
  1949. if (cmdline_memory_size)
  1950. reduce_memory(cmdline_memory_size);
  1951. memblock_allow_resize();
  1952. memblock_dump_all();
  1953. set_bit(0, mmu_context_bmap);
  1954. shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
  1955. real_end = (unsigned long)_end;
  1956. num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
  1957. printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
  1958. num_kernel_image_mappings);
  1959. /* Set kernel pgd to upper alias so physical page computations
  1960. * work.
  1961. */
  1962. init_mm.pgd += ((shift) / (sizeof(pgd_t)));
  1963. memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
  1964. inherit_prom_mappings();
  1965. /* Ok, we can use our TLB miss and window trap handlers safely. */
  1966. setup_tba();
  1967. __flush_tlb_all();
  1968. prom_build_devicetree();
  1969. of_populate_present_mask();
  1970. #ifndef CONFIG_SMP
  1971. of_fill_in_cpu_data();
  1972. #endif
  1973. if (tlb_type == hypervisor) {
  1974. sun4v_mdesc_init();
  1975. mdesc_populate_present_mask(cpu_all_mask);
  1976. #ifndef CONFIG_SMP
  1977. mdesc_fill_in_cpu_data(cpu_all_mask);
  1978. #endif
  1979. mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
  1980. sun4v_linear_pte_xor_finalize();
  1981. sun4v_ktsb_init();
  1982. sun4v_ktsb_register();
  1983. } else {
  1984. unsigned long impl, ver;
  1985. cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
  1986. HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
  1987. __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
  1988. impl = ((ver >> 32) & 0xffff);
  1989. if (impl == PANTHER_IMPL)
  1990. cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
  1991. HV_PGSZ_MASK_256MB);
  1992. sun4u_linear_pte_xor_finalize();
  1993. }
  1994. /* Flush the TLBs and the 4M TSB so that the updated linear
  1995. * pte XOR settings are realized for all mappings.
  1996. */
  1997. __flush_tlb_all();
  1998. #ifndef CONFIG_DEBUG_PAGEALLOC
  1999. memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
  2000. #endif
  2001. __flush_tlb_all();
  2002. /* Setup bootmem... */
  2003. last_valid_pfn = end_pfn = bootmem_init(phys_base);
  2004. kernel_physical_mapping_init();
  2005. {
  2006. unsigned long max_zone_pfns[MAX_NR_ZONES];
  2007. memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
  2008. max_zone_pfns[ZONE_NORMAL] = end_pfn;
  2009. free_area_init(max_zone_pfns);
  2010. }
  2011. printk("Booting Linux...\n");
  2012. }
  2013. int page_in_phys_avail(unsigned long paddr)
  2014. {
  2015. int i;
  2016. paddr &= PAGE_MASK;
  2017. for (i = 0; i < pavail_ents; i++) {
  2018. unsigned long start, end;
  2019. start = pavail[i].phys_addr;
  2020. end = start + pavail[i].reg_size;
  2021. if (paddr >= start && paddr < end)
  2022. return 1;
  2023. }
  2024. if (paddr >= kern_base && paddr < (kern_base + kern_size))
  2025. return 1;
  2026. #ifdef CONFIG_BLK_DEV_INITRD
  2027. if (paddr >= __pa(initrd_start) &&
  2028. paddr < __pa(PAGE_ALIGN(initrd_end)))
  2029. return 1;
  2030. #endif
  2031. return 0;
  2032. }
  2033. static void __init register_page_bootmem_info(void)
  2034. {
  2035. #ifdef CONFIG_NEED_MULTIPLE_NODES
  2036. int i;
  2037. for_each_online_node(i)
  2038. if (NODE_DATA(i)->node_spanned_pages)
  2039. register_page_bootmem_info_node(NODE_DATA(i));
  2040. #endif
  2041. }
  2042. void __init mem_init(void)
  2043. {
  2044. high_memory = __va(last_valid_pfn << PAGE_SHIFT);
  2045. memblock_free_all();
  2046. /*
  2047. * Must be done after boot memory is put on freelist, because here we
  2048. * might set fields in deferred struct pages that have not yet been
  2049. * initialized, and memblock_free_all() initializes all the reserved
  2050. * deferred pages for us.
  2051. */
  2052. register_page_bootmem_info();
  2053. /*
  2054. * Set up the zero page, mark it reserved, so that page count
  2055. * is not manipulated when freeing the page from user ptes.
  2056. */
  2057. mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
  2058. if (mem_map_zero == NULL) {
  2059. prom_printf("paging_init: Cannot alloc zero page.\n");
  2060. prom_halt();
  2061. }
  2062. mark_page_reserved(mem_map_zero);
  2063. mem_init_print_info(NULL);
  2064. if (tlb_type == cheetah || tlb_type == cheetah_plus)
  2065. cheetah_ecache_flush_init();
  2066. }
  2067. void free_initmem(void)
  2068. {
  2069. unsigned long addr, initend;
  2070. int do_free = 1;
  2071. /* If the physical memory maps were trimmed by kernel command
  2072. * line options, don't even try freeing this initmem stuff up.
  2073. * The kernel image could have been in the trimmed out region
  2074. * and if so the freeing below will free invalid page structs.
  2075. */
  2076. if (cmdline_memory_size)
  2077. do_free = 0;
  2078. /*
  2079. * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
  2080. */
  2081. addr = PAGE_ALIGN((unsigned long)(__init_begin));
  2082. initend = (unsigned long)(__init_end) & PAGE_MASK;
  2083. for (; addr < initend; addr += PAGE_SIZE) {
  2084. unsigned long page;
  2085. page = (addr +
  2086. ((unsigned long) __va(kern_base)) -
  2087. ((unsigned long) KERNBASE));
  2088. memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
  2089. if (do_free)
  2090. free_reserved_page(virt_to_page(page));
  2091. }
  2092. }
  2093. pgprot_t PAGE_KERNEL __read_mostly;
  2094. EXPORT_SYMBOL(PAGE_KERNEL);
  2095. pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
  2096. pgprot_t PAGE_COPY __read_mostly;
  2097. pgprot_t PAGE_SHARED __read_mostly;
  2098. EXPORT_SYMBOL(PAGE_SHARED);
  2099. unsigned long pg_iobits __read_mostly;
  2100. unsigned long _PAGE_IE __read_mostly;
  2101. EXPORT_SYMBOL(_PAGE_IE);
  2102. unsigned long _PAGE_E __read_mostly;
  2103. EXPORT_SYMBOL(_PAGE_E);
  2104. unsigned long _PAGE_CACHE __read_mostly;
  2105. EXPORT_SYMBOL(_PAGE_CACHE);
  2106. #ifdef CONFIG_SPARSEMEM_VMEMMAP
  2107. int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
  2108. int node, struct vmem_altmap *altmap)
  2109. {
  2110. unsigned long pte_base;
  2111. pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
  2112. _PAGE_CP_4U | _PAGE_CV_4U |
  2113. _PAGE_P_4U | _PAGE_W_4U);
  2114. if (tlb_type == hypervisor)
  2115. pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
  2116. page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
  2117. pte_base |= _PAGE_PMD_HUGE;
  2118. vstart = vstart & PMD_MASK;
  2119. vend = ALIGN(vend, PMD_SIZE);
  2120. for (; vstart < vend; vstart += PMD_SIZE) {
  2121. pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
  2122. unsigned long pte;
  2123. p4d_t *p4d;
  2124. pud_t *pud;
  2125. pmd_t *pmd;
  2126. if (!pgd)
  2127. return -ENOMEM;
  2128. p4d = vmemmap_p4d_populate(pgd, vstart, node);
  2129. if (!p4d)
  2130. return -ENOMEM;
  2131. pud = vmemmap_pud_populate(p4d, vstart, node);
  2132. if (!pud)
  2133. return -ENOMEM;
  2134. pmd = pmd_offset(pud, vstart);
  2135. pte = pmd_val(*pmd);
  2136. if (!(pte & _PAGE_VALID)) {
  2137. void *block = vmemmap_alloc_block(PMD_SIZE, node);
  2138. if (!block)
  2139. return -ENOMEM;
  2140. pmd_val(*pmd) = pte_base | __pa(block);
  2141. }
  2142. }
  2143. return 0;
  2144. }
  2145. void vmemmap_free(unsigned long start, unsigned long end,
  2146. struct vmem_altmap *altmap)
  2147. {
  2148. }
  2149. #endif /* CONFIG_SPARSEMEM_VMEMMAP */
  2150. static void prot_init_common(unsigned long page_none,
  2151. unsigned long page_shared,
  2152. unsigned long page_copy,
  2153. unsigned long page_readonly,
  2154. unsigned long page_exec_bit)
  2155. {
  2156. PAGE_COPY = __pgprot(page_copy);
  2157. PAGE_SHARED = __pgprot(page_shared);
  2158. protection_map[0x0] = __pgprot(page_none);
  2159. protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
  2160. protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
  2161. protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
  2162. protection_map[0x4] = __pgprot(page_readonly);
  2163. protection_map[0x5] = __pgprot(page_readonly);
  2164. protection_map[0x6] = __pgprot(page_copy);
  2165. protection_map[0x7] = __pgprot(page_copy);
  2166. protection_map[0x8] = __pgprot(page_none);
  2167. protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
  2168. protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
  2169. protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
  2170. protection_map[0xc] = __pgprot(page_readonly);
  2171. protection_map[0xd] = __pgprot(page_readonly);
  2172. protection_map[0xe] = __pgprot(page_shared);
  2173. protection_map[0xf] = __pgprot(page_shared);
  2174. }
  2175. static void __init sun4u_pgprot_init(void)
  2176. {
  2177. unsigned long page_none, page_shared, page_copy, page_readonly;
  2178. unsigned long page_exec_bit;
  2179. int i;
  2180. PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
  2181. _PAGE_CACHE_4U | _PAGE_P_4U |
  2182. __ACCESS_BITS_4U | __DIRTY_BITS_4U |
  2183. _PAGE_EXEC_4U);
  2184. PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
  2185. _PAGE_CACHE_4U | _PAGE_P_4U |
  2186. __ACCESS_BITS_4U | __DIRTY_BITS_4U |
  2187. _PAGE_EXEC_4U | _PAGE_L_4U);
  2188. _PAGE_IE = _PAGE_IE_4U;
  2189. _PAGE_E = _PAGE_E_4U;
  2190. _PAGE_CACHE = _PAGE_CACHE_4U;
  2191. pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
  2192. __ACCESS_BITS_4U | _PAGE_E_4U);
  2193. #ifdef CONFIG_DEBUG_PAGEALLOC
  2194. kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
  2195. #else
  2196. kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
  2197. PAGE_OFFSET;
  2198. #endif
  2199. kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
  2200. _PAGE_P_4U | _PAGE_W_4U);
  2201. for (i = 1; i < 4; i++)
  2202. kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
  2203. _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
  2204. _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
  2205. _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
  2206. page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
  2207. page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
  2208. __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
  2209. page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
  2210. __ACCESS_BITS_4U | _PAGE_EXEC_4U);
  2211. page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
  2212. __ACCESS_BITS_4U | _PAGE_EXEC_4U);
  2213. page_exec_bit = _PAGE_EXEC_4U;
  2214. prot_init_common(page_none, page_shared, page_copy, page_readonly,
  2215. page_exec_bit);
  2216. }
  2217. static void __init sun4v_pgprot_init(void)
  2218. {
  2219. unsigned long page_none, page_shared, page_copy, page_readonly;
  2220. unsigned long page_exec_bit;
  2221. int i;
  2222. PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
  2223. page_cache4v_flag | _PAGE_P_4V |
  2224. __ACCESS_BITS_4V | __DIRTY_BITS_4V |
  2225. _PAGE_EXEC_4V);
  2226. PAGE_KERNEL_LOCKED = PAGE_KERNEL;
  2227. _PAGE_IE = _PAGE_IE_4V;
  2228. _PAGE_E = _PAGE_E_4V;
  2229. _PAGE_CACHE = page_cache4v_flag;
  2230. #ifdef CONFIG_DEBUG_PAGEALLOC
  2231. kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
  2232. #else
  2233. kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
  2234. PAGE_OFFSET;
  2235. #endif
  2236. kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
  2237. _PAGE_W_4V);
  2238. for (i = 1; i < 4; i++)
  2239. kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
  2240. pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
  2241. __ACCESS_BITS_4V | _PAGE_E_4V);
  2242. _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
  2243. _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
  2244. _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
  2245. _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
  2246. page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
  2247. page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
  2248. __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
  2249. page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
  2250. __ACCESS_BITS_4V | _PAGE_EXEC_4V);
  2251. page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
  2252. __ACCESS_BITS_4V | _PAGE_EXEC_4V);
  2253. page_exec_bit = _PAGE_EXEC_4V;
  2254. prot_init_common(page_none, page_shared, page_copy, page_readonly,
  2255. page_exec_bit);
  2256. }
  2257. unsigned long pte_sz_bits(unsigned long sz)
  2258. {
  2259. if (tlb_type == hypervisor) {
  2260. switch (sz) {
  2261. case 8 * 1024:
  2262. default:
  2263. return _PAGE_SZ8K_4V;
  2264. case 64 * 1024:
  2265. return _PAGE_SZ64K_4V;
  2266. case 512 * 1024:
  2267. return _PAGE_SZ512K_4V;
  2268. case 4 * 1024 * 1024:
  2269. return _PAGE_SZ4MB_4V;
  2270. }
  2271. } else {
  2272. switch (sz) {
  2273. case 8 * 1024:
  2274. default:
  2275. return _PAGE_SZ8K_4U;
  2276. case 64 * 1024:
  2277. return _PAGE_SZ64K_4U;
  2278. case 512 * 1024:
  2279. return _PAGE_SZ512K_4U;
  2280. case 4 * 1024 * 1024:
  2281. return _PAGE_SZ4MB_4U;
  2282. }
  2283. }
  2284. }
  2285. pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
  2286. {
  2287. pte_t pte;
  2288. pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
  2289. pte_val(pte) |= (((unsigned long)space) << 32);
  2290. pte_val(pte) |= pte_sz_bits(page_size);
  2291. return pte;
  2292. }
  2293. static unsigned long kern_large_tte(unsigned long paddr)
  2294. {
  2295. unsigned long val;
  2296. val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
  2297. _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
  2298. _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
  2299. if (tlb_type == hypervisor)
  2300. val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
  2301. page_cache4v_flag | _PAGE_P_4V |
  2302. _PAGE_EXEC_4V | _PAGE_W_4V);
  2303. return val | paddr;
  2304. }
  2305. /* If not locked, zap it. */
  2306. void __flush_tlb_all(void)
  2307. {
  2308. unsigned long pstate;
  2309. int i;
  2310. __asm__ __volatile__("flushw\n\t"
  2311. "rdpr %%pstate, %0\n\t"
  2312. "wrpr %0, %1, %%pstate"
  2313. : "=r" (pstate)
  2314. : "i" (PSTATE_IE));
  2315. if (tlb_type == hypervisor) {
  2316. sun4v_mmu_demap_all();
  2317. } else if (tlb_type == spitfire) {
  2318. for (i = 0; i < 64; i++) {
  2319. /* Spitfire Errata #32 workaround */
  2320. /* NOTE: Always runs on spitfire, so no
  2321. * cheetah+ page size encodings.
  2322. */
  2323. __asm__ __volatile__("stxa %0, [%1] %2\n\t"
  2324. "flush %%g6"
  2325. : /* No outputs */
  2326. : "r" (0),
  2327. "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
  2328. if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
  2329. __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
  2330. "membar #Sync"
  2331. : /* no outputs */
  2332. : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
  2333. spitfire_put_dtlb_data(i, 0x0UL);
  2334. }
  2335. /* Spitfire Errata #32 workaround */
  2336. /* NOTE: Always runs on spitfire, so no
  2337. * cheetah+ page size encodings.
  2338. */
  2339. __asm__ __volatile__("stxa %0, [%1] %2\n\t"
  2340. "flush %%g6"
  2341. : /* No outputs */
  2342. : "r" (0),
  2343. "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
  2344. if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
  2345. __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
  2346. "membar #Sync"
  2347. : /* no outputs */
  2348. : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
  2349. spitfire_put_itlb_data(i, 0x0UL);
  2350. }
  2351. }
  2352. } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
  2353. cheetah_flush_dtlb_all();
  2354. cheetah_flush_itlb_all();
  2355. }
  2356. __asm__ __volatile__("wrpr %0, 0, %%pstate"
  2357. : : "r" (pstate));
  2358. }
  2359. pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
  2360. {
  2361. struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
  2362. pte_t *pte = NULL;
  2363. if (page)
  2364. pte = (pte_t *) page_address(page);
  2365. return pte;
  2366. }
  2367. pgtable_t pte_alloc_one(struct mm_struct *mm)
  2368. {
  2369. struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
  2370. if (!page)
  2371. return NULL;
  2372. if (!pgtable_pte_page_ctor(page)) {
  2373. __free_page(page);
  2374. return NULL;
  2375. }
  2376. return (pte_t *) page_address(page);
  2377. }
  2378. void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
  2379. {
  2380. free_page((unsigned long)pte);
  2381. }
  2382. static void __pte_free(pgtable_t pte)
  2383. {
  2384. struct page *page = virt_to_page(pte);
  2385. pgtable_pte_page_dtor(page);
  2386. __free_page(page);
  2387. }
  2388. void pte_free(struct mm_struct *mm, pgtable_t pte)
  2389. {
  2390. __pte_free(pte);
  2391. }
  2392. void pgtable_free(void *table, bool is_page)
  2393. {
  2394. if (is_page)
  2395. __pte_free(table);
  2396. else
  2397. kmem_cache_free(pgtable_cache, table);
  2398. }
  2399. #ifdef CONFIG_TRANSPARENT_HUGEPAGE
  2400. void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
  2401. pmd_t *pmd)
  2402. {
  2403. unsigned long pte, flags;
  2404. struct mm_struct *mm;
  2405. pmd_t entry = *pmd;
  2406. if (!pmd_large(entry) || !pmd_young(entry))
  2407. return;
  2408. pte = pmd_val(entry);
  2409. /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
  2410. if (!(pte & _PAGE_VALID))
  2411. return;
  2412. /* We are fabricating 8MB pages using 4MB real hw pages. */
  2413. pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
  2414. mm = vma->vm_mm;
  2415. spin_lock_irqsave(&mm->context.lock, flags);
  2416. if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
  2417. __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
  2418. addr, pte);
  2419. spin_unlock_irqrestore(&mm->context.lock, flags);
  2420. }
  2421. #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
  2422. #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
  2423. static void context_reload(void *__data)
  2424. {
  2425. struct mm_struct *mm = __data;
  2426. if (mm == current->mm)
  2427. load_secondary_context(mm);
  2428. }
  2429. void hugetlb_setup(struct pt_regs *regs)
  2430. {
  2431. struct mm_struct *mm = current->mm;
  2432. struct tsb_config *tp;
  2433. if (faulthandler_disabled() || !mm) {
  2434. const struct exception_table_entry *entry;
  2435. entry = search_exception_tables(regs->tpc);
  2436. if (entry) {
  2437. regs->tpc = entry->fixup;
  2438. regs->tnpc = regs->tpc + 4;
  2439. return;
  2440. }
  2441. pr_alert("Unexpected HugeTLB setup in atomic context.\n");
  2442. die_if_kernel("HugeTSB in atomic", regs);
  2443. }
  2444. tp = &mm->context.tsb_block[MM_TSB_HUGE];
  2445. if (likely(tp->tsb == NULL))
  2446. tsb_grow(mm, MM_TSB_HUGE, 0);
  2447. tsb_context_switch(mm);
  2448. smp_tsb_sync(mm);
  2449. /* On UltraSPARC-III+ and later, configure the second half of
  2450. * the Data-TLB for huge pages.
  2451. */
  2452. if (tlb_type == cheetah_plus) {
  2453. bool need_context_reload = false;
  2454. unsigned long ctx;
  2455. spin_lock_irq(&ctx_alloc_lock);
  2456. ctx = mm->context.sparc64_ctx_val;
  2457. ctx &= ~CTX_PGSZ_MASK;
  2458. ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
  2459. ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
  2460. if (ctx != mm->context.sparc64_ctx_val) {
  2461. /* When changing the page size fields, we
  2462. * must perform a context flush so that no
  2463. * stale entries match. This flush must
  2464. * occur with the original context register
  2465. * settings.
  2466. */
  2467. do_flush_tlb_mm(mm);
  2468. /* Reload the context register of all processors
  2469. * also executing in this address space.
  2470. */
  2471. mm->context.sparc64_ctx_val = ctx;
  2472. need_context_reload = true;
  2473. }
  2474. spin_unlock_irq(&ctx_alloc_lock);
  2475. if (need_context_reload)
  2476. on_each_cpu(context_reload, mm, 0);
  2477. }
  2478. }
  2479. #endif
  2480. static struct resource code_resource = {
  2481. .name = "Kernel code",
  2482. .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
  2483. };
  2484. static struct resource data_resource = {
  2485. .name = "Kernel data",
  2486. .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
  2487. };
  2488. static struct resource bss_resource = {
  2489. .name = "Kernel bss",
  2490. .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
  2491. };
  2492. static inline resource_size_t compute_kern_paddr(void *addr)
  2493. {
  2494. return (resource_size_t) (addr - KERNBASE + kern_base);
  2495. }
  2496. static void __init kernel_lds_init(void)
  2497. {
  2498. code_resource.start = compute_kern_paddr(_text);
  2499. code_resource.end = compute_kern_paddr(_etext - 1);
  2500. data_resource.start = compute_kern_paddr(_etext);
  2501. data_resource.end = compute_kern_paddr(_edata - 1);
  2502. bss_resource.start = compute_kern_paddr(__bss_start);
  2503. bss_resource.end = compute_kern_paddr(_end - 1);
  2504. }
  2505. static int __init report_memory(void)
  2506. {
  2507. int i;
  2508. struct resource *res;
  2509. kernel_lds_init();
  2510. for (i = 0; i < pavail_ents; i++) {
  2511. res = kzalloc(sizeof(struct resource), GFP_KERNEL);
  2512. if (!res) {
  2513. pr_warn("Failed to allocate source.\n");
  2514. break;
  2515. }
  2516. res->name = "System RAM";
  2517. res->start = pavail[i].phys_addr;
  2518. res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
  2519. res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
  2520. if (insert_resource(&iomem_resource, res) < 0) {
  2521. pr_warn("Resource insertion failed.\n");
  2522. break;
  2523. }
  2524. insert_resource(res, &code_resource);
  2525. insert_resource(res, &data_resource);
  2526. insert_resource(res, &bss_resource);
  2527. }
  2528. return 0;
  2529. }
  2530. arch_initcall(report_memory);
  2531. #ifdef CONFIG_SMP
  2532. #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
  2533. #else
  2534. #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
  2535. #endif
  2536. void flush_tlb_kernel_range(unsigned long start, unsigned long end)
  2537. {
  2538. if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
  2539. if (start < LOW_OBP_ADDRESS) {
  2540. flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
  2541. do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
  2542. }
  2543. if (end > HI_OBP_ADDRESS) {
  2544. flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
  2545. do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
  2546. }
  2547. } else {
  2548. flush_tsb_kernel_range(start, end);
  2549. do_flush_tlb_kernel_range(start, end);
  2550. }
  2551. }
  2552. void copy_user_highpage(struct page *to, struct page *from,
  2553. unsigned long vaddr, struct vm_area_struct *vma)
  2554. {
  2555. char *vfrom, *vto;
  2556. vfrom = kmap_atomic(from);
  2557. vto = kmap_atomic(to);
  2558. copy_user_page(vto, vfrom, vaddr, to);
  2559. kunmap_atomic(vto);
  2560. kunmap_atomic(vfrom);
  2561. /* If this page has ADI enabled, copy over any ADI tags
  2562. * as well
  2563. */
  2564. if (vma->vm_flags & VM_SPARC_ADI) {
  2565. unsigned long pfrom, pto, i, adi_tag;
  2566. pfrom = page_to_phys(from);
  2567. pto = page_to_phys(to);
  2568. for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
  2569. asm volatile("ldxa [%1] %2, %0\n\t"
  2570. : "=r" (adi_tag)
  2571. : "r" (i), "i" (ASI_MCD_REAL));
  2572. asm volatile("stxa %0, [%1] %2\n\t"
  2573. :
  2574. : "r" (adi_tag), "r" (pto),
  2575. "i" (ASI_MCD_REAL));
  2576. pto += adi_blksize();
  2577. }
  2578. asm volatile("membar #Sync\n\t");
  2579. }
  2580. }
  2581. EXPORT_SYMBOL(copy_user_highpage);
  2582. void copy_highpage(struct page *to, struct page *from)
  2583. {
  2584. char *vfrom, *vto;
  2585. vfrom = kmap_atomic(from);
  2586. vto = kmap_atomic(to);
  2587. copy_page(vto, vfrom);
  2588. kunmap_atomic(vto);
  2589. kunmap_atomic(vfrom);
  2590. /* If this platform is ADI enabled, copy any ADI tags
  2591. * as well
  2592. */
  2593. if (adi_capable()) {
  2594. unsigned long pfrom, pto, i, adi_tag;
  2595. pfrom = page_to_phys(from);
  2596. pto = page_to_phys(to);
  2597. for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
  2598. asm volatile("ldxa [%1] %2, %0\n\t"
  2599. : "=r" (adi_tag)
  2600. : "r" (i), "i" (ASI_MCD_REAL));
  2601. asm volatile("stxa %0, [%1] %2\n\t"
  2602. :
  2603. : "r" (adi_tag), "r" (pto),
  2604. "i" (ASI_MCD_REAL));
  2605. pto += adi_blksize();
  2606. }
  2607. asm volatile("membar #Sync\n\t");
  2608. }
  2609. }
  2610. EXPORT_SYMBOL(copy_highpage);