hypersparc.S 9.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * hypersparc.S: High speed Hypersparc mmu/cache operations.
  4. *
  5. * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
  6. */
  7. #include <asm/ptrace.h>
  8. #include <asm/psr.h>
  9. #include <asm/asm-offsets.h>
  10. #include <asm/asi.h>
  11. #include <asm/page.h>
  12. #include <asm/pgtable.h>
  13. #include <asm/pgtsrmmu.h>
  14. #include <linux/init.h>
  15. .text
  16. .align 4
  17. .globl hypersparc_flush_cache_all, hypersparc_flush_cache_mm
  18. .globl hypersparc_flush_cache_range, hypersparc_flush_cache_page
  19. .globl hypersparc_flush_page_to_ram
  20. .globl hypersparc_flush_page_for_dma, hypersparc_flush_sig_insns
  21. .globl hypersparc_flush_tlb_all, hypersparc_flush_tlb_mm
  22. .globl hypersparc_flush_tlb_range, hypersparc_flush_tlb_page
  23. hypersparc_flush_cache_all:
  24. WINDOW_FLUSH(%g4, %g5)
  25. sethi %hi(vac_cache_size), %g4
  26. ld [%g4 + %lo(vac_cache_size)], %g5
  27. sethi %hi(vac_line_size), %g1
  28. ld [%g1 + %lo(vac_line_size)], %g2
  29. 1:
  30. subcc %g5, %g2, %g5 ! hyper_flush_unconditional_combined
  31. bne 1b
  32. sta %g0, [%g5] ASI_M_FLUSH_CTX
  33. retl
  34. sta %g0, [%g0] ASI_M_FLUSH_IWHOLE ! hyper_flush_whole_icache
  35. /* We expand the window flush to get maximum performance. */
  36. hypersparc_flush_cache_mm:
  37. #ifndef CONFIG_SMP
  38. ld [%o0 + AOFF_mm_context], %g1
  39. cmp %g1, -1
  40. be hypersparc_flush_cache_mm_out
  41. #endif
  42. WINDOW_FLUSH(%g4, %g5)
  43. sethi %hi(vac_line_size), %g1
  44. ld [%g1 + %lo(vac_line_size)], %o1
  45. sethi %hi(vac_cache_size), %g2
  46. ld [%g2 + %lo(vac_cache_size)], %o0
  47. add %o1, %o1, %g1
  48. add %o1, %g1, %g2
  49. add %o1, %g2, %g3
  50. add %o1, %g3, %g4
  51. add %o1, %g4, %g5
  52. add %o1, %g5, %o4
  53. add %o1, %o4, %o5
  54. /* BLAMMO! */
  55. 1:
  56. subcc %o0, %o5, %o0 ! hyper_flush_cache_user
  57. sta %g0, [%o0 + %g0] ASI_M_FLUSH_USER
  58. sta %g0, [%o0 + %o1] ASI_M_FLUSH_USER
  59. sta %g0, [%o0 + %g1] ASI_M_FLUSH_USER
  60. sta %g0, [%o0 + %g2] ASI_M_FLUSH_USER
  61. sta %g0, [%o0 + %g3] ASI_M_FLUSH_USER
  62. sta %g0, [%o0 + %g4] ASI_M_FLUSH_USER
  63. sta %g0, [%o0 + %g5] ASI_M_FLUSH_USER
  64. bne 1b
  65. sta %g0, [%o0 + %o4] ASI_M_FLUSH_USER
  66. hypersparc_flush_cache_mm_out:
  67. retl
  68. nop
  69. /* The things we do for performance... */
  70. hypersparc_flush_cache_range:
  71. ld [%o0 + VMA_VM_MM], %o0
  72. #ifndef CONFIG_SMP
  73. ld [%o0 + AOFF_mm_context], %g1
  74. cmp %g1, -1
  75. be hypersparc_flush_cache_range_out
  76. #endif
  77. WINDOW_FLUSH(%g4, %g5)
  78. sethi %hi(vac_line_size), %g1
  79. ld [%g1 + %lo(vac_line_size)], %o4
  80. sethi %hi(vac_cache_size), %g2
  81. ld [%g2 + %lo(vac_cache_size)], %o3
  82. /* Here comes the fun part... */
  83. add %o2, (PAGE_SIZE - 1), %o2
  84. andn %o1, (PAGE_SIZE - 1), %o1
  85. add %o4, %o4, %o5
  86. andn %o2, (PAGE_SIZE - 1), %o2
  87. add %o4, %o5, %g1
  88. sub %o2, %o1, %g4
  89. add %o4, %g1, %g2
  90. sll %o3, 2, %g5
  91. add %o4, %g2, %g3
  92. cmp %g4, %g5
  93. add %o4, %g3, %g4
  94. blu 0f
  95. add %o4, %g4, %g5
  96. add %o4, %g5, %g7
  97. /* Flush entire user space, believe it or not this is quicker
  98. * than page at a time flushings for range > (cache_size<<2).
  99. */
  100. 1:
  101. subcc %o3, %g7, %o3
  102. sta %g0, [%o3 + %g0] ASI_M_FLUSH_USER
  103. sta %g0, [%o3 + %o4] ASI_M_FLUSH_USER
  104. sta %g0, [%o3 + %o5] ASI_M_FLUSH_USER
  105. sta %g0, [%o3 + %g1] ASI_M_FLUSH_USER
  106. sta %g0, [%o3 + %g2] ASI_M_FLUSH_USER
  107. sta %g0, [%o3 + %g3] ASI_M_FLUSH_USER
  108. sta %g0, [%o3 + %g4] ASI_M_FLUSH_USER
  109. bne 1b
  110. sta %g0, [%o3 + %g5] ASI_M_FLUSH_USER
  111. retl
  112. nop
  113. /* Below our threshold, flush one page at a time. */
  114. 0:
  115. ld [%o0 + AOFF_mm_context], %o0
  116. mov SRMMU_CTX_REG, %g7
  117. lda [%g7] ASI_M_MMUREGS, %o3
  118. sta %o0, [%g7] ASI_M_MMUREGS
  119. add %o2, -PAGE_SIZE, %o0
  120. 1:
  121. or %o0, 0x400, %g7
  122. lda [%g7] ASI_M_FLUSH_PROBE, %g7
  123. orcc %g7, 0, %g0
  124. be,a 3f
  125. mov %o0, %o2
  126. add %o4, %g5, %g7
  127. 2:
  128. sub %o2, %g7, %o2
  129. sta %g0, [%o2 + %g0] ASI_M_FLUSH_PAGE
  130. sta %g0, [%o2 + %o4] ASI_M_FLUSH_PAGE
  131. sta %g0, [%o2 + %o5] ASI_M_FLUSH_PAGE
  132. sta %g0, [%o2 + %g1] ASI_M_FLUSH_PAGE
  133. sta %g0, [%o2 + %g2] ASI_M_FLUSH_PAGE
  134. sta %g0, [%o2 + %g3] ASI_M_FLUSH_PAGE
  135. andcc %o2, 0xffc, %g0
  136. sta %g0, [%o2 + %g4] ASI_M_FLUSH_PAGE
  137. bne 2b
  138. sta %g0, [%o2 + %g5] ASI_M_FLUSH_PAGE
  139. 3:
  140. cmp %o2, %o1
  141. bne 1b
  142. add %o2, -PAGE_SIZE, %o0
  143. mov SRMMU_FAULT_STATUS, %g5
  144. lda [%g5] ASI_M_MMUREGS, %g0
  145. mov SRMMU_CTX_REG, %g7
  146. sta %o3, [%g7] ASI_M_MMUREGS
  147. hypersparc_flush_cache_range_out:
  148. retl
  149. nop
  150. /* HyperSparc requires a valid mapping where we are about to flush
  151. * in order to check for a physical tag match during the flush.
  152. */
  153. /* Verified, my ass... */
  154. hypersparc_flush_cache_page:
  155. ld [%o0 + VMA_VM_MM], %o0
  156. ld [%o0 + AOFF_mm_context], %g2
  157. #ifndef CONFIG_SMP
  158. cmp %g2, -1
  159. be hypersparc_flush_cache_page_out
  160. #endif
  161. WINDOW_FLUSH(%g4, %g5)
  162. sethi %hi(vac_line_size), %g1
  163. ld [%g1 + %lo(vac_line_size)], %o4
  164. mov SRMMU_CTX_REG, %o3
  165. andn %o1, (PAGE_SIZE - 1), %o1
  166. lda [%o3] ASI_M_MMUREGS, %o2
  167. sta %g2, [%o3] ASI_M_MMUREGS
  168. or %o1, 0x400, %o5
  169. lda [%o5] ASI_M_FLUSH_PROBE, %g1
  170. orcc %g0, %g1, %g0
  171. be 2f
  172. add %o4, %o4, %o5
  173. sub %o1, -PAGE_SIZE, %o1
  174. add %o4, %o5, %g1
  175. add %o4, %g1, %g2
  176. add %o4, %g2, %g3
  177. add %o4, %g3, %g4
  178. add %o4, %g4, %g5
  179. add %o4, %g5, %g7
  180. /* BLAMMO! */
  181. 1:
  182. sub %o1, %g7, %o1
  183. sta %g0, [%o1 + %g0] ASI_M_FLUSH_PAGE
  184. sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
  185. sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
  186. sta %g0, [%o1 + %g1] ASI_M_FLUSH_PAGE
  187. sta %g0, [%o1 + %g2] ASI_M_FLUSH_PAGE
  188. sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
  189. andcc %o1, 0xffc, %g0
  190. sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
  191. bne 1b
  192. sta %g0, [%o1 + %g5] ASI_M_FLUSH_PAGE
  193. 2:
  194. mov SRMMU_FAULT_STATUS, %g7
  195. mov SRMMU_CTX_REG, %g4
  196. lda [%g7] ASI_M_MMUREGS, %g0
  197. sta %o2, [%g4] ASI_M_MMUREGS
  198. hypersparc_flush_cache_page_out:
  199. retl
  200. nop
  201. hypersparc_flush_sig_insns:
  202. flush %o1
  203. retl
  204. flush %o1 + 4
  205. /* HyperSparc is copy-back. */
  206. hypersparc_flush_page_to_ram:
  207. sethi %hi(vac_line_size), %g1
  208. ld [%g1 + %lo(vac_line_size)], %o4
  209. andn %o0, (PAGE_SIZE - 1), %o0
  210. add %o4, %o4, %o5
  211. or %o0, 0x400, %g7
  212. lda [%g7] ASI_M_FLUSH_PROBE, %g5
  213. add %o4, %o5, %g1
  214. orcc %g5, 0, %g0
  215. be 2f
  216. add %o4, %g1, %g2
  217. add %o4, %g2, %g3
  218. sub %o0, -PAGE_SIZE, %o0
  219. add %o4, %g3, %g4
  220. add %o4, %g4, %g5
  221. add %o4, %g5, %g7
  222. /* BLAMMO! */
  223. 1:
  224. sub %o0, %g7, %o0
  225. sta %g0, [%o0 + %g0] ASI_M_FLUSH_PAGE
  226. sta %g0, [%o0 + %o4] ASI_M_FLUSH_PAGE
  227. sta %g0, [%o0 + %o5] ASI_M_FLUSH_PAGE
  228. sta %g0, [%o0 + %g1] ASI_M_FLUSH_PAGE
  229. sta %g0, [%o0 + %g2] ASI_M_FLUSH_PAGE
  230. sta %g0, [%o0 + %g3] ASI_M_FLUSH_PAGE
  231. andcc %o0, 0xffc, %g0
  232. sta %g0, [%o0 + %g4] ASI_M_FLUSH_PAGE
  233. bne 1b
  234. sta %g0, [%o0 + %g5] ASI_M_FLUSH_PAGE
  235. 2:
  236. mov SRMMU_FAULT_STATUS, %g1
  237. retl
  238. lda [%g1] ASI_M_MMUREGS, %g0
  239. /* HyperSparc is IO cache coherent. */
  240. hypersparc_flush_page_for_dma:
  241. retl
  242. nop
  243. /* It was noted that at boot time a TLB flush all in a delay slot
  244. * can deliver an illegal instruction to the processor if the timing
  245. * is just right...
  246. */
  247. hypersparc_flush_tlb_all:
  248. mov 0x400, %g1
  249. sta %g0, [%g1] ASI_M_FLUSH_PROBE
  250. retl
  251. nop
  252. hypersparc_flush_tlb_mm:
  253. mov SRMMU_CTX_REG, %g1
  254. ld [%o0 + AOFF_mm_context], %o1
  255. lda [%g1] ASI_M_MMUREGS, %g5
  256. #ifndef CONFIG_SMP
  257. cmp %o1, -1
  258. be hypersparc_flush_tlb_mm_out
  259. #endif
  260. mov 0x300, %g2
  261. sta %o1, [%g1] ASI_M_MMUREGS
  262. sta %g0, [%g2] ASI_M_FLUSH_PROBE
  263. hypersparc_flush_tlb_mm_out:
  264. retl
  265. sta %g5, [%g1] ASI_M_MMUREGS
  266. hypersparc_flush_tlb_range:
  267. ld [%o0 + VMA_VM_MM], %o0
  268. mov SRMMU_CTX_REG, %g1
  269. ld [%o0 + AOFF_mm_context], %o3
  270. lda [%g1] ASI_M_MMUREGS, %g5
  271. #ifndef CONFIG_SMP
  272. cmp %o3, -1
  273. be hypersparc_flush_tlb_range_out
  274. #endif
  275. sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
  276. sta %o3, [%g1] ASI_M_MMUREGS
  277. and %o1, %o4, %o1
  278. add %o1, 0x200, %o1
  279. sta %g0, [%o1] ASI_M_FLUSH_PROBE
  280. 1:
  281. sub %o1, %o4, %o1
  282. cmp %o1, %o2
  283. blu,a 1b
  284. sta %g0, [%o1] ASI_M_FLUSH_PROBE
  285. hypersparc_flush_tlb_range_out:
  286. retl
  287. sta %g5, [%g1] ASI_M_MMUREGS
  288. hypersparc_flush_tlb_page:
  289. ld [%o0 + VMA_VM_MM], %o0
  290. mov SRMMU_CTX_REG, %g1
  291. ld [%o0 + AOFF_mm_context], %o3
  292. andn %o1, (PAGE_SIZE - 1), %o1
  293. #ifndef CONFIG_SMP
  294. cmp %o3, -1
  295. be hypersparc_flush_tlb_page_out
  296. #endif
  297. lda [%g1] ASI_M_MMUREGS, %g5
  298. sta %o3, [%g1] ASI_M_MMUREGS
  299. sta %g0, [%o1] ASI_M_FLUSH_PROBE
  300. hypersparc_flush_tlb_page_out:
  301. retl
  302. sta %g5, [%g1] ASI_M_MMUREGS
  303. __INIT
  304. /* High speed page clear/copy. */
  305. hypersparc_bzero_1page:
  306. /* NOTE: This routine has to be shorter than 40insns --jj */
  307. clr %g1
  308. mov 32, %g2
  309. mov 64, %g3
  310. mov 96, %g4
  311. mov 128, %g5
  312. mov 160, %g7
  313. mov 192, %o2
  314. mov 224, %o3
  315. mov 16, %o1
  316. 1:
  317. stda %g0, [%o0 + %g0] ASI_M_BFILL
  318. stda %g0, [%o0 + %g2] ASI_M_BFILL
  319. stda %g0, [%o0 + %g3] ASI_M_BFILL
  320. stda %g0, [%o0 + %g4] ASI_M_BFILL
  321. stda %g0, [%o0 + %g5] ASI_M_BFILL
  322. stda %g0, [%o0 + %g7] ASI_M_BFILL
  323. stda %g0, [%o0 + %o2] ASI_M_BFILL
  324. stda %g0, [%o0 + %o3] ASI_M_BFILL
  325. subcc %o1, 1, %o1
  326. bne 1b
  327. add %o0, 256, %o0
  328. retl
  329. nop
  330. hypersparc_copy_1page:
  331. /* NOTE: This routine has to be shorter than 70insns --jj */
  332. sub %o1, %o0, %o2 ! difference
  333. mov 16, %g1
  334. 1:
  335. sta %o0, [%o0 + %o2] ASI_M_BCOPY
  336. add %o0, 32, %o0
  337. sta %o0, [%o0 + %o2] ASI_M_BCOPY
  338. add %o0, 32, %o0
  339. sta %o0, [%o0 + %o2] ASI_M_BCOPY
  340. add %o0, 32, %o0
  341. sta %o0, [%o0 + %o2] ASI_M_BCOPY
  342. add %o0, 32, %o0
  343. sta %o0, [%o0 + %o2] ASI_M_BCOPY
  344. add %o0, 32, %o0
  345. sta %o0, [%o0 + %o2] ASI_M_BCOPY
  346. add %o0, 32, %o0
  347. sta %o0, [%o0 + %o2] ASI_M_BCOPY
  348. add %o0, 32, %o0
  349. sta %o0, [%o0 + %o2] ASI_M_BCOPY
  350. subcc %g1, 1, %g1
  351. bne 1b
  352. add %o0, 32, %o0
  353. retl
  354. nop
  355. .globl hypersparc_setup_blockops
  356. hypersparc_setup_blockops:
  357. sethi %hi(bzero_1page), %o0
  358. or %o0, %lo(bzero_1page), %o0
  359. sethi %hi(hypersparc_bzero_1page), %o1
  360. or %o1, %lo(hypersparc_bzero_1page), %o1
  361. sethi %hi(hypersparc_copy_1page), %o2
  362. or %o2, %lo(hypersparc_copy_1page), %o2
  363. ld [%o1], %o4
  364. 1:
  365. add %o1, 4, %o1
  366. st %o4, [%o0]
  367. add %o0, 4, %o0
  368. cmp %o1, %o2
  369. bne 1b
  370. ld [%o1], %o4
  371. sethi %hi(__copy_1page), %o0
  372. or %o0, %lo(__copy_1page), %o0
  373. sethi %hi(hypersparc_setup_blockops), %o2
  374. or %o2, %lo(hypersparc_setup_blockops), %o2
  375. ld [%o1], %o4
  376. 1:
  377. add %o1, 4, %o1
  378. st %o4, [%o0]
  379. add %o0, 4, %o0
  380. cmp %o1, %o2
  381. bne 1b
  382. ld [%o1], %o4
  383. sta %g0, [%g0] ASI_M_FLUSH_IWHOLE
  384. retl
  385. nop