math_64.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * arch/sparc64/math-emu/math.c
  4. *
  5. * Copyright (C) 1997,1999 Jakub Jelinek (jj@ultra.linux.cz)
  6. * Copyright (C) 1999 David S. Miller (davem@redhat.com)
  7. *
  8. * Emulation routines originate from soft-fp package, which is part
  9. * of glibc and has appropriate copyrights in it.
  10. */
  11. #include <linux/types.h>
  12. #include <linux/sched.h>
  13. #include <linux/errno.h>
  14. #include <linux/perf_event.h>
  15. #include <asm/fpumacro.h>
  16. #include <asm/ptrace.h>
  17. #include <linux/uaccess.h>
  18. #include <asm/cacheflush.h>
  19. #include "sfp-util_64.h"
  20. #include <math-emu/soft-fp.h>
  21. #include <math-emu/single.h>
  22. #include <math-emu/double.h>
  23. #include <math-emu/quad.h>
  24. /* QUAD - ftt == 3 */
  25. #define FMOVQ 0x003
  26. #define FNEGQ 0x007
  27. #define FABSQ 0x00b
  28. #define FSQRTQ 0x02b
  29. #define FADDQ 0x043
  30. #define FSUBQ 0x047
  31. #define FMULQ 0x04b
  32. #define FDIVQ 0x04f
  33. #define FDMULQ 0x06e
  34. #define FQTOX 0x083
  35. #define FXTOQ 0x08c
  36. #define FQTOS 0x0c7
  37. #define FQTOD 0x0cb
  38. #define FITOQ 0x0cc
  39. #define FSTOQ 0x0cd
  40. #define FDTOQ 0x0ce
  41. #define FQTOI 0x0d3
  42. /* SUBNORMAL - ftt == 2 */
  43. #define FSQRTS 0x029
  44. #define FSQRTD 0x02a
  45. #define FADDS 0x041
  46. #define FADDD 0x042
  47. #define FSUBS 0x045
  48. #define FSUBD 0x046
  49. #define FMULS 0x049
  50. #define FMULD 0x04a
  51. #define FDIVS 0x04d
  52. #define FDIVD 0x04e
  53. #define FSMULD 0x069
  54. #define FSTOX 0x081
  55. #define FDTOX 0x082
  56. #define FDTOS 0x0c6
  57. #define FSTOD 0x0c9
  58. #define FSTOI 0x0d1
  59. #define FDTOI 0x0d2
  60. #define FXTOS 0x084 /* Only Ultra-III generates this. */
  61. #define FXTOD 0x088 /* Only Ultra-III generates this. */
  62. #if 0 /* Optimized inline in sparc64/kernel/entry.S */
  63. #define FITOS 0x0c4 /* Only Ultra-III generates this. */
  64. #endif
  65. #define FITOD 0x0c8 /* Only Ultra-III generates this. */
  66. /* FPOP2 */
  67. #define FCMPQ 0x053
  68. #define FCMPEQ 0x057
  69. #define FMOVQ0 0x003
  70. #define FMOVQ1 0x043
  71. #define FMOVQ2 0x083
  72. #define FMOVQ3 0x0c3
  73. #define FMOVQI 0x103
  74. #define FMOVQX 0x183
  75. #define FMOVQZ 0x027
  76. #define FMOVQLE 0x047
  77. #define FMOVQLZ 0x067
  78. #define FMOVQNZ 0x0a7
  79. #define FMOVQGZ 0x0c7
  80. #define FMOVQGE 0x0e7
  81. #define FSR_TEM_SHIFT 23UL
  82. #define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
  83. #define FSR_AEXC_SHIFT 5UL
  84. #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
  85. #define FSR_CEXC_SHIFT 0UL
  86. #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
  87. /* All routines returning an exception to raise should detect
  88. * such exceptions _before_ rounding to be consistent with
  89. * the behavior of the hardware in the implemented cases
  90. * (and thus with the recommendations in the V9 architecture
  91. * manual).
  92. *
  93. * We return 0 if a SIGFPE should be sent, 1 otherwise.
  94. */
  95. static inline int record_exception(struct pt_regs *regs, int eflag)
  96. {
  97. u64 fsr = current_thread_info()->xfsr[0];
  98. int would_trap;
  99. /* Determine if this exception would have generated a trap. */
  100. would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
  101. /* If trapping, we only want to signal one bit. */
  102. if(would_trap != 0) {
  103. eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
  104. if((eflag & (eflag - 1)) != 0) {
  105. if(eflag & FP_EX_INVALID)
  106. eflag = FP_EX_INVALID;
  107. else if(eflag & FP_EX_OVERFLOW)
  108. eflag = FP_EX_OVERFLOW;
  109. else if(eflag & FP_EX_UNDERFLOW)
  110. eflag = FP_EX_UNDERFLOW;
  111. else if(eflag & FP_EX_DIVZERO)
  112. eflag = FP_EX_DIVZERO;
  113. else if(eflag & FP_EX_INEXACT)
  114. eflag = FP_EX_INEXACT;
  115. }
  116. }
  117. /* Set CEXC, here is the rule:
  118. *
  119. * In general all FPU ops will set one and only one
  120. * bit in the CEXC field, this is always the case
  121. * when the IEEE exception trap is enabled in TEM.
  122. */
  123. fsr &= ~(FSR_CEXC_MASK);
  124. fsr |= ((long)eflag << FSR_CEXC_SHIFT);
  125. /* Set the AEXC field, rule is:
  126. *
  127. * If a trap would not be generated, the
  128. * CEXC just generated is OR'd into the
  129. * existing value of AEXC.
  130. */
  131. if(would_trap == 0)
  132. fsr |= ((long)eflag << FSR_AEXC_SHIFT);
  133. /* If trapping, indicate fault trap type IEEE. */
  134. if(would_trap != 0)
  135. fsr |= (1UL << 14);
  136. current_thread_info()->xfsr[0] = fsr;
  137. /* If we will not trap, advance the program counter over
  138. * the instruction being handled.
  139. */
  140. if(would_trap == 0) {
  141. regs->tpc = regs->tnpc;
  142. regs->tnpc += 4;
  143. }
  144. return (would_trap ? 0 : 1);
  145. }
  146. typedef union {
  147. u32 s;
  148. u64 d;
  149. u64 q[2];
  150. } *argp;
  151. int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap)
  152. {
  153. unsigned long pc = regs->tpc;
  154. unsigned long tstate = regs->tstate;
  155. u32 insn = 0;
  156. int type = 0;
  157. /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells
  158. whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
  159. non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
  160. #define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6) | (ftt << 9)
  161. int freg;
  162. static u64 zero[2] = { 0L, 0L };
  163. int flags;
  164. FP_DECL_EX;
  165. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  166. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  167. FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
  168. int IR;
  169. long XR, xfsr;
  170. if (tstate & TSTATE_PRIV)
  171. die_if_kernel("unfinished/unimplemented FPop from kernel", regs);
  172. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
  173. if (test_thread_flag(TIF_32BIT))
  174. pc = (u32)pc;
  175. if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
  176. if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
  177. switch ((insn >> 5) & 0x1ff) {
  178. /* QUAD - ftt == 3 */
  179. case FMOVQ:
  180. case FNEGQ:
  181. case FABSQ: TYPE(3,3,0,3,0,0,0); break;
  182. case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
  183. case FADDQ:
  184. case FSUBQ:
  185. case FMULQ:
  186. case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
  187. case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
  188. case FQTOX: TYPE(3,2,0,3,1,0,0); break;
  189. case FXTOQ: TYPE(3,3,1,2,0,0,0); break;
  190. case FQTOS: TYPE(3,1,1,3,1,0,0); break;
  191. case FQTOD: TYPE(3,2,1,3,1,0,0); break;
  192. case FITOQ: TYPE(3,3,1,1,0,0,0); break;
  193. case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
  194. case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
  195. case FQTOI: TYPE(3,1,0,3,1,0,0); break;
  196. /* We can get either unimplemented or unfinished
  197. * for these cases. Pre-Niagara systems generate
  198. * unfinished fpop for SUBNORMAL cases, and Niagara
  199. * always gives unimplemented fpop for fsqrt{s,d}.
  200. */
  201. case FSQRTS: {
  202. unsigned long x = current_thread_info()->xfsr[0];
  203. x = (x >> 14) & 0x7;
  204. TYPE(x,1,1,1,1,0,0);
  205. break;
  206. }
  207. case FSQRTD: {
  208. unsigned long x = current_thread_info()->xfsr[0];
  209. x = (x >> 14) & 0x7;
  210. TYPE(x,2,1,2,1,0,0);
  211. break;
  212. }
  213. /* SUBNORMAL - ftt == 2 */
  214. case FADDD:
  215. case FSUBD:
  216. case FMULD:
  217. case FDIVD: TYPE(2,2,1,2,1,2,1); break;
  218. case FADDS:
  219. case FSUBS:
  220. case FMULS:
  221. case FDIVS: TYPE(2,1,1,1,1,1,1); break;
  222. case FSMULD: TYPE(2,2,1,1,1,1,1); break;
  223. case FSTOX: TYPE(2,2,0,1,1,0,0); break;
  224. case FDTOX: TYPE(2,2,0,2,1,0,0); break;
  225. case FDTOS: TYPE(2,1,1,2,1,0,0); break;
  226. case FSTOD: TYPE(2,2,1,1,1,0,0); break;
  227. case FSTOI: TYPE(2,1,0,1,1,0,0); break;
  228. case FDTOI: TYPE(2,1,0,2,1,0,0); break;
  229. /* Only Ultra-III generates these */
  230. case FXTOS: TYPE(2,1,1,2,0,0,0); break;
  231. case FXTOD: TYPE(2,2,1,2,0,0,0); break;
  232. #if 0 /* Optimized inline in sparc64/kernel/entry.S */
  233. case FITOS: TYPE(2,1,1,1,0,0,0); break;
  234. #endif
  235. case FITOD: TYPE(2,2,1,1,0,0,0); break;
  236. }
  237. }
  238. else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
  239. IR = 2;
  240. switch ((insn >> 5) & 0x1ff) {
  241. case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
  242. case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
  243. /* Now the conditional fmovq support */
  244. case FMOVQ0:
  245. case FMOVQ1:
  246. case FMOVQ2:
  247. case FMOVQ3:
  248. /* fmovq %fccX, %fY, %fZ */
  249. if (!((insn >> 11) & 3))
  250. XR = current_thread_info()->xfsr[0] >> 10;
  251. else
  252. XR = current_thread_info()->xfsr[0] >> (30 + ((insn >> 10) & 0x6));
  253. XR &= 3;
  254. IR = 0;
  255. switch ((insn >> 14) & 0x7) {
  256. /* case 0: IR = 0; break; */ /* Never */
  257. case 1: if (XR) IR = 1; break; /* Not Equal */
  258. case 2: if (XR == 1 || XR == 2) IR = 1; break; /* Less or Greater */
  259. case 3: if (XR & 1) IR = 1; break; /* Unordered or Less */
  260. case 4: if (XR == 1) IR = 1; break; /* Less */
  261. case 5: if (XR & 2) IR = 1; break; /* Unordered or Greater */
  262. case 6: if (XR == 2) IR = 1; break; /* Greater */
  263. case 7: if (XR == 3) IR = 1; break; /* Unordered */
  264. }
  265. if ((insn >> 14) & 8)
  266. IR ^= 1;
  267. break;
  268. case FMOVQI:
  269. case FMOVQX:
  270. /* fmovq %[ix]cc, %fY, %fZ */
  271. XR = regs->tstate >> 32;
  272. if ((insn >> 5) & 0x80)
  273. XR >>= 4;
  274. XR &= 0xf;
  275. IR = 0;
  276. freg = ((XR >> 2) ^ XR) & 2;
  277. switch ((insn >> 14) & 0x7) {
  278. /* case 0: IR = 0; break; */ /* Never */
  279. case 1: if (XR & 4) IR = 1; break; /* Equal */
  280. case 2: if ((XR & 4) || freg) IR = 1; break; /* Less or Equal */
  281. case 3: if (freg) IR = 1; break; /* Less */
  282. case 4: if (XR & 5) IR = 1; break; /* Less or Equal Unsigned */
  283. case 5: if (XR & 1) IR = 1; break; /* Carry Set */
  284. case 6: if (XR & 8) IR = 1; break; /* Negative */
  285. case 7: if (XR & 2) IR = 1; break; /* Overflow Set */
  286. }
  287. if ((insn >> 14) & 8)
  288. IR ^= 1;
  289. break;
  290. case FMOVQZ:
  291. case FMOVQLE:
  292. case FMOVQLZ:
  293. case FMOVQNZ:
  294. case FMOVQGZ:
  295. case FMOVQGE:
  296. freg = (insn >> 14) & 0x1f;
  297. if (!freg)
  298. XR = 0;
  299. else if (freg < 16)
  300. XR = regs->u_regs[freg];
  301. else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
  302. struct reg_window32 __user *win32;
  303. flushw_user ();
  304. win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
  305. get_user(XR, &win32->locals[freg - 16]);
  306. } else {
  307. struct reg_window __user *win;
  308. flushw_user ();
  309. win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
  310. get_user(XR, &win->locals[freg - 16]);
  311. }
  312. IR = 0;
  313. switch ((insn >> 10) & 3) {
  314. case 1: if (!XR) IR = 1; break; /* Register Zero */
  315. case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */
  316. case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */
  317. }
  318. if ((insn >> 10) & 4)
  319. IR ^= 1;
  320. break;
  321. }
  322. if (IR == 0) {
  323. /* The fmov test was false. Do a nop instead */
  324. current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK);
  325. regs->tpc = regs->tnpc;
  326. regs->tnpc += 4;
  327. return 1;
  328. } else if (IR == 1) {
  329. /* Change the instruction into plain fmovq */
  330. insn = (insn & 0x3e00001f) | 0x81a00060;
  331. TYPE(3,3,0,3,0,0,0);
  332. }
  333. }
  334. }
  335. if (type) {
  336. argp rs1 = NULL, rs2 = NULL, rd = NULL;
  337. /* Starting with UltraSPARC-T2, the cpu does not set the FP Trap
  338. * Type field in the %fsr to unimplemented_FPop. Nor does it
  339. * use the fp_exception_other trap. Instead it signals an
  340. * illegal instruction and leaves the FP trap type field of
  341. * the %fsr unchanged.
  342. */
  343. if (!illegal_insn_trap) {
  344. int ftt = (current_thread_info()->xfsr[0] >> 14) & 0x7;
  345. if (ftt != (type >> 9))
  346. goto err;
  347. }
  348. current_thread_info()->xfsr[0] &= ~0x1c000;
  349. freg = ((insn >> 14) & 0x1f);
  350. switch (type & 0x3) {
  351. case 3: if (freg & 2) {
  352. current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
  353. goto err;
  354. }
  355. case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
  356. case 1: rs1 = (argp)&f->regs[freg];
  357. flags = (freg < 32) ? FPRS_DL : FPRS_DU;
  358. if (!(current_thread_info()->fpsaved[0] & flags))
  359. rs1 = (argp)&zero;
  360. break;
  361. }
  362. switch (type & 0x7) {
  363. case 7: FP_UNPACK_QP (QA, rs1); break;
  364. case 6: FP_UNPACK_DP (DA, rs1); break;
  365. case 5: FP_UNPACK_SP (SA, rs1); break;
  366. }
  367. freg = (insn & 0x1f);
  368. switch ((type >> 3) & 0x3) {
  369. case 3: if (freg & 2) {
  370. current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
  371. goto err;
  372. }
  373. case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
  374. case 1: rs2 = (argp)&f->regs[freg];
  375. flags = (freg < 32) ? FPRS_DL : FPRS_DU;
  376. if (!(current_thread_info()->fpsaved[0] & flags))
  377. rs2 = (argp)&zero;
  378. break;
  379. }
  380. switch ((type >> 3) & 0x7) {
  381. case 7: FP_UNPACK_QP (QB, rs2); break;
  382. case 6: FP_UNPACK_DP (DB, rs2); break;
  383. case 5: FP_UNPACK_SP (SB, rs2); break;
  384. }
  385. freg = ((insn >> 25) & 0x1f);
  386. switch ((type >> 6) & 0x3) {
  387. case 3: if (freg & 2) {
  388. current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
  389. goto err;
  390. }
  391. case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
  392. case 1: rd = (argp)&f->regs[freg];
  393. flags = (freg < 32) ? FPRS_DL : FPRS_DU;
  394. if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
  395. current_thread_info()->fpsaved[0] = FPRS_FEF;
  396. current_thread_info()->gsr[0] = 0;
  397. }
  398. if (!(current_thread_info()->fpsaved[0] & flags)) {
  399. if (freg < 32)
  400. memset(f->regs, 0, 32*sizeof(u32));
  401. else
  402. memset(f->regs+32, 0, 32*sizeof(u32));
  403. }
  404. current_thread_info()->fpsaved[0] |= flags;
  405. break;
  406. }
  407. switch ((insn >> 5) & 0x1ff) {
  408. /* + */
  409. case FADDS: FP_ADD_S (SR, SA, SB); break;
  410. case FADDD: FP_ADD_D (DR, DA, DB); break;
  411. case FADDQ: FP_ADD_Q (QR, QA, QB); break;
  412. /* - */
  413. case FSUBS: FP_SUB_S (SR, SA, SB); break;
  414. case FSUBD: FP_SUB_D (DR, DA, DB); break;
  415. case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
  416. /* * */
  417. case FMULS: FP_MUL_S (SR, SA, SB); break;
  418. case FSMULD: FP_CONV (D, S, 1, 1, DA, SA);
  419. FP_CONV (D, S, 1, 1, DB, SB);
  420. case FMULD: FP_MUL_D (DR, DA, DB); break;
  421. case FDMULQ: FP_CONV (Q, D, 2, 1, QA, DA);
  422. FP_CONV (Q, D, 2, 1, QB, DB);
  423. case FMULQ: FP_MUL_Q (QR, QA, QB); break;
  424. /* / */
  425. case FDIVS: FP_DIV_S (SR, SA, SB); break;
  426. case FDIVD: FP_DIV_D (DR, DA, DB); break;
  427. case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
  428. /* sqrt */
  429. case FSQRTS: FP_SQRT_S (SR, SB); break;
  430. case FSQRTD: FP_SQRT_D (DR, DB); break;
  431. case FSQRTQ: FP_SQRT_Q (QR, QB); break;
  432. /* mov */
  433. case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break;
  434. case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break;
  435. case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break;
  436. /* float to int */
  437. case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
  438. case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
  439. case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
  440. case FSTOX: FP_TO_INT_S (XR, SB, 64, 1); break;
  441. case FDTOX: FP_TO_INT_D (XR, DB, 64, 1); break;
  442. case FQTOX: FP_TO_INT_Q (XR, QB, 64, 1); break;
  443. /* int to float */
  444. case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
  445. case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break;
  446. /* Only Ultra-III generates these */
  447. case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break;
  448. case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break;
  449. #if 0 /* Optimized inline in sparc64/kernel/entry.S */
  450. case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
  451. #endif
  452. case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
  453. /* float to float */
  454. case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break;
  455. case FSTOQ: FP_CONV (Q, S, 2, 1, QR, SB); break;
  456. case FDTOQ: FP_CONV (Q, D, 2, 1, QR, DB); break;
  457. case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break;
  458. case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break;
  459. case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break;
  460. /* comparison */
  461. case FCMPQ:
  462. case FCMPEQ:
  463. FP_CMP_Q(XR, QB, QA, 3);
  464. if (XR == 3 &&
  465. (((insn >> 5) & 0x1ff) == FCMPEQ ||
  466. FP_ISSIGNAN_Q(QA) ||
  467. FP_ISSIGNAN_Q(QB)))
  468. FP_SET_EXCEPTION (FP_EX_INVALID);
  469. }
  470. if (!FP_INHIBIT_RESULTS) {
  471. switch ((type >> 6) & 0x7) {
  472. case 0: xfsr = current_thread_info()->xfsr[0];
  473. if (XR == -1) XR = 2;
  474. switch (freg & 3) {
  475. /* fcc0, 1, 2, 3 */
  476. case 0: xfsr &= ~0xc00; xfsr |= (XR << 10); break;
  477. case 1: xfsr &= ~0x300000000UL; xfsr |= (XR << 32); break;
  478. case 2: xfsr &= ~0xc00000000UL; xfsr |= (XR << 34); break;
  479. case 3: xfsr &= ~0x3000000000UL; xfsr |= (XR << 36); break;
  480. }
  481. current_thread_info()->xfsr[0] = xfsr;
  482. break;
  483. case 1: rd->s = IR; break;
  484. case 2: rd->d = XR; break;
  485. case 5: FP_PACK_SP (rd, SR); break;
  486. case 6: FP_PACK_DP (rd, DR); break;
  487. case 7: FP_PACK_QP (rd, QR); break;
  488. }
  489. }
  490. if(_fex != 0)
  491. return record_exception(regs, _fex);
  492. /* Success and no exceptions detected. */
  493. current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK);
  494. regs->tpc = regs->tnpc;
  495. regs->tnpc += 4;
  496. return 1;
  497. }
  498. err: return 0;
  499. }