math_32.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * arch/sparc/math-emu/math.c
  4. *
  5. * Copyright (C) 1998 Peter Maydell (pmaydell@chiark.greenend.org.uk)
  6. * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
  7. * Copyright (C) 1999 David S. Miller (davem@redhat.com)
  8. *
  9. * This is a good place to start if you're trying to understand the
  10. * emulation code, because it's pretty simple. What we do is
  11. * essentially analyse the instruction to work out what the operation
  12. * is and which registers are involved. We then execute the appropriate
  13. * FXXXX function. [The floating point queue introduces a minor wrinkle;
  14. * see below...]
  15. * The fxxxxx.c files each emulate a single insn. They look relatively
  16. * simple because the complexity is hidden away in an unholy tangle
  17. * of preprocessor macros.
  18. *
  19. * The first layer of macros is single.h, double.h, quad.h. Generally
  20. * these files define macros for working with floating point numbers
  21. * of the three IEEE formats. FP_ADD_D(R,A,B) is for adding doubles,
  22. * for instance. These macros are usually defined as calls to more
  23. * generic macros (in this case _FP_ADD(D,2,R,X,Y) where the number
  24. * of machine words required to store the given IEEE format is passed
  25. * as a parameter. [double.h and co check the number of bits in a word
  26. * and define FP_ADD_D & co appropriately].
  27. * The generic macros are defined in op-common.h. This is where all
  28. * the grotty stuff like handling NaNs is coded. To handle the possible
  29. * word sizes macros in op-common.h use macros like _FP_FRAC_SLL_##wc()
  30. * where wc is the 'number of machine words' parameter (here 2).
  31. * These are defined in the third layer of macros: op-1.h, op-2.h
  32. * and op-4.h. These handle operations on floating point numbers composed
  33. * of 1,2 and 4 machine words respectively. [For example, on sparc64
  34. * doubles are one machine word so macros in double.h eventually use
  35. * constructs in op-1.h, but on sparc32 they use op-2.h definitions.]
  36. * soft-fp.h is on the same level as op-common.h, and defines some
  37. * macros which are independent of both word size and FP format.
  38. * Finally, sfp-machine.h is the machine dependent part of the
  39. * code: it defines the word size and what type a word is. It also
  40. * defines how _FP_MUL_MEAT_t() maps to _FP_MUL_MEAT_n_* : op-n.h
  41. * provide several possible flavours of multiply algorithm, most
  42. * of which require that you supply some form of asm or C primitive to
  43. * do the actual multiply. (such asm primitives should be defined
  44. * in sfp-machine.h too). udivmodti4.c is the same sort of thing.
  45. *
  46. * There may be some errors here because I'm working from a
  47. * SPARC architecture manual V9, and what I really want is V8...
  48. * Also, the insns which can generate exceptions seem to be a
  49. * greater subset of the FPops than for V9 (for example, FCMPED
  50. * has to be emulated on V8). So I think I'm going to have
  51. * to emulate them all just to be on the safe side...
  52. *
  53. * Emulation routines originate from soft-fp package, which is
  54. * part of glibc and has appropriate copyrights in it (allegedly).
  55. *
  56. * NB: on sparc int == long == 4 bytes, long long == 8 bytes.
  57. * Most bits of the kernel seem to go for long rather than int,
  58. * so we follow that practice...
  59. */
  60. /* TODO:
  61. * fpsave() saves the FP queue but fpload() doesn't reload it.
  62. * Therefore when we context switch or change FPU ownership
  63. * we have to check to see if the queue had anything in it and
  64. * emulate it if it did. This is going to be a pain.
  65. */
  66. #include <linux/types.h>
  67. #include <linux/sched.h>
  68. #include <linux/mm.h>
  69. #include <linux/perf_event.h>
  70. #include <linux/uaccess.h>
  71. #include "sfp-util_32.h"
  72. #include <math-emu/soft-fp.h>
  73. #include <math-emu/single.h>
  74. #include <math-emu/double.h>
  75. #include <math-emu/quad.h>
  76. #define FLOATFUNC(x) extern int x(void *,void *,void *)
  77. /* The Vn labels indicate what version of the SPARC architecture gas thinks
  78. * each insn is. This is from the binutils source :->
  79. */
  80. /* quadword instructions */
  81. #define FSQRTQ 0x02b /* v8 */
  82. #define FADDQ 0x043 /* v8 */
  83. #define FSUBQ 0x047 /* v8 */
  84. #define FMULQ 0x04b /* v8 */
  85. #define FDIVQ 0x04f /* v8 */
  86. #define FDMULQ 0x06e /* v8 */
  87. #define FQTOS 0x0c7 /* v8 */
  88. #define FQTOD 0x0cb /* v8 */
  89. #define FITOQ 0x0cc /* v8 */
  90. #define FSTOQ 0x0cd /* v8 */
  91. #define FDTOQ 0x0ce /* v8 */
  92. #define FQTOI 0x0d3 /* v8 */
  93. #define FCMPQ 0x053 /* v8 */
  94. #define FCMPEQ 0x057 /* v8 */
  95. /* single/double instructions (subnormal): should all work */
  96. #define FSQRTS 0x029 /* v7 */
  97. #define FSQRTD 0x02a /* v7 */
  98. #define FADDS 0x041 /* v6 */
  99. #define FADDD 0x042 /* v6 */
  100. #define FSUBS 0x045 /* v6 */
  101. #define FSUBD 0x046 /* v6 */
  102. #define FMULS 0x049 /* v6 */
  103. #define FMULD 0x04a /* v6 */
  104. #define FDIVS 0x04d /* v6 */
  105. #define FDIVD 0x04e /* v6 */
  106. #define FSMULD 0x069 /* v6 */
  107. #define FDTOS 0x0c6 /* v6 */
  108. #define FSTOD 0x0c9 /* v6 */
  109. #define FSTOI 0x0d1 /* v6 */
  110. #define FDTOI 0x0d2 /* v6 */
  111. #define FABSS 0x009 /* v6 */
  112. #define FCMPS 0x051 /* v6 */
  113. #define FCMPES 0x055 /* v6 */
  114. #define FCMPD 0x052 /* v6 */
  115. #define FCMPED 0x056 /* v6 */
  116. #define FMOVS 0x001 /* v6 */
  117. #define FNEGS 0x005 /* v6 */
  118. #define FITOS 0x0c4 /* v6 */
  119. #define FITOD 0x0c8 /* v6 */
  120. #define FSR_TEM_SHIFT 23UL
  121. #define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
  122. #define FSR_AEXC_SHIFT 5UL
  123. #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
  124. #define FSR_CEXC_SHIFT 0UL
  125. #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
  126. static int do_one_mathemu(u32 insn, unsigned long *fsr, unsigned long *fregs);
  127. /* Unlike the Sparc64 version (which has a struct fpustate), we
  128. * pass the taskstruct corresponding to the task which currently owns the
  129. * FPU. This is partly because we don't have the fpustate struct and
  130. * partly because the task owning the FPU isn't always current (as is
  131. * the case for the Sparc64 port). This is probably SMP-related...
  132. * This function returns 1 if all queued insns were emulated successfully.
  133. * The test for unimplemented FPop in kernel mode has been moved into
  134. * kernel/traps.c for simplicity.
  135. */
  136. int do_mathemu(struct pt_regs *regs, struct task_struct *fpt)
  137. {
  138. /* regs->pc isn't necessarily the PC at which the offending insn is sitting.
  139. * The FPU maintains a queue of FPops which cause traps.
  140. * When it hits an instruction that requires that the trapped op succeeded
  141. * (usually because it reads a reg. that the trapped op wrote) then it
  142. * causes this exception. We need to emulate all the insns on the queue
  143. * and then allow the op to proceed.
  144. * This code should also handle the case where the trap was precise,
  145. * in which case the queue length is zero and regs->pc points at the
  146. * single FPop to be emulated. (this case is untested, though :->)
  147. * You'll need this case if you want to be able to emulate all FPops
  148. * because the FPU either doesn't exist or has been software-disabled.
  149. * [The UltraSPARC makes FP a precise trap; this isn't as stupid as it
  150. * might sound because the Ultra does funky things with a superscalar
  151. * architecture.]
  152. */
  153. /* You wouldn't believe how often I typed 'ftp' when I meant 'fpt' :-> */
  154. int i;
  155. int retcode = 0; /* assume all succeed */
  156. unsigned long insn;
  157. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
  158. #ifdef DEBUG_MATHEMU
  159. printk("In do_mathemu()... pc is %08lx\n", regs->pc);
  160. printk("fpqdepth is %ld\n", fpt->thread.fpqdepth);
  161. for (i = 0; i < fpt->thread.fpqdepth; i++)
  162. printk("%d: %08lx at %08lx\n", i, fpt->thread.fpqueue[i].insn,
  163. (unsigned long)fpt->thread.fpqueue[i].insn_addr);
  164. #endif
  165. if (fpt->thread.fpqdepth == 0) { /* no queue, guilty insn is at regs->pc */
  166. #ifdef DEBUG_MATHEMU
  167. printk("precise trap at %08lx\n", regs->pc);
  168. #endif
  169. if (!get_user(insn, (u32 __user *) regs->pc)) {
  170. retcode = do_one_mathemu(insn, &fpt->thread.fsr, fpt->thread.float_regs);
  171. if (retcode) {
  172. /* in this case we need to fix up PC & nPC */
  173. regs->pc = regs->npc;
  174. regs->npc += 4;
  175. }
  176. }
  177. return retcode;
  178. }
  179. /* Normal case: need to empty the queue... */
  180. for (i = 0; i < fpt->thread.fpqdepth; i++) {
  181. retcode = do_one_mathemu(fpt->thread.fpqueue[i].insn, &(fpt->thread.fsr), fpt->thread.float_regs);
  182. if (!retcode) /* insn failed, no point doing any more */
  183. break;
  184. }
  185. /* Now empty the queue and clear the queue_not_empty flag */
  186. if (retcode)
  187. fpt->thread.fsr &= ~(0x3000 | FSR_CEXC_MASK);
  188. else
  189. fpt->thread.fsr &= ~0x3000;
  190. fpt->thread.fpqdepth = 0;
  191. return retcode;
  192. }
  193. /* All routines returning an exception to raise should detect
  194. * such exceptions _before_ rounding to be consistent with
  195. * the behavior of the hardware in the implemented cases
  196. * (and thus with the recommendations in the V9 architecture
  197. * manual).
  198. *
  199. * We return 0 if a SIGFPE should be sent, 1 otherwise.
  200. */
  201. static inline int record_exception(unsigned long *pfsr, int eflag)
  202. {
  203. unsigned long fsr = *pfsr;
  204. int would_trap;
  205. /* Determine if this exception would have generated a trap. */
  206. would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
  207. /* If trapping, we only want to signal one bit. */
  208. if (would_trap != 0) {
  209. eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
  210. if ((eflag & (eflag - 1)) != 0) {
  211. if (eflag & FP_EX_INVALID)
  212. eflag = FP_EX_INVALID;
  213. else if (eflag & FP_EX_OVERFLOW)
  214. eflag = FP_EX_OVERFLOW;
  215. else if (eflag & FP_EX_UNDERFLOW)
  216. eflag = FP_EX_UNDERFLOW;
  217. else if (eflag & FP_EX_DIVZERO)
  218. eflag = FP_EX_DIVZERO;
  219. else if (eflag & FP_EX_INEXACT)
  220. eflag = FP_EX_INEXACT;
  221. }
  222. }
  223. /* Set CEXC, here is the rule:
  224. *
  225. * In general all FPU ops will set one and only one
  226. * bit in the CEXC field, this is always the case
  227. * when the IEEE exception trap is enabled in TEM.
  228. */
  229. fsr &= ~(FSR_CEXC_MASK);
  230. fsr |= ((long)eflag << FSR_CEXC_SHIFT);
  231. /* Set the AEXC field, rule is:
  232. *
  233. * If a trap would not be generated, the
  234. * CEXC just generated is OR'd into the
  235. * existing value of AEXC.
  236. */
  237. if (would_trap == 0)
  238. fsr |= ((long)eflag << FSR_AEXC_SHIFT);
  239. /* If trapping, indicate fault trap type IEEE. */
  240. if (would_trap != 0)
  241. fsr |= (1UL << 14);
  242. *pfsr = fsr;
  243. return (would_trap ? 0 : 1);
  244. }
  245. typedef union {
  246. u32 s;
  247. u64 d;
  248. u64 q[2];
  249. } *argp;
  250. static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs)
  251. {
  252. /* Emulate the given insn, updating fsr and fregs appropriately. */
  253. int type = 0;
  254. /* r is rd, b is rs2 and a is rs1. The *u arg tells
  255. whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
  256. non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
  257. #define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6)
  258. int freg;
  259. argp rs1 = NULL, rs2 = NULL, rd = NULL;
  260. FP_DECL_EX;
  261. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  262. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  263. FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
  264. int IR;
  265. long fsr;
  266. #ifdef DEBUG_MATHEMU
  267. printk("In do_mathemu(), emulating %08lx\n", insn);
  268. #endif
  269. if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
  270. switch ((insn >> 5) & 0x1ff) {
  271. case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
  272. case FADDQ:
  273. case FSUBQ:
  274. case FMULQ:
  275. case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
  276. case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
  277. case FQTOS: TYPE(3,1,1,3,1,0,0); break;
  278. case FQTOD: TYPE(3,2,1,3,1,0,0); break;
  279. case FITOQ: TYPE(3,3,1,1,0,0,0); break;
  280. case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
  281. case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
  282. case FQTOI: TYPE(3,1,0,3,1,0,0); break;
  283. case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
  284. case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
  285. case FADDD:
  286. case FSUBD:
  287. case FMULD:
  288. case FDIVD: TYPE(2,2,1,2,1,2,1); break;
  289. case FADDS:
  290. case FSUBS:
  291. case FMULS:
  292. case FDIVS: TYPE(2,1,1,1,1,1,1); break;
  293. case FSMULD: TYPE(2,2,1,1,1,1,1); break;
  294. case FDTOS: TYPE(2,1,1,2,1,0,0); break;
  295. case FSTOD: TYPE(2,2,1,1,1,0,0); break;
  296. case FSTOI: TYPE(2,1,0,1,1,0,0); break;
  297. case FDTOI: TYPE(2,1,0,2,1,0,0); break;
  298. case FITOS: TYPE(2,1,1,1,0,0,0); break;
  299. case FITOD: TYPE(2,2,1,1,0,0,0); break;
  300. case FMOVS:
  301. case FABSS:
  302. case FNEGS: TYPE(2,1,0,1,0,0,0); break;
  303. }
  304. } else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
  305. switch ((insn >> 5) & 0x1ff) {
  306. case FCMPS: TYPE(3,0,0,1,1,1,1); break;
  307. case FCMPES: TYPE(3,0,0,1,1,1,1); break;
  308. case FCMPD: TYPE(3,0,0,2,1,2,1); break;
  309. case FCMPED: TYPE(3,0,0,2,1,2,1); break;
  310. case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
  311. case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
  312. }
  313. }
  314. if (!type) { /* oops, didn't recognise that FPop */
  315. #ifdef DEBUG_MATHEMU
  316. printk("attempt to emulate unrecognised FPop!\n");
  317. #endif
  318. return 0;
  319. }
  320. /* Decode the registers to be used */
  321. freg = (*pfsr >> 14) & 0xf;
  322. *pfsr &= ~0x1c000; /* clear the traptype bits */
  323. freg = ((insn >> 14) & 0x1f);
  324. switch (type & 0x3) { /* is rs1 single, double or quad? */
  325. case 3:
  326. if (freg & 3) { /* quadwords must have bits 4&5 of the */
  327. /* encoded reg. number set to zero. */
  328. *pfsr |= (6 << 14);
  329. return 0; /* simulate invalid_fp_register exception */
  330. }
  331. fallthrough;
  332. case 2:
  333. if (freg & 1) { /* doublewords must have bit 5 zeroed */
  334. *pfsr |= (6 << 14);
  335. return 0;
  336. }
  337. }
  338. rs1 = (argp)&fregs[freg];
  339. switch (type & 0x7) {
  340. case 7: FP_UNPACK_QP (QA, rs1); break;
  341. case 6: FP_UNPACK_DP (DA, rs1); break;
  342. case 5: FP_UNPACK_SP (SA, rs1); break;
  343. }
  344. freg = (insn & 0x1f);
  345. switch ((type >> 3) & 0x3) { /* same again for rs2 */
  346. case 3:
  347. if (freg & 3) { /* quadwords must have bits 4&5 of the */
  348. /* encoded reg. number set to zero. */
  349. *pfsr |= (6 << 14);
  350. return 0; /* simulate invalid_fp_register exception */
  351. }
  352. fallthrough;
  353. case 2:
  354. if (freg & 1) { /* doublewords must have bit 5 zeroed */
  355. *pfsr |= (6 << 14);
  356. return 0;
  357. }
  358. }
  359. rs2 = (argp)&fregs[freg];
  360. switch ((type >> 3) & 0x7) {
  361. case 7: FP_UNPACK_QP (QB, rs2); break;
  362. case 6: FP_UNPACK_DP (DB, rs2); break;
  363. case 5: FP_UNPACK_SP (SB, rs2); break;
  364. }
  365. freg = ((insn >> 25) & 0x1f);
  366. switch ((type >> 6) & 0x3) { /* and finally rd. This one's a bit different */
  367. case 0: /* dest is fcc. (this must be FCMPQ or FCMPEQ) */
  368. if (freg) { /* V8 has only one set of condition codes, so */
  369. /* anything but 0 in the rd field is an error */
  370. *pfsr |= (6 << 14); /* (should probably flag as invalid opcode */
  371. return 0; /* but SIGFPE will do :-> ) */
  372. }
  373. break;
  374. case 3:
  375. if (freg & 3) { /* quadwords must have bits 4&5 of the */
  376. /* encoded reg. number set to zero. */
  377. *pfsr |= (6 << 14);
  378. return 0; /* simulate invalid_fp_register exception */
  379. }
  380. fallthrough;
  381. case 2:
  382. if (freg & 1) { /* doublewords must have bit 5 zeroed */
  383. *pfsr |= (6 << 14);
  384. return 0;
  385. }
  386. fallthrough;
  387. case 1:
  388. rd = (void *)&fregs[freg];
  389. break;
  390. }
  391. #ifdef DEBUG_MATHEMU
  392. printk("executing insn...\n");
  393. #endif
  394. /* do the Right Thing */
  395. switch ((insn >> 5) & 0x1ff) {
  396. /* + */
  397. case FADDS: FP_ADD_S (SR, SA, SB); break;
  398. case FADDD: FP_ADD_D (DR, DA, DB); break;
  399. case FADDQ: FP_ADD_Q (QR, QA, QB); break;
  400. /* - */
  401. case FSUBS: FP_SUB_S (SR, SA, SB); break;
  402. case FSUBD: FP_SUB_D (DR, DA, DB); break;
  403. case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
  404. /* * */
  405. case FMULS: FP_MUL_S (SR, SA, SB); break;
  406. case FSMULD: FP_CONV (D, S, 2, 1, DA, SA);
  407. FP_CONV (D, S, 2, 1, DB, SB);
  408. case FMULD: FP_MUL_D (DR, DA, DB); break;
  409. case FDMULQ: FP_CONV (Q, D, 4, 2, QA, DA);
  410. FP_CONV (Q, D, 4, 2, QB, DB);
  411. case FMULQ: FP_MUL_Q (QR, QA, QB); break;
  412. /* / */
  413. case FDIVS: FP_DIV_S (SR, SA, SB); break;
  414. case FDIVD: FP_DIV_D (DR, DA, DB); break;
  415. case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
  416. /* sqrt */
  417. case FSQRTS: FP_SQRT_S (SR, SB); break;
  418. case FSQRTD: FP_SQRT_D (DR, DB); break;
  419. case FSQRTQ: FP_SQRT_Q (QR, QB); break;
  420. /* mov */
  421. case FMOVS: rd->s = rs2->s; break;
  422. case FABSS: rd->s = rs2->s & 0x7fffffff; break;
  423. case FNEGS: rd->s = rs2->s ^ 0x80000000; break;
  424. /* float to int */
  425. case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
  426. case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
  427. case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
  428. /* int to float */
  429. case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
  430. case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
  431. case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
  432. /* float to float */
  433. case FSTOD: FP_CONV (D, S, 2, 1, DR, SB); break;
  434. case FSTOQ: FP_CONV (Q, S, 4, 1, QR, SB); break;
  435. case FDTOQ: FP_CONV (Q, D, 4, 2, QR, DB); break;
  436. case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break;
  437. case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break;
  438. case FQTOD: FP_CONV (D, Q, 2, 4, DR, QB); break;
  439. /* comparison */
  440. case FCMPS:
  441. case FCMPES:
  442. FP_CMP_S(IR, SB, SA, 3);
  443. if (IR == 3 &&
  444. (((insn >> 5) & 0x1ff) == FCMPES ||
  445. FP_ISSIGNAN_S(SA) ||
  446. FP_ISSIGNAN_S(SB)))
  447. FP_SET_EXCEPTION (FP_EX_INVALID);
  448. break;
  449. case FCMPD:
  450. case FCMPED:
  451. FP_CMP_D(IR, DB, DA, 3);
  452. if (IR == 3 &&
  453. (((insn >> 5) & 0x1ff) == FCMPED ||
  454. FP_ISSIGNAN_D(DA) ||
  455. FP_ISSIGNAN_D(DB)))
  456. FP_SET_EXCEPTION (FP_EX_INVALID);
  457. break;
  458. case FCMPQ:
  459. case FCMPEQ:
  460. FP_CMP_Q(IR, QB, QA, 3);
  461. if (IR == 3 &&
  462. (((insn >> 5) & 0x1ff) == FCMPEQ ||
  463. FP_ISSIGNAN_Q(QA) ||
  464. FP_ISSIGNAN_Q(QB)))
  465. FP_SET_EXCEPTION (FP_EX_INVALID);
  466. }
  467. if (!FP_INHIBIT_RESULTS) {
  468. switch ((type >> 6) & 0x7) {
  469. case 0: fsr = *pfsr;
  470. if (IR == -1) IR = 2;
  471. /* fcc is always fcc0 */
  472. fsr &= ~0xc00; fsr |= (IR << 10);
  473. *pfsr = fsr;
  474. break;
  475. case 1: rd->s = IR; break;
  476. case 5: FP_PACK_SP (rd, SR); break;
  477. case 6: FP_PACK_DP (rd, DR); break;
  478. case 7: FP_PACK_QP (rd, QR); break;
  479. }
  480. }
  481. if (_fex == 0)
  482. return 1; /* success! */
  483. return record_exception(pfsr, _fex);
  484. }