winfixup.S 3.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* winfixup.S: Handle cases where user stack pointer is found to be bogus.
  3. *
  4. * Copyright (C) 1997, 2006 David S. Miller (davem@davemloft.net)
  5. */
  6. #include <asm/asi.h>
  7. #include <asm/head.h>
  8. #include <asm/page.h>
  9. #include <asm/ptrace.h>
  10. #include <asm/processor.h>
  11. #include <asm/spitfire.h>
  12. #include <asm/thread_info.h>
  13. .text
  14. /* It used to be the case that these register window fault
  15. * handlers could run via the save and restore instructions
  16. * done by the trap entry and exit code. They now do the
  17. * window spill/fill by hand, so that case no longer can occur.
  18. */
  19. .align 32
  20. fill_fixup:
  21. TRAP_LOAD_THREAD_REG(%g6, %g1)
  22. rdpr %tstate, %g1
  23. and %g1, TSTATE_CWP, %g1
  24. or %g4, FAULT_CODE_WINFIXUP, %g4
  25. stb %g4, [%g6 + TI_FAULT_CODE]
  26. stx %g5, [%g6 + TI_FAULT_ADDR]
  27. wrpr %g1, %cwp
  28. ba,pt %xcc, etrap
  29. rd %pc, %g7
  30. call do_sparc64_fault
  31. add %sp, PTREGS_OFF, %o0
  32. ba,a,pt %xcc, rtrap
  33. /* Be very careful about usage of the trap globals here.
  34. * You cannot touch %g5 as that has the fault information.
  35. */
  36. spill_fixup:
  37. spill_fixup_mna:
  38. spill_fixup_dax:
  39. TRAP_LOAD_THREAD_REG(%g6, %g1)
  40. ldx [%g6 + TI_FLAGS], %g1
  41. andcc %sp, 0x1, %g0
  42. movne %icc, 0, %g1
  43. andcc %g1, _TIF_32BIT, %g0
  44. ldub [%g6 + TI_WSAVED], %g1
  45. sll %g1, 3, %g3
  46. add %g6, %g3, %g3
  47. stx %sp, [%g3 + TI_RWIN_SPTRS]
  48. sll %g1, 7, %g3
  49. bne,pt %xcc, 1f
  50. add %g6, %g3, %g3
  51. stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
  52. stx %l1, [%g3 + TI_REG_WINDOW + 0x08]
  53. stx %l2, [%g3 + TI_REG_WINDOW + 0x10]
  54. stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
  55. stx %l4, [%g3 + TI_REG_WINDOW + 0x20]
  56. stx %l5, [%g3 + TI_REG_WINDOW + 0x28]
  57. stx %l6, [%g3 + TI_REG_WINDOW + 0x30]
  58. stx %l7, [%g3 + TI_REG_WINDOW + 0x38]
  59. stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
  60. stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
  61. stx %i2, [%g3 + TI_REG_WINDOW + 0x50]
  62. stx %i3, [%g3 + TI_REG_WINDOW + 0x58]
  63. stx %i4, [%g3 + TI_REG_WINDOW + 0x60]
  64. stx %i5, [%g3 + TI_REG_WINDOW + 0x68]
  65. stx %i6, [%g3 + TI_REG_WINDOW + 0x70]
  66. ba,pt %xcc, 2f
  67. stx %i7, [%g3 + TI_REG_WINDOW + 0x78]
  68. 1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00]
  69. stw %l1, [%g3 + TI_REG_WINDOW + 0x04]
  70. stw %l2, [%g3 + TI_REG_WINDOW + 0x08]
  71. stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]
  72. stw %l4, [%g3 + TI_REG_WINDOW + 0x10]
  73. stw %l5, [%g3 + TI_REG_WINDOW + 0x14]
  74. stw %l6, [%g3 + TI_REG_WINDOW + 0x18]
  75. stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]
  76. stw %i0, [%g3 + TI_REG_WINDOW + 0x20]
  77. stw %i1, [%g3 + TI_REG_WINDOW + 0x24]
  78. stw %i2, [%g3 + TI_REG_WINDOW + 0x28]
  79. stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]
  80. stw %i4, [%g3 + TI_REG_WINDOW + 0x30]
  81. stw %i5, [%g3 + TI_REG_WINDOW + 0x34]
  82. stw %i6, [%g3 + TI_REG_WINDOW + 0x38]
  83. stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]
  84. 2: add %g1, 1, %g1
  85. stb %g1, [%g6 + TI_WSAVED]
  86. rdpr %tstate, %g1
  87. andcc %g1, TSTATE_PRIV, %g0
  88. saved
  89. be,pn %xcc, 1f
  90. and %g1, TSTATE_CWP, %g1
  91. retry
  92. 1: mov FAULT_CODE_WRITE | FAULT_CODE_DTLB | FAULT_CODE_WINFIXUP, %g4
  93. stb %g4, [%g6 + TI_FAULT_CODE]
  94. stx %g5, [%g6 + TI_FAULT_ADDR]
  95. wrpr %g1, %cwp
  96. ba,pt %xcc, etrap
  97. rd %pc, %g7
  98. call do_sparc64_fault
  99. add %sp, PTREGS_OFF, %o0
  100. ba,a,pt %xcc, rtrap
  101. winfix_mna:
  102. andn %g3, 0x7f, %g3
  103. add %g3, 0x78, %g3
  104. wrpr %g3, %tnpc
  105. done
  106. fill_fixup_mna:
  107. rdpr %tstate, %g1
  108. and %g1, TSTATE_CWP, %g1
  109. wrpr %g1, %cwp
  110. ba,pt %xcc, etrap
  111. rd %pc, %g7
  112. sethi %hi(tlb_type), %g1
  113. lduw [%g1 + %lo(tlb_type)], %g1
  114. cmp %g1, 3
  115. bne,pt %icc, 1f
  116. add %sp, PTREGS_OFF, %o0
  117. mov %l4, %o2
  118. call sun4v_do_mna
  119. mov %l5, %o1
  120. ba,a,pt %xcc, rtrap
  121. 1: mov %l4, %o1
  122. mov %l5, %o2
  123. call mem_address_unaligned
  124. nop
  125. ba,a,pt %xcc, rtrap
  126. winfix_dax:
  127. andn %g3, 0x7f, %g3
  128. add %g3, 0x74, %g3
  129. wrpr %g3, %tnpc
  130. done
  131. fill_fixup_dax:
  132. rdpr %tstate, %g1
  133. and %g1, TSTATE_CWP, %g1
  134. wrpr %g1, %cwp
  135. ba,pt %xcc, etrap
  136. rd %pc, %g7
  137. sethi %hi(tlb_type), %g1
  138. mov %l4, %o1
  139. lduw [%g1 + %lo(tlb_type)], %g1
  140. mov %l5, %o2
  141. cmp %g1, 3
  142. bne,pt %icc, 1f
  143. add %sp, PTREGS_OFF, %o0
  144. call sun4v_data_access_exception
  145. nop
  146. ba,a,pt %xcc, rtrap
  147. nop
  148. 1: call spitfire_data_access_exception
  149. nop
  150. ba,a,pt %xcc, rtrap
  151. nop