trampoline_64.S 9.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * trampoline.S: Jump start slave processors on sparc64.
  4. *
  5. * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
  6. */
  7. #include <linux/pgtable.h>
  8. #include <asm/head.h>
  9. #include <asm/asi.h>
  10. #include <asm/lsu.h>
  11. #include <asm/dcr.h>
  12. #include <asm/dcu.h>
  13. #include <asm/pstate.h>
  14. #include <asm/page.h>
  15. #include <asm/spitfire.h>
  16. #include <asm/processor.h>
  17. #include <asm/thread_info.h>
  18. #include <asm/mmu.h>
  19. #include <asm/hypervisor.h>
  20. #include <asm/cpudata.h>
  21. .data
  22. .align 8
  23. call_method:
  24. .asciz "call-method"
  25. .align 8
  26. itlb_load:
  27. .asciz "SUNW,itlb-load"
  28. .align 8
  29. dtlb_load:
  30. .asciz "SUNW,dtlb-load"
  31. #define TRAMP_STACK_SIZE 1024
  32. .align 16
  33. tramp_stack:
  34. .skip TRAMP_STACK_SIZE
  35. .align 8
  36. .globl sparc64_cpu_startup, sparc64_cpu_startup_end
  37. sparc64_cpu_startup:
  38. BRANCH_IF_SUN4V(g1, niagara_startup)
  39. BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
  40. BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
  41. ba,pt %xcc, spitfire_startup
  42. nop
  43. cheetah_plus_startup:
  44. /* Preserve OBP chosen DCU and DCR register settings. */
  45. ba,pt %xcc, cheetah_generic_startup
  46. nop
  47. cheetah_startup:
  48. mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
  49. wr %g1, %asr18
  50. sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
  51. or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
  52. sllx %g5, 32, %g5
  53. or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
  54. stxa %g5, [%g0] ASI_DCU_CONTROL_REG
  55. membar #Sync
  56. /* fallthru */
  57. cheetah_generic_startup:
  58. mov TSB_EXTENSION_P, %g3
  59. stxa %g0, [%g3] ASI_DMMU
  60. stxa %g0, [%g3] ASI_IMMU
  61. membar #Sync
  62. mov TSB_EXTENSION_S, %g3
  63. stxa %g0, [%g3] ASI_DMMU
  64. membar #Sync
  65. mov TSB_EXTENSION_N, %g3
  66. stxa %g0, [%g3] ASI_DMMU
  67. stxa %g0, [%g3] ASI_IMMU
  68. membar #Sync
  69. /* fallthru */
  70. niagara_startup:
  71. /* Disable STICK_INT interrupts. */
  72. sethi %hi(0x80000000), %g5
  73. sllx %g5, 32, %g5
  74. wr %g5, %asr25
  75. ba,pt %xcc, startup_continue
  76. nop
  77. spitfire_startup:
  78. mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
  79. stxa %g1, [%g0] ASI_LSU_CONTROL
  80. membar #Sync
  81. startup_continue:
  82. mov %o0, %l0
  83. BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
  84. sethi %hi(0x80000000), %g2
  85. sllx %g2, 32, %g2
  86. wr %g2, 0, %tick_cmpr
  87. /* Call OBP by hand to lock KERNBASE into i/d tlbs.
  88. * We lock 'num_kernel_image_mappings' consequetive entries.
  89. */
  90. sethi %hi(prom_entry_lock), %g2
  91. 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
  92. brnz,pn %g1, 1b
  93. nop
  94. /* Get onto temporary stack which will be in the locked
  95. * kernel image.
  96. */
  97. sethi %hi(tramp_stack), %g1
  98. or %g1, %lo(tramp_stack), %g1
  99. add %g1, TRAMP_STACK_SIZE, %g1
  100. sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp
  101. flushw
  102. /* Setup the loop variables:
  103. * %l3: VADDR base
  104. * %l4: TTE base
  105. * %l5: Loop iterator, iterates from 0 to 'num_kernel_image_mappings'
  106. * %l6: Number of TTE entries to map
  107. * %l7: Highest TTE entry number, we count down
  108. */
  109. sethi %hi(KERNBASE), %l3
  110. sethi %hi(kern_locked_tte_data), %l4
  111. ldx [%l4 + %lo(kern_locked_tte_data)], %l4
  112. clr %l5
  113. sethi %hi(num_kernel_image_mappings), %l6
  114. lduw [%l6 + %lo(num_kernel_image_mappings)], %l6
  115. mov 15, %l7
  116. BRANCH_IF_ANY_CHEETAH(g1,g5,2f)
  117. mov 63, %l7
  118. 2:
  119. 3:
  120. /* Lock into I-MMU */
  121. sethi %hi(call_method), %g2
  122. or %g2, %lo(call_method), %g2
  123. stx %g2, [%sp + 2047 + 128 + 0x00]
  124. mov 5, %g2
  125. stx %g2, [%sp + 2047 + 128 + 0x08]
  126. mov 1, %g2
  127. stx %g2, [%sp + 2047 + 128 + 0x10]
  128. sethi %hi(itlb_load), %g2
  129. or %g2, %lo(itlb_load), %g2
  130. stx %g2, [%sp + 2047 + 128 + 0x18]
  131. sethi %hi(prom_mmu_ihandle_cache), %g2
  132. lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
  133. stx %g2, [%sp + 2047 + 128 + 0x20]
  134. /* Each TTE maps 4MB, convert index to offset. */
  135. sllx %l5, 22, %g1
  136. add %l3, %g1, %g2
  137. stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
  138. add %l4, %g1, %g2
  139. stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE
  140. /* TTE index is highest minus loop index. */
  141. sub %l7, %l5, %g2
  142. stx %g2, [%sp + 2047 + 128 + 0x38]
  143. sethi %hi(p1275buf), %g2
  144. or %g2, %lo(p1275buf), %g2
  145. ldx [%g2 + 0x08], %o1
  146. call %o1
  147. add %sp, (2047 + 128), %o0
  148. /* Lock into D-MMU */
  149. sethi %hi(call_method), %g2
  150. or %g2, %lo(call_method), %g2
  151. stx %g2, [%sp + 2047 + 128 + 0x00]
  152. mov 5, %g2
  153. stx %g2, [%sp + 2047 + 128 + 0x08]
  154. mov 1, %g2
  155. stx %g2, [%sp + 2047 + 128 + 0x10]
  156. sethi %hi(dtlb_load), %g2
  157. or %g2, %lo(dtlb_load), %g2
  158. stx %g2, [%sp + 2047 + 128 + 0x18]
  159. sethi %hi(prom_mmu_ihandle_cache), %g2
  160. lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
  161. stx %g2, [%sp + 2047 + 128 + 0x20]
  162. /* Each TTE maps 4MB, convert index to offset. */
  163. sllx %l5, 22, %g1
  164. add %l3, %g1, %g2
  165. stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
  166. add %l4, %g1, %g2
  167. stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE
  168. /* TTE index is highest minus loop index. */
  169. sub %l7, %l5, %g2
  170. stx %g2, [%sp + 2047 + 128 + 0x38]
  171. sethi %hi(p1275buf), %g2
  172. or %g2, %lo(p1275buf), %g2
  173. ldx [%g2 + 0x08], %o1
  174. call %o1
  175. add %sp, (2047 + 128), %o0
  176. add %l5, 1, %l5
  177. cmp %l5, %l6
  178. bne,pt %xcc, 3b
  179. nop
  180. sethi %hi(prom_entry_lock), %g2
  181. stb %g0, [%g2 + %lo(prom_entry_lock)]
  182. ba,pt %xcc, after_lock_tlb
  183. nop
  184. niagara_lock_tlb:
  185. sethi %hi(KERNBASE), %l3
  186. sethi %hi(kern_locked_tte_data), %l4
  187. ldx [%l4 + %lo(kern_locked_tte_data)], %l4
  188. clr %l5
  189. sethi %hi(num_kernel_image_mappings), %l6
  190. lduw [%l6 + %lo(num_kernel_image_mappings)], %l6
  191. 1:
  192. mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
  193. sllx %l5, 22, %g2
  194. add %l3, %g2, %o0
  195. clr %o1
  196. add %l4, %g2, %o2
  197. mov HV_MMU_IMMU, %o3
  198. ta HV_FAST_TRAP
  199. mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
  200. sllx %l5, 22, %g2
  201. add %l3, %g2, %o0
  202. clr %o1
  203. add %l4, %g2, %o2
  204. mov HV_MMU_DMMU, %o3
  205. ta HV_FAST_TRAP
  206. add %l5, 1, %l5
  207. cmp %l5, %l6
  208. bne,pt %xcc, 1b
  209. nop
  210. after_lock_tlb:
  211. wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
  212. wr %g0, 0, %fprs
  213. wr %g0, ASI_P, %asi
  214. mov PRIMARY_CONTEXT, %g7
  215. 661: stxa %g0, [%g7] ASI_DMMU
  216. .section .sun4v_1insn_patch, "ax"
  217. .word 661b
  218. stxa %g0, [%g7] ASI_MMU
  219. .previous
  220. membar #Sync
  221. mov SECONDARY_CONTEXT, %g7
  222. 661: stxa %g0, [%g7] ASI_DMMU
  223. .section .sun4v_1insn_patch, "ax"
  224. .word 661b
  225. stxa %g0, [%g7] ASI_MMU
  226. .previous
  227. membar #Sync
  228. /* Everything we do here, until we properly take over the
  229. * trap table, must be done with extreme care. We cannot
  230. * make any references to %g6 (current thread pointer),
  231. * %g4 (current task pointer), or %g5 (base of current cpu's
  232. * per-cpu area) until we properly take over the trap table
  233. * from the firmware and hypervisor.
  234. *
  235. * Get onto temporary stack which is in the locked kernel image.
  236. */
  237. sethi %hi(tramp_stack), %g1
  238. or %g1, %lo(tramp_stack), %g1
  239. add %g1, TRAMP_STACK_SIZE, %g1
  240. sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp
  241. mov 0, %fp
  242. /* Put garbage in these registers to trap any access to them. */
  243. set 0xdeadbeef, %g4
  244. set 0xdeadbeef, %g5
  245. set 0xdeadbeef, %g6
  246. call init_irqwork_curcpu
  247. nop
  248. sethi %hi(tlb_type), %g3
  249. lduw [%g3 + %lo(tlb_type)], %g2
  250. cmp %g2, 3
  251. bne,pt %icc, 1f
  252. nop
  253. call hard_smp_processor_id
  254. nop
  255. call sun4v_register_mondo_queues
  256. nop
  257. 1: call init_cur_cpu_trap
  258. ldx [%l0], %o0
  259. /* Start using proper page size encodings in ctx register. */
  260. sethi %hi(sparc64_kern_pri_context), %g3
  261. ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
  262. mov PRIMARY_CONTEXT, %g1
  263. 661: stxa %g2, [%g1] ASI_DMMU
  264. .section .sun4v_1insn_patch, "ax"
  265. .word 661b
  266. stxa %g2, [%g1] ASI_MMU
  267. .previous
  268. membar #Sync
  269. wrpr %g0, 0, %wstate
  270. sethi %hi(prom_entry_lock), %g2
  271. 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
  272. brnz,pn %g1, 1b
  273. nop
  274. /* As a hack, put &init_thread_union into %g6.
  275. * prom_world() loads from here to restore the %asi
  276. * register.
  277. */
  278. sethi %hi(init_thread_union), %g6
  279. or %g6, %lo(init_thread_union), %g6
  280. sethi %hi(is_sun4v), %o0
  281. lduw [%o0 + %lo(is_sun4v)], %o0
  282. brz,pt %o0, 2f
  283. nop
  284. TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
  285. add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
  286. stxa %g2, [%g0] ASI_SCRATCHPAD
  287. /* Compute physical address:
  288. *
  289. * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
  290. */
  291. sethi %hi(KERNBASE), %g3
  292. sub %g2, %g3, %g2
  293. sethi %hi(kern_base), %g3
  294. ldx [%g3 + %lo(kern_base)], %g3
  295. add %g2, %g3, %o1
  296. sethi %hi(sparc64_ttable_tl0), %o0
  297. set prom_set_trap_table_name, %g2
  298. stx %g2, [%sp + 2047 + 128 + 0x00]
  299. mov 2, %g2
  300. stx %g2, [%sp + 2047 + 128 + 0x08]
  301. mov 0, %g2
  302. stx %g2, [%sp + 2047 + 128 + 0x10]
  303. stx %o0, [%sp + 2047 + 128 + 0x18]
  304. stx %o1, [%sp + 2047 + 128 + 0x20]
  305. sethi %hi(p1275buf), %g2
  306. or %g2, %lo(p1275buf), %g2
  307. ldx [%g2 + 0x08], %o1
  308. call %o1
  309. add %sp, (2047 + 128), %o0
  310. ba,pt %xcc, 3f
  311. nop
  312. 2: sethi %hi(sparc64_ttable_tl0), %o0
  313. set prom_set_trap_table_name, %g2
  314. stx %g2, [%sp + 2047 + 128 + 0x00]
  315. mov 1, %g2
  316. stx %g2, [%sp + 2047 + 128 + 0x08]
  317. mov 0, %g2
  318. stx %g2, [%sp + 2047 + 128 + 0x10]
  319. stx %o0, [%sp + 2047 + 128 + 0x18]
  320. sethi %hi(p1275buf), %g2
  321. or %g2, %lo(p1275buf), %g2
  322. ldx [%g2 + 0x08], %o1
  323. call %o1
  324. add %sp, (2047 + 128), %o0
  325. 3: sethi %hi(prom_entry_lock), %g2
  326. stb %g0, [%g2 + %lo(prom_entry_lock)]
  327. ldx [%l0], %g6
  328. ldx [%g6 + TI_TASK], %g4
  329. mov 1, %g5
  330. sllx %g5, THREAD_SHIFT, %g5
  331. sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
  332. add %g6, %g5, %sp
  333. rdpr %pstate, %o1
  334. or %o1, PSTATE_IE, %o1
  335. wrpr %o1, 0, %pstate
  336. call smp_callin
  337. nop
  338. call cpu_panic
  339. nop
  340. 1: b,a,pt %xcc, 1b
  341. .align 8
  342. sparc64_cpu_startup_end: