trampoline_32.S 3.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * trampoline.S: SMP cpu boot-up trampoline code.
  4. *
  5. * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
  6. * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  7. */
  8. #include <asm/head.h>
  9. #include <asm/psr.h>
  10. #include <asm/page.h>
  11. #include <asm/asi.h>
  12. #include <asm/ptrace.h>
  13. #include <asm/vaddrs.h>
  14. #include <asm/contregs.h>
  15. #include <asm/thread_info.h>
  16. .globl sun4m_cpu_startup
  17. .globl sun4d_cpu_startup
  18. .align 4
  19. /* When we start up a cpu for the first time it enters this routine.
  20. * This initializes the chip from whatever state the prom left it
  21. * in and sets PIL in %psr to 15, no irqs.
  22. */
  23. sun4m_cpu_startup:
  24. cpu1_startup:
  25. sethi %hi(trapbase_cpu1), %g3
  26. b 1f
  27. or %g3, %lo(trapbase_cpu1), %g3
  28. cpu2_startup:
  29. sethi %hi(trapbase_cpu2), %g3
  30. b 1f
  31. or %g3, %lo(trapbase_cpu2), %g3
  32. cpu3_startup:
  33. sethi %hi(trapbase_cpu3), %g3
  34. b 1f
  35. or %g3, %lo(trapbase_cpu3), %g3
  36. 1:
  37. /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
  38. set (PSR_PIL | PSR_S | PSR_PS), %g1
  39. wr %g1, 0x0, %psr ! traps off though
  40. WRITE_PAUSE
  41. /* Our %wim is one behind CWP */
  42. mov 2, %g1
  43. wr %g1, 0x0, %wim
  44. WRITE_PAUSE
  45. /* This identifies "this cpu". */
  46. wr %g3, 0x0, %tbr
  47. WRITE_PAUSE
  48. /* Give ourselves a stack and curptr. */
  49. set current_set, %g5
  50. srl %g3, 10, %g4
  51. and %g4, 0xc, %g4
  52. ld [%g5 + %g4], %g6
  53. sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
  54. or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
  55. add %g6, %sp, %sp
  56. /* Turn on traps (PSR_ET). */
  57. rd %psr, %g1
  58. wr %g1, PSR_ET, %psr ! traps on
  59. WRITE_PAUSE
  60. /* Init our caches, etc. */
  61. set poke_srmmu, %g5
  62. ld [%g5], %g5
  63. call %g5
  64. nop
  65. /* Start this processor. */
  66. call smp_callin
  67. nop
  68. b,a smp_panic
  69. .text
  70. .align 4
  71. smp_panic:
  72. call cpu_panic
  73. nop
  74. /* CPUID in bootbus can be found at PA 0xff0140000 */
  75. #define SUN4D_BOOTBUS_CPUID 0xf0140000
  76. .align 4
  77. sun4d_cpu_startup:
  78. /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
  79. set (PSR_PIL | PSR_S | PSR_PS), %g1
  80. wr %g1, 0x0, %psr ! traps off though
  81. WRITE_PAUSE
  82. /* Our %wim is one behind CWP */
  83. mov 2, %g1
  84. wr %g1, 0x0, %wim
  85. WRITE_PAUSE
  86. /* Set tbr - we use just one trap table. */
  87. set trapbase, %g1
  88. wr %g1, 0x0, %tbr
  89. WRITE_PAUSE
  90. /* Get our CPU id out of bootbus */
  91. set SUN4D_BOOTBUS_CPUID, %g3
  92. lduba [%g3] ASI_M_CTL, %g3
  93. and %g3, 0xf8, %g3
  94. srl %g3, 3, %g1
  95. sta %g1, [%g0] ASI_M_VIKING_TMP1
  96. /* Give ourselves a stack and curptr. */
  97. set current_set, %g5
  98. srl %g3, 1, %g4
  99. ld [%g5 + %g4], %g6
  100. sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
  101. or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
  102. add %g6, %sp, %sp
  103. /* Turn on traps (PSR_ET). */
  104. rd %psr, %g1
  105. wr %g1, PSR_ET, %psr ! traps on
  106. WRITE_PAUSE
  107. /* Init our caches, etc. */
  108. set poke_srmmu, %g5
  109. ld [%g5], %g5
  110. call %g5
  111. nop
  112. /* Start this processor. */
  113. call smp_callin
  114. nop
  115. b,a smp_panic
  116. .align 4
  117. .global leon_smp_cpu_startup, smp_penguin_ctable
  118. leon_smp_cpu_startup:
  119. set smp_penguin_ctable,%g1
  120. ld [%g1+4],%g1
  121. srl %g1,4,%g1
  122. set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */
  123. sta %g1, [%g5] ASI_LEON_MMUREGS
  124. /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
  125. set (PSR_PIL | PSR_S | PSR_PS), %g1
  126. wr %g1, 0x0, %psr ! traps off though
  127. WRITE_PAUSE
  128. /* Our %wim is one behind CWP */
  129. mov 2, %g1
  130. wr %g1, 0x0, %wim
  131. WRITE_PAUSE
  132. /* Set tbr - we use just one trap table. */
  133. set trapbase, %g1
  134. wr %g1, 0x0, %tbr
  135. WRITE_PAUSE
  136. /* Get our CPU id */
  137. rd %asr17,%g3
  138. /* Give ourselves a stack and curptr. */
  139. set current_set, %g5
  140. srl %g3, 28, %g4
  141. sll %g4, 2, %g4
  142. ld [%g5 + %g4], %g6
  143. sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
  144. or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
  145. add %g6, %sp, %sp
  146. /* Turn on traps (PSR_ET). */
  147. rd %psr, %g1
  148. wr %g1, PSR_ET, %psr ! traps on
  149. WRITE_PAUSE
  150. /* Init our caches, etc. */
  151. set poke_srmmu, %g5
  152. ld [%g5], %g5
  153. call %g5
  154. nop
  155. /* Start this processor. */
  156. call smp_callin
  157. nop
  158. b,a smp_panic