time_32.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* linux/arch/sparc/kernel/time.c
  3. *
  4. * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
  5. * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
  6. *
  7. * Chris Davis (cdavis@cois.on.ca) 03/27/1998
  8. * Added support for the intersil on the sun4/4200
  9. *
  10. * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
  11. * Support for MicroSPARC-IIep, PCI CPU.
  12. *
  13. * This file handles the Sparc specific time handling details.
  14. *
  15. * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
  16. * "A Kernel Model for Precision Timekeeping" by Dave Mills
  17. */
  18. #include <linux/errno.h>
  19. #include <linux/module.h>
  20. #include <linux/sched.h>
  21. #include <linux/kernel.h>
  22. #include <linux/param.h>
  23. #include <linux/string.h>
  24. #include <linux/mm.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/time.h>
  27. #include <linux/rtc/m48t59.h>
  28. #include <linux/timex.h>
  29. #include <linux/clocksource.h>
  30. #include <linux/clockchips.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/ioport.h>
  34. #include <linux/profile.h>
  35. #include <linux/of.h>
  36. #include <linux/of_device.h>
  37. #include <linux/platform_device.h>
  38. #include <asm/mc146818rtc.h>
  39. #include <asm/oplib.h>
  40. #include <asm/timex.h>
  41. #include <asm/timer.h>
  42. #include <asm/irq.h>
  43. #include <asm/io.h>
  44. #include <asm/idprom.h>
  45. #include <asm/page.h>
  46. #include <asm/pcic.h>
  47. #include <asm/irq_regs.h>
  48. #include <asm/setup.h>
  49. #include "kernel.h"
  50. #include "irq.h"
  51. static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
  52. static __volatile__ u64 timer_cs_internal_counter = 0;
  53. static char timer_cs_enabled = 0;
  54. static struct clock_event_device timer_ce;
  55. static char timer_ce_enabled = 0;
  56. #ifdef CONFIG_SMP
  57. DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
  58. #endif
  59. DEFINE_SPINLOCK(rtc_lock);
  60. EXPORT_SYMBOL(rtc_lock);
  61. unsigned long profile_pc(struct pt_regs *regs)
  62. {
  63. extern char __copy_user_begin[], __copy_user_end[];
  64. extern char __bzero_begin[], __bzero_end[];
  65. unsigned long pc = regs->pc;
  66. if (in_lock_functions(pc) ||
  67. (pc >= (unsigned long) __copy_user_begin &&
  68. pc < (unsigned long) __copy_user_end) ||
  69. (pc >= (unsigned long) __bzero_begin &&
  70. pc < (unsigned long) __bzero_end))
  71. pc = regs->u_regs[UREG_RETPC];
  72. return pc;
  73. }
  74. EXPORT_SYMBOL(profile_pc);
  75. volatile u32 __iomem *master_l10_counter;
  76. irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
  77. {
  78. if (timer_cs_enabled) {
  79. write_seqlock(&timer_cs_lock);
  80. timer_cs_internal_counter++;
  81. sparc_config.clear_clock_irq();
  82. write_sequnlock(&timer_cs_lock);
  83. } else {
  84. sparc_config.clear_clock_irq();
  85. }
  86. if (timer_ce_enabled)
  87. timer_ce.event_handler(&timer_ce);
  88. return IRQ_HANDLED;
  89. }
  90. static int timer_ce_shutdown(struct clock_event_device *evt)
  91. {
  92. timer_ce_enabled = 0;
  93. smp_mb();
  94. return 0;
  95. }
  96. static int timer_ce_set_periodic(struct clock_event_device *evt)
  97. {
  98. timer_ce_enabled = 1;
  99. smp_mb();
  100. return 0;
  101. }
  102. static __init void setup_timer_ce(void)
  103. {
  104. struct clock_event_device *ce = &timer_ce;
  105. BUG_ON(smp_processor_id() != boot_cpu_id);
  106. ce->name = "timer_ce";
  107. ce->rating = 100;
  108. ce->features = CLOCK_EVT_FEAT_PERIODIC;
  109. ce->set_state_shutdown = timer_ce_shutdown;
  110. ce->set_state_periodic = timer_ce_set_periodic;
  111. ce->tick_resume = timer_ce_set_periodic;
  112. ce->cpumask = cpu_possible_mask;
  113. ce->shift = 32;
  114. ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
  115. ce->shift);
  116. clockevents_register_device(ce);
  117. }
  118. static unsigned int sbus_cycles_offset(void)
  119. {
  120. u32 val, offset;
  121. val = sbus_readl(master_l10_counter);
  122. offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
  123. /* Limit hit? */
  124. if (val & TIMER_LIMIT_BIT)
  125. offset += sparc_config.cs_period;
  126. return offset;
  127. }
  128. static u64 timer_cs_read(struct clocksource *cs)
  129. {
  130. unsigned int seq, offset;
  131. u64 cycles;
  132. do {
  133. seq = read_seqbegin(&timer_cs_lock);
  134. cycles = timer_cs_internal_counter;
  135. offset = sparc_config.get_cycles_offset();
  136. } while (read_seqretry(&timer_cs_lock, seq));
  137. /* Count absolute cycles */
  138. cycles *= sparc_config.cs_period;
  139. cycles += offset;
  140. return cycles;
  141. }
  142. static struct clocksource timer_cs = {
  143. .name = "timer_cs",
  144. .rating = 100,
  145. .read = timer_cs_read,
  146. .mask = CLOCKSOURCE_MASK(64),
  147. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  148. };
  149. static __init int setup_timer_cs(void)
  150. {
  151. timer_cs_enabled = 1;
  152. return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
  153. }
  154. #ifdef CONFIG_SMP
  155. static int percpu_ce_shutdown(struct clock_event_device *evt)
  156. {
  157. int cpu = cpumask_first(evt->cpumask);
  158. sparc_config.load_profile_irq(cpu, 0);
  159. return 0;
  160. }
  161. static int percpu_ce_set_periodic(struct clock_event_device *evt)
  162. {
  163. int cpu = cpumask_first(evt->cpumask);
  164. sparc_config.load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
  165. return 0;
  166. }
  167. static int percpu_ce_set_next_event(unsigned long delta,
  168. struct clock_event_device *evt)
  169. {
  170. int cpu = cpumask_first(evt->cpumask);
  171. unsigned int next = (unsigned int)delta;
  172. sparc_config.load_profile_irq(cpu, next);
  173. return 0;
  174. }
  175. void register_percpu_ce(int cpu)
  176. {
  177. struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
  178. unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
  179. if (sparc_config.features & FEAT_L14_ONESHOT)
  180. features |= CLOCK_EVT_FEAT_ONESHOT;
  181. ce->name = "percpu_ce";
  182. ce->rating = 200;
  183. ce->features = features;
  184. ce->set_state_shutdown = percpu_ce_shutdown;
  185. ce->set_state_periodic = percpu_ce_set_periodic;
  186. ce->set_state_oneshot = percpu_ce_shutdown;
  187. ce->set_next_event = percpu_ce_set_next_event;
  188. ce->cpumask = cpumask_of(cpu);
  189. ce->shift = 32;
  190. ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
  191. ce->shift);
  192. ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce);
  193. ce->max_delta_ticks = (unsigned long)sparc_config.clock_rate;
  194. ce->min_delta_ns = clockevent_delta2ns(100, ce);
  195. ce->min_delta_ticks = 100;
  196. clockevents_register_device(ce);
  197. }
  198. #endif
  199. static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
  200. {
  201. struct platform_device *pdev = to_platform_device(dev);
  202. struct m48t59_plat_data *pdata = pdev->dev.platform_data;
  203. return readb(pdata->ioaddr + ofs);
  204. }
  205. static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
  206. {
  207. struct platform_device *pdev = to_platform_device(dev);
  208. struct m48t59_plat_data *pdata = pdev->dev.platform_data;
  209. writeb(val, pdata->ioaddr + ofs);
  210. }
  211. static struct m48t59_plat_data m48t59_data = {
  212. .read_byte = mostek_read_byte,
  213. .write_byte = mostek_write_byte,
  214. };
  215. /* resource is set at runtime */
  216. static struct platform_device m48t59_rtc = {
  217. .name = "rtc-m48t59",
  218. .id = 0,
  219. .num_resources = 1,
  220. .dev = {
  221. .platform_data = &m48t59_data,
  222. },
  223. };
  224. static int clock_probe(struct platform_device *op)
  225. {
  226. struct device_node *dp = op->dev.of_node;
  227. const char *model = of_get_property(dp, "model", NULL);
  228. if (!model)
  229. return -ENODEV;
  230. /* Only the primary RTC has an address property */
  231. if (!of_find_property(dp, "address", NULL))
  232. return -ENODEV;
  233. m48t59_rtc.resource = &op->resource[0];
  234. if (!strcmp(model, "mk48t02")) {
  235. /* Map the clock register io area read-only */
  236. m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
  237. 2048, "rtc-m48t59");
  238. m48t59_data.type = M48T59RTC_TYPE_M48T02;
  239. } else if (!strcmp(model, "mk48t08")) {
  240. m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
  241. 8192, "rtc-m48t59");
  242. m48t59_data.type = M48T59RTC_TYPE_M48T08;
  243. } else
  244. return -ENODEV;
  245. if (platform_device_register(&m48t59_rtc) < 0)
  246. printk(KERN_ERR "Registering RTC device failed\n");
  247. return 0;
  248. }
  249. static const struct of_device_id clock_match[] = {
  250. {
  251. .name = "eeprom",
  252. },
  253. {},
  254. };
  255. static struct platform_driver clock_driver = {
  256. .probe = clock_probe,
  257. .driver = {
  258. .name = "rtc",
  259. .of_match_table = clock_match,
  260. },
  261. };
  262. /* Probe for the mostek real time clock chip. */
  263. static int __init clock_init(void)
  264. {
  265. return platform_driver_register(&clock_driver);
  266. }
  267. /* Must be after subsys_initcall() so that busses are probed. Must
  268. * be before device_initcall() because things like the RTC driver
  269. * need to see the clock registers.
  270. */
  271. fs_initcall(clock_init);
  272. static void __init sparc32_late_time_init(void)
  273. {
  274. if (sparc_config.features & FEAT_L10_CLOCKEVENT)
  275. setup_timer_ce();
  276. if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
  277. setup_timer_cs();
  278. #ifdef CONFIG_SMP
  279. register_percpu_ce(smp_processor_id());
  280. #endif
  281. }
  282. static void __init sbus_time_init(void)
  283. {
  284. sparc_config.get_cycles_offset = sbus_cycles_offset;
  285. sparc_config.init_timers();
  286. }
  287. void __init time_init(void)
  288. {
  289. sparc_config.features = 0;
  290. late_time_init = sparc32_late_time_init;
  291. if (pcic_present())
  292. pci_time_init();
  293. else
  294. sbus_time_init();
  295. }