sun4m_smp.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * sun4m SMP support.
  4. *
  5. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  6. */
  7. #include <linux/clockchips.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/profile.h>
  10. #include <linux/delay.h>
  11. #include <linux/sched/mm.h>
  12. #include <linux/cpu.h>
  13. #include <asm/cacheflush.h>
  14. #include <asm/switch_to.h>
  15. #include <asm/tlbflush.h>
  16. #include <asm/timer.h>
  17. #include <asm/oplib.h>
  18. #include "irq.h"
  19. #include "kernel.h"
  20. #define IRQ_IPI_SINGLE 12
  21. #define IRQ_IPI_MASK 13
  22. #define IRQ_IPI_RESCHED 14
  23. #define IRQ_CROSS_CALL 15
  24. static inline unsigned long
  25. swap_ulong(volatile unsigned long *ptr, unsigned long val)
  26. {
  27. __asm__ __volatile__("swap [%1], %0\n\t" :
  28. "=&r" (val), "=&r" (ptr) :
  29. "0" (val), "1" (ptr));
  30. return val;
  31. }
  32. void sun4m_cpu_pre_starting(void *arg)
  33. {
  34. }
  35. void sun4m_cpu_pre_online(void *arg)
  36. {
  37. int cpuid = hard_smp_processor_id();
  38. /* Allow master to continue. The master will then give us the
  39. * go-ahead by setting the smp_commenced_mask and will wait without
  40. * timeouts until our setup is completed fully (signified by
  41. * our bit being set in the cpu_online_mask).
  42. */
  43. swap_ulong(&cpu_callin_map[cpuid], 1);
  44. /* XXX: What's up with all the flushes? */
  45. local_ops->cache_all();
  46. local_ops->tlb_all();
  47. /* Fix idle thread fields. */
  48. __asm__ __volatile__("ld [%0], %%g6\n\t"
  49. : : "r" (&current_set[cpuid])
  50. : "memory" /* paranoid */);
  51. /* Attach to the address space of init_task. */
  52. mmgrab(&init_mm);
  53. current->active_mm = &init_mm;
  54. while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
  55. mb();
  56. }
  57. /*
  58. * Cycle through the processors asking the PROM to start each one.
  59. */
  60. void __init smp4m_boot_cpus(void)
  61. {
  62. sun4m_unmask_profile_irq();
  63. local_ops->cache_all();
  64. }
  65. int smp4m_boot_one_cpu(int i, struct task_struct *idle)
  66. {
  67. unsigned long *entry = &sun4m_cpu_startup;
  68. int timeout;
  69. int cpu_node;
  70. cpu_find_by_mid(i, &cpu_node);
  71. current_set[i] = task_thread_info(idle);
  72. /* See trampoline.S for details... */
  73. entry += ((i - 1) * 3);
  74. /*
  75. * Initialize the contexts table
  76. * Since the call to prom_startcpu() trashes the structure,
  77. * we need to re-initialize it for each cpu
  78. */
  79. smp_penguin_ctable.which_io = 0;
  80. smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
  81. smp_penguin_ctable.reg_size = 0;
  82. /* whirrr, whirrr, whirrrrrrrrr... */
  83. printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
  84. local_ops->cache_all();
  85. prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
  86. /* wheee... it's going... */
  87. for (timeout = 0; timeout < 10000; timeout++) {
  88. if (cpu_callin_map[i])
  89. break;
  90. udelay(200);
  91. }
  92. if (!(cpu_callin_map[i])) {
  93. printk(KERN_ERR "Processor %d is stuck.\n", i);
  94. return -ENODEV;
  95. }
  96. local_ops->cache_all();
  97. return 0;
  98. }
  99. void __init smp4m_smp_done(void)
  100. {
  101. int i, first;
  102. int *prev;
  103. /* setup cpu list for irq rotation */
  104. first = 0;
  105. prev = &first;
  106. for_each_online_cpu(i) {
  107. *prev = i;
  108. prev = &cpu_data(i).next;
  109. }
  110. *prev = first;
  111. local_ops->cache_all();
  112. /* Ok, they are spinning and ready to go. */
  113. }
  114. static void sun4m_send_ipi(int cpu, int level)
  115. {
  116. sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set);
  117. }
  118. static void sun4m_ipi_resched(int cpu)
  119. {
  120. sun4m_send_ipi(cpu, IRQ_IPI_RESCHED);
  121. }
  122. static void sun4m_ipi_single(int cpu)
  123. {
  124. sun4m_send_ipi(cpu, IRQ_IPI_SINGLE);
  125. }
  126. static void sun4m_ipi_mask_one(int cpu)
  127. {
  128. sun4m_send_ipi(cpu, IRQ_IPI_MASK);
  129. }
  130. static struct smp_funcall {
  131. smpfunc_t func;
  132. unsigned long arg1;
  133. unsigned long arg2;
  134. unsigned long arg3;
  135. unsigned long arg4;
  136. unsigned long arg5;
  137. unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
  138. unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
  139. } ccall_info;
  140. static DEFINE_SPINLOCK(cross_call_lock);
  141. /* Cross calls must be serialized, at least currently. */
  142. static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
  143. unsigned long arg2, unsigned long arg3,
  144. unsigned long arg4)
  145. {
  146. register int ncpus = SUN4M_NCPUS;
  147. unsigned long flags;
  148. spin_lock_irqsave(&cross_call_lock, flags);
  149. /* Init function glue. */
  150. ccall_info.func = func;
  151. ccall_info.arg1 = arg1;
  152. ccall_info.arg2 = arg2;
  153. ccall_info.arg3 = arg3;
  154. ccall_info.arg4 = arg4;
  155. ccall_info.arg5 = 0;
  156. /* Init receive/complete mapping, plus fire the IPI's off. */
  157. {
  158. register int i;
  159. cpumask_clear_cpu(smp_processor_id(), &mask);
  160. cpumask_and(&mask, cpu_online_mask, &mask);
  161. for (i = 0; i < ncpus; i++) {
  162. if (cpumask_test_cpu(i, &mask)) {
  163. ccall_info.processors_in[i] = 0;
  164. ccall_info.processors_out[i] = 0;
  165. sun4m_send_ipi(i, IRQ_CROSS_CALL);
  166. } else {
  167. ccall_info.processors_in[i] = 1;
  168. ccall_info.processors_out[i] = 1;
  169. }
  170. }
  171. }
  172. {
  173. register int i;
  174. i = 0;
  175. do {
  176. if (!cpumask_test_cpu(i, &mask))
  177. continue;
  178. while (!ccall_info.processors_in[i])
  179. barrier();
  180. } while (++i < ncpus);
  181. i = 0;
  182. do {
  183. if (!cpumask_test_cpu(i, &mask))
  184. continue;
  185. while (!ccall_info.processors_out[i])
  186. barrier();
  187. } while (++i < ncpus);
  188. }
  189. spin_unlock_irqrestore(&cross_call_lock, flags);
  190. }
  191. /* Running cross calls. */
  192. void smp4m_cross_call_irq(void)
  193. {
  194. int i = smp_processor_id();
  195. ccall_info.processors_in[i] = 1;
  196. ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
  197. ccall_info.arg4, ccall_info.arg5);
  198. ccall_info.processors_out[i] = 1;
  199. }
  200. void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
  201. {
  202. struct pt_regs *old_regs;
  203. struct clock_event_device *ce;
  204. int cpu = smp_processor_id();
  205. old_regs = set_irq_regs(regs);
  206. ce = &per_cpu(sparc32_clockevent, cpu);
  207. if (clockevent_state_periodic(ce))
  208. sun4m_clear_profile_irq(cpu);
  209. else
  210. sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */
  211. irq_enter();
  212. ce->event_handler(ce);
  213. irq_exit();
  214. set_irq_regs(old_regs);
  215. }
  216. static const struct sparc32_ipi_ops sun4m_ipi_ops = {
  217. .cross_call = sun4m_cross_call,
  218. .resched = sun4m_ipi_resched,
  219. .single = sun4m_ipi_single,
  220. .mask_one = sun4m_ipi_mask_one,
  221. };
  222. void __init sun4m_init_smp(void)
  223. {
  224. sparc32_ipi_ops = &sun4m_ipi_ops;
  225. }