sun4d_irq.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SS1000/SC2000 interrupt handling.
  4. *
  5. * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  6. * Heavily based on arch/sparc/kernel/irq.c.
  7. */
  8. #include <linux/kernel_stat.h>
  9. #include <linux/slab.h>
  10. #include <linux/seq_file.h>
  11. #include <asm/timer.h>
  12. #include <asm/traps.h>
  13. #include <asm/irq.h>
  14. #include <asm/io.h>
  15. #include <asm/sbi.h>
  16. #include <asm/cacheflush.h>
  17. #include <asm/setup.h>
  18. #include <asm/oplib.h>
  19. #include "kernel.h"
  20. #include "irq.h"
  21. /* Sun4d interrupts fall roughly into two categories. SBUS and
  22. * cpu local. CPU local interrupts cover the timer interrupts
  23. * and whatnot, and we encode those as normal PILs between
  24. * 0 and 15.
  25. * SBUS interrupts are encodes as a combination of board, level and slot.
  26. */
  27. struct sun4d_handler_data {
  28. unsigned int cpuid; /* target cpu */
  29. unsigned int real_irq; /* interrupt level */
  30. };
  31. static unsigned int sun4d_encode_irq(int board, int lvl, int slot)
  32. {
  33. return (board + 1) << 5 | (lvl << 2) | slot;
  34. }
  35. struct sun4d_timer_regs {
  36. u32 l10_timer_limit;
  37. u32 l10_cur_countx;
  38. u32 l10_limit_noclear;
  39. u32 ctrl;
  40. u32 l10_cur_count;
  41. };
  42. static struct sun4d_timer_regs __iomem *sun4d_timers;
  43. #define SUN4D_TIMER_IRQ 10
  44. /* Specify which cpu handle interrupts from which board.
  45. * Index is board - value is cpu.
  46. */
  47. static unsigned char board_to_cpu[32];
  48. static int pil_to_sbus[] = {
  49. 0,
  50. 0,
  51. 1,
  52. 2,
  53. 0,
  54. 3,
  55. 0,
  56. 4,
  57. 0,
  58. 5,
  59. 0,
  60. 6,
  61. 0,
  62. 7,
  63. 0,
  64. 0,
  65. };
  66. /* Exported for sun4d_smp.c */
  67. DEFINE_SPINLOCK(sun4d_imsk_lock);
  68. /* SBUS interrupts are encoded integers including the board number
  69. * (plus one), the SBUS level, and the SBUS slot number. Sun4D
  70. * IRQ dispatch is done by:
  71. *
  72. * 1) Reading the BW local interrupt table in order to get the bus
  73. * interrupt mask.
  74. *
  75. * This table is indexed by SBUS interrupt level which can be
  76. * derived from the PIL we got interrupted on.
  77. *
  78. * 2) For each bus showing interrupt pending from #1, read the
  79. * SBI interrupt state register. This will indicate which slots
  80. * have interrupts pending for that SBUS interrupt level.
  81. *
  82. * 3) Call the genreric IRQ support.
  83. */
  84. static void sun4d_sbus_handler_irq(int sbusl)
  85. {
  86. unsigned int bus_mask;
  87. unsigned int sbino, slot;
  88. unsigned int sbil;
  89. bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff;
  90. bw_clear_intr_mask(sbusl, bus_mask);
  91. sbil = (sbusl << 2);
  92. /* Loop for each pending SBI */
  93. for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) {
  94. unsigned int idx, mask;
  95. if (!(bus_mask & 1))
  96. continue;
  97. /* XXX This seems to ACK the irq twice. acquire_sbi()
  98. * XXX uses swap, therefore this writes 0xf << sbil,
  99. * XXX then later release_sbi() will write the individual
  100. * XXX bits which were set again.
  101. */
  102. mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil);
  103. mask &= (0xf << sbil);
  104. /* Loop for each pending SBI slot */
  105. slot = (1 << sbil);
  106. for (idx = 0; mask != 0; idx++, slot <<= 1) {
  107. unsigned int pil;
  108. struct irq_bucket *p;
  109. if (!(mask & slot))
  110. continue;
  111. mask &= ~slot;
  112. pil = sun4d_encode_irq(sbino, sbusl, idx);
  113. p = irq_map[pil];
  114. while (p) {
  115. struct irq_bucket *next;
  116. next = p->next;
  117. generic_handle_irq(p->irq);
  118. p = next;
  119. }
  120. release_sbi(SBI2DEVID(sbino), slot);
  121. }
  122. }
  123. }
  124. void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs)
  125. {
  126. struct pt_regs *old_regs;
  127. /* SBUS IRQ level (1 - 7) */
  128. int sbusl = pil_to_sbus[pil];
  129. /* FIXME: Is this necessary?? */
  130. cc_get_ipen();
  131. cc_set_iclr(1 << pil);
  132. #ifdef CONFIG_SMP
  133. /*
  134. * Check IPI data structures after IRQ has been cleared. Hard and Soft
  135. * IRQ can happen at the same time, so both cases are always handled.
  136. */
  137. if (pil == SUN4D_IPI_IRQ)
  138. sun4d_ipi_interrupt();
  139. #endif
  140. old_regs = set_irq_regs(regs);
  141. irq_enter();
  142. if (sbusl == 0) {
  143. /* cpu interrupt */
  144. struct irq_bucket *p;
  145. p = irq_map[pil];
  146. while (p) {
  147. struct irq_bucket *next;
  148. next = p->next;
  149. generic_handle_irq(p->irq);
  150. p = next;
  151. }
  152. } else {
  153. /* SBUS interrupt */
  154. sun4d_sbus_handler_irq(sbusl);
  155. }
  156. irq_exit();
  157. set_irq_regs(old_regs);
  158. }
  159. static void sun4d_mask_irq(struct irq_data *data)
  160. {
  161. struct sun4d_handler_data *handler_data = irq_data_get_irq_handler_data(data);
  162. unsigned int real_irq;
  163. #ifdef CONFIG_SMP
  164. int cpuid = handler_data->cpuid;
  165. unsigned long flags;
  166. #endif
  167. real_irq = handler_data->real_irq;
  168. #ifdef CONFIG_SMP
  169. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  170. cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | (1 << real_irq));
  171. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  172. #else
  173. cc_set_imsk(cc_get_imsk() | (1 << real_irq));
  174. #endif
  175. }
  176. static void sun4d_unmask_irq(struct irq_data *data)
  177. {
  178. struct sun4d_handler_data *handler_data = irq_data_get_irq_handler_data(data);
  179. unsigned int real_irq;
  180. #ifdef CONFIG_SMP
  181. int cpuid = handler_data->cpuid;
  182. unsigned long flags;
  183. #endif
  184. real_irq = handler_data->real_irq;
  185. #ifdef CONFIG_SMP
  186. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  187. cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq));
  188. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  189. #else
  190. cc_set_imsk(cc_get_imsk() & ~(1 << real_irq));
  191. #endif
  192. }
  193. static unsigned int sun4d_startup_irq(struct irq_data *data)
  194. {
  195. irq_link(data->irq);
  196. sun4d_unmask_irq(data);
  197. return 0;
  198. }
  199. static void sun4d_shutdown_irq(struct irq_data *data)
  200. {
  201. sun4d_mask_irq(data);
  202. irq_unlink(data->irq);
  203. }
  204. static struct irq_chip sun4d_irq = {
  205. .name = "sun4d",
  206. .irq_startup = sun4d_startup_irq,
  207. .irq_shutdown = sun4d_shutdown_irq,
  208. .irq_unmask = sun4d_unmask_irq,
  209. .irq_mask = sun4d_mask_irq,
  210. };
  211. #ifdef CONFIG_SMP
  212. /* Setup IRQ distribution scheme. */
  213. void __init sun4d_distribute_irqs(void)
  214. {
  215. struct device_node *dp;
  216. int cpuid = cpu_logical_map(1);
  217. if (cpuid == -1)
  218. cpuid = cpu_logical_map(0);
  219. for_each_node_by_name(dp, "sbi") {
  220. int devid = of_getintprop_default(dp, "device-id", 0);
  221. int board = of_getintprop_default(dp, "board#", 0);
  222. board_to_cpu[board] = cpuid;
  223. set_sbi_tid(devid, cpuid << 3);
  224. }
  225. printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid);
  226. }
  227. #endif
  228. static void sun4d_clear_clock_irq(void)
  229. {
  230. sbus_readl(&sun4d_timers->l10_timer_limit);
  231. }
  232. static void sun4d_load_profile_irq(int cpu, unsigned int limit)
  233. {
  234. unsigned int value = limit ? timer_value(limit) : 0;
  235. bw_set_prof_limit(cpu, value);
  236. }
  237. static void __init sun4d_load_profile_irqs(void)
  238. {
  239. int cpu = 0, mid;
  240. while (!cpu_find_by_instance(cpu, NULL, &mid)) {
  241. sun4d_load_profile_irq(mid >> 3, 0);
  242. cpu++;
  243. }
  244. }
  245. static unsigned int _sun4d_build_device_irq(unsigned int real_irq,
  246. unsigned int pil,
  247. unsigned int board)
  248. {
  249. struct sun4d_handler_data *handler_data;
  250. unsigned int irq;
  251. irq = irq_alloc(real_irq, pil);
  252. if (irq == 0) {
  253. prom_printf("IRQ: allocate for %d %d %d failed\n",
  254. real_irq, pil, board);
  255. goto err_out;
  256. }
  257. handler_data = irq_get_handler_data(irq);
  258. if (unlikely(handler_data))
  259. goto err_out;
  260. handler_data = kzalloc(sizeof(struct sun4d_handler_data), GFP_ATOMIC);
  261. if (unlikely(!handler_data)) {
  262. prom_printf("IRQ: kzalloc(sun4d_handler_data) failed.\n");
  263. prom_halt();
  264. }
  265. handler_data->cpuid = board_to_cpu[board];
  266. handler_data->real_irq = real_irq;
  267. irq_set_chip_and_handler_name(irq, &sun4d_irq,
  268. handle_level_irq, "level");
  269. irq_set_handler_data(irq, handler_data);
  270. err_out:
  271. return irq;
  272. }
  273. static unsigned int sun4d_build_device_irq(struct platform_device *op,
  274. unsigned int real_irq)
  275. {
  276. struct device_node *dp = op->dev.of_node;
  277. struct device_node *board_parent, *bus = dp->parent;
  278. char *bus_connection;
  279. const struct linux_prom_registers *regs;
  280. unsigned int pil;
  281. unsigned int irq;
  282. int board, slot;
  283. int sbusl;
  284. irq = real_irq;
  285. while (bus) {
  286. if (of_node_name_eq(bus, "sbi")) {
  287. bus_connection = "io-unit";
  288. break;
  289. }
  290. if (of_node_name_eq(bus, "bootbus")) {
  291. bus_connection = "cpu-unit";
  292. break;
  293. }
  294. bus = bus->parent;
  295. }
  296. if (!bus)
  297. goto err_out;
  298. regs = of_get_property(dp, "reg", NULL);
  299. if (!regs)
  300. goto err_out;
  301. slot = regs->which_io;
  302. /*
  303. * If Bus nodes parent is not io-unit/cpu-unit or the io-unit/cpu-unit
  304. * lacks a "board#" property, something is very wrong.
  305. */
  306. if (!of_node_name_eq(bus->parent, bus_connection)) {
  307. printk(KERN_ERR "%pOF: Error, parent is not %s.\n",
  308. bus, bus_connection);
  309. goto err_out;
  310. }
  311. board_parent = bus->parent;
  312. board = of_getintprop_default(board_parent, "board#", -1);
  313. if (board == -1) {
  314. printk(KERN_ERR "%pOF: Error, lacks board# property.\n",
  315. board_parent);
  316. goto err_out;
  317. }
  318. sbusl = pil_to_sbus[real_irq];
  319. if (sbusl)
  320. pil = sun4d_encode_irq(board, sbusl, slot);
  321. else
  322. pil = real_irq;
  323. irq = _sun4d_build_device_irq(real_irq, pil, board);
  324. err_out:
  325. return irq;
  326. }
  327. static unsigned int sun4d_build_timer_irq(unsigned int board,
  328. unsigned int real_irq)
  329. {
  330. return _sun4d_build_device_irq(real_irq, real_irq, board);
  331. }
  332. static void __init sun4d_fixup_trap_table(void)
  333. {
  334. #ifdef CONFIG_SMP
  335. unsigned long flags;
  336. struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
  337. /* Adjust so that we jump directly to smp4d_ticker */
  338. lvl14_save[2] += smp4d_ticker - real_irq_entry;
  339. /* For SMP we use the level 14 ticker, however the bootup code
  340. * has copied the firmware's level 14 vector into the boot cpu's
  341. * trap table, we must fix this now or we get squashed.
  342. */
  343. local_irq_save(flags);
  344. patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
  345. trap_table->inst_one = lvl14_save[0];
  346. trap_table->inst_two = lvl14_save[1];
  347. trap_table->inst_three = lvl14_save[2];
  348. trap_table->inst_four = lvl14_save[3];
  349. local_ops->cache_all();
  350. local_irq_restore(flags);
  351. #endif
  352. }
  353. static void __init sun4d_init_timers(void)
  354. {
  355. struct device_node *dp;
  356. struct resource res;
  357. unsigned int irq;
  358. const u32 *reg;
  359. int err;
  360. int board;
  361. dp = of_find_node_by_name(NULL, "cpu-unit");
  362. if (!dp) {
  363. prom_printf("sun4d_init_timers: Unable to find cpu-unit\n");
  364. prom_halt();
  365. }
  366. /* Which cpu-unit we use is arbitrary, we can view the bootbus timer
  367. * registers via any cpu's mapping. The first 'reg' property is the
  368. * bootbus.
  369. */
  370. reg = of_get_property(dp, "reg", NULL);
  371. if (!reg) {
  372. prom_printf("sun4d_init_timers: No reg property\n");
  373. prom_halt();
  374. }
  375. board = of_getintprop_default(dp, "board#", -1);
  376. if (board == -1) {
  377. prom_printf("sun4d_init_timers: No board# property on cpu-unit\n");
  378. prom_halt();
  379. }
  380. of_node_put(dp);
  381. res.start = reg[1];
  382. res.end = reg[2] - 1;
  383. res.flags = reg[0] & 0xff;
  384. sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT,
  385. sizeof(struct sun4d_timer_regs), "user timer");
  386. if (!sun4d_timers) {
  387. prom_printf("sun4d_init_timers: Can't map timer regs\n");
  388. prom_halt();
  389. }
  390. #ifdef CONFIG_SMP
  391. sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
  392. #else
  393. sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
  394. sparc_config.features |= FEAT_L10_CLOCKEVENT;
  395. #endif
  396. sparc_config.features |= FEAT_L10_CLOCKSOURCE;
  397. sbus_writel(timer_value(sparc_config.cs_period),
  398. &sun4d_timers->l10_timer_limit);
  399. master_l10_counter = &sun4d_timers->l10_cur_count;
  400. irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
  401. err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
  402. if (err) {
  403. prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
  404. err);
  405. prom_halt();
  406. }
  407. sun4d_load_profile_irqs();
  408. sun4d_fixup_trap_table();
  409. }
  410. void __init sun4d_init_sbi_irq(void)
  411. {
  412. struct device_node *dp;
  413. int target_cpu;
  414. target_cpu = boot_cpu_id;
  415. for_each_node_by_name(dp, "sbi") {
  416. int devid = of_getintprop_default(dp, "device-id", 0);
  417. int board = of_getintprop_default(dp, "board#", 0);
  418. unsigned int mask;
  419. set_sbi_tid(devid, target_cpu << 3);
  420. board_to_cpu[board] = target_cpu;
  421. /* Get rid of pending irqs from PROM */
  422. mask = acquire_sbi(devid, 0xffffffff);
  423. if (mask) {
  424. printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n",
  425. mask, board);
  426. release_sbi(devid, mask);
  427. }
  428. }
  429. }
  430. void __init sun4d_init_IRQ(void)
  431. {
  432. local_irq_disable();
  433. sparc_config.init_timers = sun4d_init_timers;
  434. sparc_config.build_device_irq = sun4d_build_device_irq;
  435. sparc_config.clock_rate = SBUS_CLOCK_RATE;
  436. sparc_config.clear_clock_irq = sun4d_clear_clock_irq;
  437. sparc_config.load_profile_irq = sun4d_load_profile_irq;
  438. /* Cannot enable interrupts until OBP ticker is disabled. */
  439. }