setup_64.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/sparc64/kernel/setup.c
  4. *
  5. * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
  6. * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  7. */
  8. #include <linux/errno.h>
  9. #include <linux/sched.h>
  10. #include <linux/kernel.h>
  11. #include <linux/mm.h>
  12. #include <linux/stddef.h>
  13. #include <linux/unistd.h>
  14. #include <linux/ptrace.h>
  15. #include <asm/smp.h>
  16. #include <linux/user.h>
  17. #include <linux/screen_info.h>
  18. #include <linux/delay.h>
  19. #include <linux/fs.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/syscalls.h>
  22. #include <linux/kdev_t.h>
  23. #include <linux/major.h>
  24. #include <linux/string.h>
  25. #include <linux/init.h>
  26. #include <linux/inet.h>
  27. #include <linux/console.h>
  28. #include <linux/root_dev.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/cpu.h>
  31. #include <linux/initrd.h>
  32. #include <linux/module.h>
  33. #include <linux/start_kernel.h>
  34. #include <linux/memblock.h>
  35. #include <uapi/linux/mount.h>
  36. #include <asm/io.h>
  37. #include <asm/processor.h>
  38. #include <asm/oplib.h>
  39. #include <asm/page.h>
  40. #include <asm/idprom.h>
  41. #include <asm/head.h>
  42. #include <asm/starfire.h>
  43. #include <asm/mmu_context.h>
  44. #include <asm/timer.h>
  45. #include <asm/sections.h>
  46. #include <asm/setup.h>
  47. #include <asm/mmu.h>
  48. #include <asm/ns87303.h>
  49. #include <asm/btext.h>
  50. #include <asm/elf.h>
  51. #include <asm/mdesc.h>
  52. #include <asm/cacheflush.h>
  53. #include <asm/dma.h>
  54. #include <asm/irq.h>
  55. #ifdef CONFIG_IP_PNP
  56. #include <net/ipconfig.h>
  57. #endif
  58. #include "entry.h"
  59. #include "kernel.h"
  60. /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
  61. * operations in asm/ns87303.h
  62. */
  63. DEFINE_SPINLOCK(ns87303_lock);
  64. EXPORT_SYMBOL(ns87303_lock);
  65. struct screen_info screen_info = {
  66. 0, 0, /* orig-x, orig-y */
  67. 0, /* unused */
  68. 0, /* orig-video-page */
  69. 0, /* orig-video-mode */
  70. 128, /* orig-video-cols */
  71. 0, 0, 0, /* unused, ega_bx, unused */
  72. 54, /* orig-video-lines */
  73. 0, /* orig-video-isVGA */
  74. 16 /* orig-video-points */
  75. };
  76. static void
  77. prom_console_write(struct console *con, const char *s, unsigned int n)
  78. {
  79. prom_write(s, n);
  80. }
  81. /* Exported for mm/init.c:paging_init. */
  82. unsigned long cmdline_memory_size = 0;
  83. static struct console prom_early_console = {
  84. .name = "earlyprom",
  85. .write = prom_console_write,
  86. .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
  87. .index = -1,
  88. };
  89. /*
  90. * Process kernel command line switches that are specific to the
  91. * SPARC or that require special low-level processing.
  92. */
  93. static void __init process_switch(char c)
  94. {
  95. switch (c) {
  96. case 'd':
  97. case 's':
  98. break;
  99. case 'h':
  100. prom_printf("boot_flags_init: Halt!\n");
  101. prom_halt();
  102. break;
  103. case 'p':
  104. prom_early_console.flags &= ~CON_BOOT;
  105. break;
  106. case 'P':
  107. /* Force UltraSPARC-III P-Cache on. */
  108. if (tlb_type != cheetah) {
  109. printk("BOOT: Ignoring P-Cache force option.\n");
  110. break;
  111. }
  112. cheetah_pcache_forced_on = 1;
  113. add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
  114. cheetah_enable_pcache();
  115. break;
  116. default:
  117. printk("Unknown boot switch (-%c)\n", c);
  118. break;
  119. }
  120. }
  121. static void __init boot_flags_init(char *commands)
  122. {
  123. while (*commands) {
  124. /* Move to the start of the next "argument". */
  125. while (*commands == ' ')
  126. commands++;
  127. /* Process any command switches, otherwise skip it. */
  128. if (*commands == '\0')
  129. break;
  130. if (*commands == '-') {
  131. commands++;
  132. while (*commands && *commands != ' ')
  133. process_switch(*commands++);
  134. continue;
  135. }
  136. if (!strncmp(commands, "mem=", 4))
  137. cmdline_memory_size = memparse(commands + 4, &commands);
  138. while (*commands && *commands != ' ')
  139. commands++;
  140. }
  141. }
  142. extern unsigned short root_flags;
  143. extern unsigned short root_dev;
  144. extern unsigned short ram_flags;
  145. #define RAMDISK_IMAGE_START_MASK 0x07FF
  146. #define RAMDISK_PROMPT_FLAG 0x8000
  147. #define RAMDISK_LOAD_FLAG 0x4000
  148. extern int root_mountflags;
  149. char reboot_command[COMMAND_LINE_SIZE];
  150. static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
  151. static void __init per_cpu_patch(void)
  152. {
  153. struct cpuid_patch_entry *p;
  154. unsigned long ver;
  155. int is_jbus;
  156. if (tlb_type == spitfire && !this_is_starfire)
  157. return;
  158. is_jbus = 0;
  159. if (tlb_type != hypervisor) {
  160. __asm__ ("rdpr %%ver, %0" : "=r" (ver));
  161. is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
  162. (ver >> 32UL) == __SERRANO_ID);
  163. }
  164. p = &__cpuid_patch;
  165. while (p < &__cpuid_patch_end) {
  166. unsigned long addr = p->addr;
  167. unsigned int *insns;
  168. switch (tlb_type) {
  169. case spitfire:
  170. insns = &p->starfire[0];
  171. break;
  172. case cheetah:
  173. case cheetah_plus:
  174. if (is_jbus)
  175. insns = &p->cheetah_jbus[0];
  176. else
  177. insns = &p->cheetah_safari[0];
  178. break;
  179. case hypervisor:
  180. insns = &p->sun4v[0];
  181. break;
  182. default:
  183. prom_printf("Unknown cpu type, halting.\n");
  184. prom_halt();
  185. }
  186. *(unsigned int *) (addr + 0) = insns[0];
  187. wmb();
  188. __asm__ __volatile__("flush %0" : : "r" (addr + 0));
  189. *(unsigned int *) (addr + 4) = insns[1];
  190. wmb();
  191. __asm__ __volatile__("flush %0" : : "r" (addr + 4));
  192. *(unsigned int *) (addr + 8) = insns[2];
  193. wmb();
  194. __asm__ __volatile__("flush %0" : : "r" (addr + 8));
  195. *(unsigned int *) (addr + 12) = insns[3];
  196. wmb();
  197. __asm__ __volatile__("flush %0" : : "r" (addr + 12));
  198. p++;
  199. }
  200. }
  201. void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
  202. struct sun4v_1insn_patch_entry *end)
  203. {
  204. while (start < end) {
  205. unsigned long addr = start->addr;
  206. *(unsigned int *) (addr + 0) = start->insn;
  207. wmb();
  208. __asm__ __volatile__("flush %0" : : "r" (addr + 0));
  209. start++;
  210. }
  211. }
  212. void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
  213. struct sun4v_2insn_patch_entry *end)
  214. {
  215. while (start < end) {
  216. unsigned long addr = start->addr;
  217. *(unsigned int *) (addr + 0) = start->insns[0];
  218. wmb();
  219. __asm__ __volatile__("flush %0" : : "r" (addr + 0));
  220. *(unsigned int *) (addr + 4) = start->insns[1];
  221. wmb();
  222. __asm__ __volatile__("flush %0" : : "r" (addr + 4));
  223. start++;
  224. }
  225. }
  226. void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
  227. struct sun4v_2insn_patch_entry *end)
  228. {
  229. while (start < end) {
  230. unsigned long addr = start->addr;
  231. *(unsigned int *) (addr + 0) = start->insns[0];
  232. wmb();
  233. __asm__ __volatile__("flush %0" : : "r" (addr + 0));
  234. *(unsigned int *) (addr + 4) = start->insns[1];
  235. wmb();
  236. __asm__ __volatile__("flush %0" : : "r" (addr + 4));
  237. start++;
  238. }
  239. }
  240. static void __init sun4v_patch(void)
  241. {
  242. extern void sun4v_hvapi_init(void);
  243. if (tlb_type != hypervisor)
  244. return;
  245. sun4v_patch_1insn_range(&__sun4v_1insn_patch,
  246. &__sun4v_1insn_patch_end);
  247. sun4v_patch_2insn_range(&__sun4v_2insn_patch,
  248. &__sun4v_2insn_patch_end);
  249. switch (sun4v_chip_type) {
  250. case SUN4V_CHIP_SPARC_M7:
  251. case SUN4V_CHIP_SPARC_M8:
  252. case SUN4V_CHIP_SPARC_SN:
  253. sun4v_patch_1insn_range(&__sun_m7_1insn_patch,
  254. &__sun_m7_1insn_patch_end);
  255. sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
  256. &__sun_m7_2insn_patch_end);
  257. break;
  258. default:
  259. break;
  260. }
  261. if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) {
  262. sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
  263. &__fast_win_ctrl_1insn_patch_end);
  264. }
  265. sun4v_hvapi_init();
  266. }
  267. static void __init popc_patch(void)
  268. {
  269. struct popc_3insn_patch_entry *p3;
  270. struct popc_6insn_patch_entry *p6;
  271. p3 = &__popc_3insn_patch;
  272. while (p3 < &__popc_3insn_patch_end) {
  273. unsigned long i, addr = p3->addr;
  274. for (i = 0; i < 3; i++) {
  275. *(unsigned int *) (addr + (i * 4)) = p3->insns[i];
  276. wmb();
  277. __asm__ __volatile__("flush %0"
  278. : : "r" (addr + (i * 4)));
  279. }
  280. p3++;
  281. }
  282. p6 = &__popc_6insn_patch;
  283. while (p6 < &__popc_6insn_patch_end) {
  284. unsigned long i, addr = p6->addr;
  285. for (i = 0; i < 6; i++) {
  286. *(unsigned int *) (addr + (i * 4)) = p6->insns[i];
  287. wmb();
  288. __asm__ __volatile__("flush %0"
  289. : : "r" (addr + (i * 4)));
  290. }
  291. p6++;
  292. }
  293. }
  294. static void __init pause_patch(void)
  295. {
  296. struct pause_patch_entry *p;
  297. p = &__pause_3insn_patch;
  298. while (p < &__pause_3insn_patch_end) {
  299. unsigned long i, addr = p->addr;
  300. for (i = 0; i < 3; i++) {
  301. *(unsigned int *) (addr + (i * 4)) = p->insns[i];
  302. wmb();
  303. __asm__ __volatile__("flush %0"
  304. : : "r" (addr + (i * 4)));
  305. }
  306. p++;
  307. }
  308. }
  309. void __init start_early_boot(void)
  310. {
  311. int cpu;
  312. check_if_starfire();
  313. per_cpu_patch();
  314. sun4v_patch();
  315. smp_init_cpu_poke();
  316. cpu = hard_smp_processor_id();
  317. if (cpu >= NR_CPUS) {
  318. prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
  319. cpu, NR_CPUS);
  320. prom_halt();
  321. }
  322. current_thread_info()->cpu = cpu;
  323. time_init_early();
  324. prom_init_report();
  325. start_kernel();
  326. }
  327. /* On Ultra, we support all of the v8 capabilities. */
  328. unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
  329. HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
  330. HWCAP_SPARC_V9);
  331. EXPORT_SYMBOL(sparc64_elf_hwcap);
  332. static const char *hwcaps[] = {
  333. "flush", "stbar", "swap", "muldiv", "v9",
  334. "ultra3", "blkinit", "n2",
  335. /* These strings are as they appear in the machine description
  336. * 'hwcap-list' property for cpu nodes.
  337. */
  338. "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
  339. "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
  340. "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
  341. "adp",
  342. };
  343. static const char *crypto_hwcaps[] = {
  344. "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
  345. "sha512", "mpmul", "montmul", "montsqr", "crc32c",
  346. };
  347. void cpucap_info(struct seq_file *m)
  348. {
  349. unsigned long caps = sparc64_elf_hwcap;
  350. int i, printed = 0;
  351. seq_puts(m, "cpucaps\t\t: ");
  352. for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
  353. unsigned long bit = 1UL << i;
  354. if (hwcaps[i] && (caps & bit)) {
  355. seq_printf(m, "%s%s",
  356. printed ? "," : "", hwcaps[i]);
  357. printed++;
  358. }
  359. }
  360. if (caps & HWCAP_SPARC_CRYPTO) {
  361. unsigned long cfr;
  362. __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
  363. for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
  364. unsigned long bit = 1UL << i;
  365. if (cfr & bit) {
  366. seq_printf(m, "%s%s",
  367. printed ? "," : "", crypto_hwcaps[i]);
  368. printed++;
  369. }
  370. }
  371. }
  372. seq_putc(m, '\n');
  373. }
  374. static void __init report_one_hwcap(int *printed, const char *name)
  375. {
  376. if ((*printed) == 0)
  377. printk(KERN_INFO "CPU CAPS: [");
  378. printk(KERN_CONT "%s%s",
  379. (*printed) ? "," : "", name);
  380. if (++(*printed) == 8) {
  381. printk(KERN_CONT "]\n");
  382. *printed = 0;
  383. }
  384. }
  385. static void __init report_crypto_hwcaps(int *printed)
  386. {
  387. unsigned long cfr;
  388. int i;
  389. __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
  390. for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
  391. unsigned long bit = 1UL << i;
  392. if (cfr & bit)
  393. report_one_hwcap(printed, crypto_hwcaps[i]);
  394. }
  395. }
  396. static void __init report_hwcaps(unsigned long caps)
  397. {
  398. int i, printed = 0;
  399. for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
  400. unsigned long bit = 1UL << i;
  401. if (hwcaps[i] && (caps & bit))
  402. report_one_hwcap(&printed, hwcaps[i]);
  403. }
  404. if (caps & HWCAP_SPARC_CRYPTO)
  405. report_crypto_hwcaps(&printed);
  406. if (printed != 0)
  407. printk(KERN_CONT "]\n");
  408. }
  409. static unsigned long __init mdesc_cpu_hwcap_list(void)
  410. {
  411. struct mdesc_handle *hp;
  412. unsigned long caps = 0;
  413. const char *prop;
  414. int len;
  415. u64 pn;
  416. hp = mdesc_grab();
  417. if (!hp)
  418. return 0;
  419. pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
  420. if (pn == MDESC_NODE_NULL)
  421. goto out;
  422. prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
  423. if (!prop)
  424. goto out;
  425. while (len) {
  426. int i, plen;
  427. for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
  428. unsigned long bit = 1UL << i;
  429. if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
  430. caps |= bit;
  431. break;
  432. }
  433. }
  434. for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
  435. if (!strcmp(prop, crypto_hwcaps[i]))
  436. caps |= HWCAP_SPARC_CRYPTO;
  437. }
  438. plen = strlen(prop) + 1;
  439. prop += plen;
  440. len -= plen;
  441. }
  442. out:
  443. mdesc_release(hp);
  444. return caps;
  445. }
  446. /* This yields a mask that user programs can use to figure out what
  447. * instruction set this cpu supports.
  448. */
  449. static void __init init_sparc64_elf_hwcap(void)
  450. {
  451. unsigned long cap = sparc64_elf_hwcap;
  452. unsigned long mdesc_caps;
  453. if (tlb_type == cheetah || tlb_type == cheetah_plus)
  454. cap |= HWCAP_SPARC_ULTRA3;
  455. else if (tlb_type == hypervisor) {
  456. if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
  457. sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
  458. sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
  459. sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
  460. sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
  461. sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
  462. sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
  463. sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
  464. sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
  465. sun4v_chip_type == SUN4V_CHIP_SPARC64X)
  466. cap |= HWCAP_SPARC_BLKINIT;
  467. if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
  468. sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
  469. sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
  470. sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
  471. sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
  472. sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
  473. sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
  474. sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
  475. sun4v_chip_type == SUN4V_CHIP_SPARC64X)
  476. cap |= HWCAP_SPARC_N2;
  477. }
  478. cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
  479. mdesc_caps = mdesc_cpu_hwcap_list();
  480. if (!mdesc_caps) {
  481. if (tlb_type == spitfire)
  482. cap |= AV_SPARC_VIS;
  483. if (tlb_type == cheetah || tlb_type == cheetah_plus)
  484. cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
  485. if (tlb_type == cheetah_plus) {
  486. unsigned long impl, ver;
  487. __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
  488. impl = ((ver >> 32) & 0xffff);
  489. if (impl == PANTHER_IMPL)
  490. cap |= AV_SPARC_POPC;
  491. }
  492. if (tlb_type == hypervisor) {
  493. if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
  494. cap |= AV_SPARC_ASI_BLK_INIT;
  495. if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
  496. sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
  497. sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
  498. sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
  499. sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
  500. sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
  501. sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
  502. sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
  503. sun4v_chip_type == SUN4V_CHIP_SPARC64X)
  504. cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
  505. AV_SPARC_ASI_BLK_INIT |
  506. AV_SPARC_POPC);
  507. if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
  508. sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
  509. sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
  510. sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
  511. sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
  512. sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
  513. sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
  514. sun4v_chip_type == SUN4V_CHIP_SPARC64X)
  515. cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
  516. AV_SPARC_FMAF);
  517. }
  518. }
  519. sparc64_elf_hwcap = cap | mdesc_caps;
  520. report_hwcaps(sparc64_elf_hwcap);
  521. if (sparc64_elf_hwcap & AV_SPARC_POPC)
  522. popc_patch();
  523. if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
  524. pause_patch();
  525. }
  526. void __init alloc_irqstack_bootmem(void)
  527. {
  528. unsigned int i, node;
  529. for_each_possible_cpu(i) {
  530. node = cpu_to_node(i);
  531. softirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
  532. THREAD_SIZE, node);
  533. if (!softirq_stack[i])
  534. panic("%s: Failed to allocate %lu bytes align=%lx nid=%d\n",
  535. __func__, THREAD_SIZE, THREAD_SIZE, node);
  536. hardirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
  537. THREAD_SIZE, node);
  538. if (!hardirq_stack[i])
  539. panic("%s: Failed to allocate %lu bytes align=%lx nid=%d\n",
  540. __func__, THREAD_SIZE, THREAD_SIZE, node);
  541. }
  542. }
  543. void __init setup_arch(char **cmdline_p)
  544. {
  545. /* Initialize PROM console and command line. */
  546. *cmdline_p = prom_getbootargs();
  547. strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
  548. parse_early_param();
  549. boot_flags_init(*cmdline_p);
  550. #ifdef CONFIG_EARLYFB
  551. if (btext_find_display())
  552. #endif
  553. register_console(&prom_early_console);
  554. if (tlb_type == hypervisor)
  555. pr_info("ARCH: SUN4V\n");
  556. else
  557. pr_info("ARCH: SUN4U\n");
  558. idprom_init();
  559. if (!root_flags)
  560. root_mountflags &= ~MS_RDONLY;
  561. ROOT_DEV = old_decode_dev(root_dev);
  562. #ifdef CONFIG_BLK_DEV_RAM
  563. rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
  564. #endif
  565. task_thread_info(&init_task)->kregs = &fake_swapper_regs;
  566. #ifdef CONFIG_IP_PNP
  567. if (!ic_set_manually) {
  568. phandle chosen = prom_finddevice("/chosen");
  569. u32 cl, sv, gw;
  570. cl = prom_getintdefault (chosen, "client-ip", 0);
  571. sv = prom_getintdefault (chosen, "server-ip", 0);
  572. gw = prom_getintdefault (chosen, "gateway-ip", 0);
  573. if (cl && sv) {
  574. ic_myaddr = cl;
  575. ic_servaddr = sv;
  576. if (gw)
  577. ic_gateway = gw;
  578. #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
  579. ic_proto_enabled = 0;
  580. #endif
  581. }
  582. }
  583. #endif
  584. /* Get boot processor trap_block[] setup. */
  585. init_cur_cpu_trap(current_thread_info());
  586. paging_init();
  587. init_sparc64_elf_hwcap();
  588. smp_fill_in_cpu_possible_map();
  589. /*
  590. * Once the OF device tree and MDESC have been setup and nr_cpus has
  591. * been parsed, we know the list of possible cpus. Therefore we can
  592. * allocate the IRQ stacks.
  593. */
  594. alloc_irqstack_bootmem();
  595. }
  596. extern int stop_a_enabled;
  597. void sun_do_break(void)
  598. {
  599. if (!stop_a_enabled)
  600. return;
  601. prom_printf("\n");
  602. flush_user_windows();
  603. prom_cmdline();
  604. }
  605. EXPORT_SYMBOL(sun_do_break);
  606. int stop_a_enabled = 1;
  607. EXPORT_SYMBOL(stop_a_enabled);