sbus.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * sbus.c: UltraSparc SBUS controller support.
  4. *
  5. * Copyright (C) 1999 David S. Miller (davem@redhat.com)
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/types.h>
  9. #include <linux/mm.h>
  10. #include <linux/spinlock.h>
  11. #include <linux/slab.h>
  12. #include <linux/export.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/numa.h>
  18. #include <asm/page.h>
  19. #include <asm/io.h>
  20. #include <asm/upa.h>
  21. #include <asm/cache.h>
  22. #include <asm/dma.h>
  23. #include <asm/irq.h>
  24. #include <asm/prom.h>
  25. #include <asm/oplib.h>
  26. #include <asm/starfire.h>
  27. #include "iommu_common.h"
  28. #define MAP_BASE ((u32)0xc0000000)
  29. /* Offsets from iommu_regs */
  30. #define SYSIO_IOMMUREG_BASE 0x2400UL
  31. #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
  32. #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
  33. #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
  34. #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
  35. #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
  36. #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
  37. #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
  38. #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
  39. #define IOMMU_DRAM_VALID (1UL << 30UL)
  40. /* Offsets from strbuf_regs */
  41. #define SYSIO_STRBUFREG_BASE 0x2800UL
  42. #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
  43. #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
  44. #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
  45. #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
  46. #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
  47. #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
  48. #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
  49. #define STRBUF_TAG_VALID 0x02UL
  50. /* Enable 64-bit DVMA mode for the given device. */
  51. void sbus_set_sbus64(struct device *dev, int bursts)
  52. {
  53. struct iommu *iommu = dev->archdata.iommu;
  54. struct platform_device *op = to_platform_device(dev);
  55. const struct linux_prom_registers *regs;
  56. unsigned long cfg_reg;
  57. int slot;
  58. u64 val;
  59. regs = of_get_property(op->dev.of_node, "reg", NULL);
  60. if (!regs) {
  61. printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %pOF\n",
  62. op->dev.of_node);
  63. return;
  64. }
  65. slot = regs->which_io;
  66. cfg_reg = iommu->write_complete_reg;
  67. switch (slot) {
  68. case 0:
  69. cfg_reg += 0x20UL;
  70. break;
  71. case 1:
  72. cfg_reg += 0x28UL;
  73. break;
  74. case 2:
  75. cfg_reg += 0x30UL;
  76. break;
  77. case 3:
  78. cfg_reg += 0x38UL;
  79. break;
  80. case 13:
  81. cfg_reg += 0x40UL;
  82. break;
  83. case 14:
  84. cfg_reg += 0x48UL;
  85. break;
  86. case 15:
  87. cfg_reg += 0x50UL;
  88. break;
  89. default:
  90. return;
  91. }
  92. val = upa_readq(cfg_reg);
  93. if (val & (1UL << 14UL)) {
  94. /* Extended transfer mode already enabled. */
  95. return;
  96. }
  97. val |= (1UL << 14UL);
  98. if (bursts & DMA_BURST8)
  99. val |= (1UL << 1UL);
  100. if (bursts & DMA_BURST16)
  101. val |= (1UL << 2UL);
  102. if (bursts & DMA_BURST32)
  103. val |= (1UL << 3UL);
  104. if (bursts & DMA_BURST64)
  105. val |= (1UL << 4UL);
  106. upa_writeq(val, cfg_reg);
  107. }
  108. EXPORT_SYMBOL(sbus_set_sbus64);
  109. /* INO number to IMAP register offset for SYSIO external IRQ's.
  110. * This should conform to both Sunfire/Wildfire server and Fusion
  111. * desktop designs.
  112. */
  113. #define SYSIO_IMAP_SLOT0 0x2c00UL
  114. #define SYSIO_IMAP_SLOT1 0x2c08UL
  115. #define SYSIO_IMAP_SLOT2 0x2c10UL
  116. #define SYSIO_IMAP_SLOT3 0x2c18UL
  117. #define SYSIO_IMAP_SCSI 0x3000UL
  118. #define SYSIO_IMAP_ETH 0x3008UL
  119. #define SYSIO_IMAP_BPP 0x3010UL
  120. #define SYSIO_IMAP_AUDIO 0x3018UL
  121. #define SYSIO_IMAP_PFAIL 0x3020UL
  122. #define SYSIO_IMAP_KMS 0x3028UL
  123. #define SYSIO_IMAP_FLPY 0x3030UL
  124. #define SYSIO_IMAP_SHW 0x3038UL
  125. #define SYSIO_IMAP_KBD 0x3040UL
  126. #define SYSIO_IMAP_MS 0x3048UL
  127. #define SYSIO_IMAP_SER 0x3050UL
  128. #define SYSIO_IMAP_TIM0 0x3060UL
  129. #define SYSIO_IMAP_TIM1 0x3068UL
  130. #define SYSIO_IMAP_UE 0x3070UL
  131. #define SYSIO_IMAP_CE 0x3078UL
  132. #define SYSIO_IMAP_SBERR 0x3080UL
  133. #define SYSIO_IMAP_PMGMT 0x3088UL
  134. #define SYSIO_IMAP_GFX 0x3090UL
  135. #define SYSIO_IMAP_EUPA 0x3098UL
  136. #define bogon ((unsigned long) -1)
  137. static unsigned long sysio_irq_offsets[] = {
  138. /* SBUS Slot 0 --> 3, level 1 --> 7 */
  139. SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
  140. SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
  141. SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
  142. SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
  143. SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
  144. SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
  145. SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
  146. SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
  147. /* Onboard devices (not relevant/used on SunFire). */
  148. SYSIO_IMAP_SCSI,
  149. SYSIO_IMAP_ETH,
  150. SYSIO_IMAP_BPP,
  151. bogon,
  152. SYSIO_IMAP_AUDIO,
  153. SYSIO_IMAP_PFAIL,
  154. bogon,
  155. bogon,
  156. SYSIO_IMAP_KMS,
  157. SYSIO_IMAP_FLPY,
  158. SYSIO_IMAP_SHW,
  159. SYSIO_IMAP_KBD,
  160. SYSIO_IMAP_MS,
  161. SYSIO_IMAP_SER,
  162. bogon,
  163. bogon,
  164. SYSIO_IMAP_TIM0,
  165. SYSIO_IMAP_TIM1,
  166. bogon,
  167. bogon,
  168. SYSIO_IMAP_UE,
  169. SYSIO_IMAP_CE,
  170. SYSIO_IMAP_SBERR,
  171. SYSIO_IMAP_PMGMT,
  172. };
  173. #undef bogon
  174. #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
  175. /* Convert Interrupt Mapping register pointer to associated
  176. * Interrupt Clear register pointer, SYSIO specific version.
  177. */
  178. #define SYSIO_ICLR_UNUSED0 0x3400UL
  179. #define SYSIO_ICLR_SLOT0 0x3408UL
  180. #define SYSIO_ICLR_SLOT1 0x3448UL
  181. #define SYSIO_ICLR_SLOT2 0x3488UL
  182. #define SYSIO_ICLR_SLOT3 0x34c8UL
  183. static unsigned long sysio_imap_to_iclr(unsigned long imap)
  184. {
  185. unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
  186. return imap + diff;
  187. }
  188. static unsigned int sbus_build_irq(struct platform_device *op, unsigned int ino)
  189. {
  190. struct iommu *iommu = op->dev.archdata.iommu;
  191. unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
  192. unsigned long imap, iclr;
  193. int sbus_level = 0;
  194. imap = sysio_irq_offsets[ino];
  195. if (imap == ((unsigned long)-1)) {
  196. prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
  197. ino);
  198. prom_halt();
  199. }
  200. imap += reg_base;
  201. /* SYSIO inconsistency. For external SLOTS, we have to select
  202. * the right ICLR register based upon the lower SBUS irq level
  203. * bits.
  204. */
  205. if (ino >= 0x20) {
  206. iclr = sysio_imap_to_iclr(imap);
  207. } else {
  208. int sbus_slot = (ino & 0x18)>>3;
  209. sbus_level = ino & 0x7;
  210. switch(sbus_slot) {
  211. case 0:
  212. iclr = reg_base + SYSIO_ICLR_SLOT0;
  213. break;
  214. case 1:
  215. iclr = reg_base + SYSIO_ICLR_SLOT1;
  216. break;
  217. case 2:
  218. iclr = reg_base + SYSIO_ICLR_SLOT2;
  219. break;
  220. default:
  221. case 3:
  222. iclr = reg_base + SYSIO_ICLR_SLOT3;
  223. break;
  224. }
  225. iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
  226. }
  227. return build_irq(sbus_level, iclr, imap);
  228. }
  229. /* Error interrupt handling. */
  230. #define SYSIO_UE_AFSR 0x0030UL
  231. #define SYSIO_UE_AFAR 0x0038UL
  232. #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
  233. #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
  234. #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
  235. #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
  236. #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
  237. #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
  238. #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
  239. #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */
  240. #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
  241. #define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
  242. #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
  243. static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
  244. {
  245. struct platform_device *op = dev_id;
  246. struct iommu *iommu = op->dev.archdata.iommu;
  247. unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
  248. unsigned long afsr_reg, afar_reg;
  249. unsigned long afsr, afar, error_bits;
  250. int reported, portid;
  251. afsr_reg = reg_base + SYSIO_UE_AFSR;
  252. afar_reg = reg_base + SYSIO_UE_AFAR;
  253. /* Latch error status. */
  254. afsr = upa_readq(afsr_reg);
  255. afar = upa_readq(afar_reg);
  256. /* Clear primary/secondary error status bits. */
  257. error_bits = afsr &
  258. (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
  259. SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
  260. upa_writeq(error_bits, afsr_reg);
  261. portid = of_getintprop_default(op->dev.of_node, "portid", -1);
  262. /* Log the error. */
  263. printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
  264. portid,
  265. (((error_bits & SYSIO_UEAFSR_PPIO) ?
  266. "PIO" :
  267. ((error_bits & SYSIO_UEAFSR_PDRD) ?
  268. "DVMA Read" :
  269. ((error_bits & SYSIO_UEAFSR_PDWR) ?
  270. "DVMA Write" : "???")))));
  271. printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
  272. portid,
  273. (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
  274. (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
  275. (afsr & SYSIO_UEAFSR_MID) >> 37UL);
  276. printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
  277. printk("SYSIO[%x]: Secondary UE errors [", portid);
  278. reported = 0;
  279. if (afsr & SYSIO_UEAFSR_SPIO) {
  280. reported++;
  281. printk("(PIO)");
  282. }
  283. if (afsr & SYSIO_UEAFSR_SDRD) {
  284. reported++;
  285. printk("(DVMA Read)");
  286. }
  287. if (afsr & SYSIO_UEAFSR_SDWR) {
  288. reported++;
  289. printk("(DVMA Write)");
  290. }
  291. if (!reported)
  292. printk("(none)");
  293. printk("]\n");
  294. return IRQ_HANDLED;
  295. }
  296. #define SYSIO_CE_AFSR 0x0040UL
  297. #define SYSIO_CE_AFAR 0x0048UL
  298. #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
  299. #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
  300. #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
  301. #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
  302. #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
  303. #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
  304. #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
  305. #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
  306. #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
  307. #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
  308. #define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
  309. #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
  310. static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
  311. {
  312. struct platform_device *op = dev_id;
  313. struct iommu *iommu = op->dev.archdata.iommu;
  314. unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
  315. unsigned long afsr_reg, afar_reg;
  316. unsigned long afsr, afar, error_bits;
  317. int reported, portid;
  318. afsr_reg = reg_base + SYSIO_CE_AFSR;
  319. afar_reg = reg_base + SYSIO_CE_AFAR;
  320. /* Latch error status. */
  321. afsr = upa_readq(afsr_reg);
  322. afar = upa_readq(afar_reg);
  323. /* Clear primary/secondary error status bits. */
  324. error_bits = afsr &
  325. (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
  326. SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
  327. upa_writeq(error_bits, afsr_reg);
  328. portid = of_getintprop_default(op->dev.of_node, "portid", -1);
  329. printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
  330. portid,
  331. (((error_bits & SYSIO_CEAFSR_PPIO) ?
  332. "PIO" :
  333. ((error_bits & SYSIO_CEAFSR_PDRD) ?
  334. "DVMA Read" :
  335. ((error_bits & SYSIO_CEAFSR_PDWR) ?
  336. "DVMA Write" : "???")))));
  337. /* XXX Use syndrome and afar to print out module string just like
  338. * XXX UDB CE trap handler does... -DaveM
  339. */
  340. printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
  341. portid,
  342. (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
  343. (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
  344. (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
  345. (afsr & SYSIO_CEAFSR_MID) >> 37UL);
  346. printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
  347. printk("SYSIO[%x]: Secondary CE errors [", portid);
  348. reported = 0;
  349. if (afsr & SYSIO_CEAFSR_SPIO) {
  350. reported++;
  351. printk("(PIO)");
  352. }
  353. if (afsr & SYSIO_CEAFSR_SDRD) {
  354. reported++;
  355. printk("(DVMA Read)");
  356. }
  357. if (afsr & SYSIO_CEAFSR_SDWR) {
  358. reported++;
  359. printk("(DVMA Write)");
  360. }
  361. if (!reported)
  362. printk("(none)");
  363. printk("]\n");
  364. return IRQ_HANDLED;
  365. }
  366. #define SYSIO_SBUS_AFSR 0x2010UL
  367. #define SYSIO_SBUS_AFAR 0x2018UL
  368. #define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */
  369. #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
  370. #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
  371. #define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */
  372. #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
  373. #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
  374. #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */
  375. #define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */
  376. #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */
  377. #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */
  378. #define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */
  379. #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
  380. static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
  381. {
  382. struct platform_device *op = dev_id;
  383. struct iommu *iommu = op->dev.archdata.iommu;
  384. unsigned long afsr_reg, afar_reg, reg_base;
  385. unsigned long afsr, afar, error_bits;
  386. int reported, portid;
  387. reg_base = iommu->write_complete_reg - 0x2000UL;
  388. afsr_reg = reg_base + SYSIO_SBUS_AFSR;
  389. afar_reg = reg_base + SYSIO_SBUS_AFAR;
  390. afsr = upa_readq(afsr_reg);
  391. afar = upa_readq(afar_reg);
  392. /* Clear primary/secondary error status bits. */
  393. error_bits = afsr &
  394. (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
  395. SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
  396. upa_writeq(error_bits, afsr_reg);
  397. portid = of_getintprop_default(op->dev.of_node, "portid", -1);
  398. /* Log the error. */
  399. printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
  400. portid,
  401. (((error_bits & SYSIO_SBAFSR_PLE) ?
  402. "Late PIO Error" :
  403. ((error_bits & SYSIO_SBAFSR_PTO) ?
  404. "Time Out" :
  405. ((error_bits & SYSIO_SBAFSR_PBERR) ?
  406. "Error Ack" : "???")))),
  407. (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
  408. printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
  409. portid,
  410. (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
  411. (afsr & SYSIO_SBAFSR_MID) >> 37UL);
  412. printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
  413. printk("SYSIO[%x]: Secondary SBUS errors [", portid);
  414. reported = 0;
  415. if (afsr & SYSIO_SBAFSR_SLE) {
  416. reported++;
  417. printk("(Late PIO Error)");
  418. }
  419. if (afsr & SYSIO_SBAFSR_STO) {
  420. reported++;
  421. printk("(Time Out)");
  422. }
  423. if (afsr & SYSIO_SBAFSR_SBERR) {
  424. reported++;
  425. printk("(Error Ack)");
  426. }
  427. if (!reported)
  428. printk("(none)");
  429. printk("]\n");
  430. /* XXX check iommu/strbuf for further error status XXX */
  431. return IRQ_HANDLED;
  432. }
  433. #define ECC_CONTROL 0x0020UL
  434. #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */
  435. #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */
  436. #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */
  437. #define SYSIO_UE_INO 0x34
  438. #define SYSIO_CE_INO 0x35
  439. #define SYSIO_SBUSERR_INO 0x36
  440. static void __init sysio_register_error_handlers(struct platform_device *op)
  441. {
  442. struct iommu *iommu = op->dev.archdata.iommu;
  443. unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
  444. unsigned int irq;
  445. u64 control;
  446. int portid;
  447. portid = of_getintprop_default(op->dev.of_node, "portid", -1);
  448. irq = sbus_build_irq(op, SYSIO_UE_INO);
  449. if (request_irq(irq, sysio_ue_handler, 0,
  450. "SYSIO_UE", op) < 0) {
  451. prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
  452. portid);
  453. prom_halt();
  454. }
  455. irq = sbus_build_irq(op, SYSIO_CE_INO);
  456. if (request_irq(irq, sysio_ce_handler, 0,
  457. "SYSIO_CE", op) < 0) {
  458. prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
  459. portid);
  460. prom_halt();
  461. }
  462. irq = sbus_build_irq(op, SYSIO_SBUSERR_INO);
  463. if (request_irq(irq, sysio_sbus_error_handler, 0,
  464. "SYSIO_SBERR", op) < 0) {
  465. prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
  466. portid);
  467. prom_halt();
  468. }
  469. /* Now turn the error interrupts on and also enable ECC checking. */
  470. upa_writeq((SYSIO_ECNTRL_ECCEN |
  471. SYSIO_ECNTRL_UEEN |
  472. SYSIO_ECNTRL_CEEN),
  473. reg_base + ECC_CONTROL);
  474. control = upa_readq(iommu->write_complete_reg);
  475. control |= 0x100UL; /* SBUS Error Interrupt Enable */
  476. upa_writeq(control, iommu->write_complete_reg);
  477. }
  478. /* Boot time initialization. */
  479. static void __init sbus_iommu_init(struct platform_device *op)
  480. {
  481. const struct linux_prom64_registers *pr;
  482. struct device_node *dp = op->dev.of_node;
  483. struct iommu *iommu;
  484. struct strbuf *strbuf;
  485. unsigned long regs, reg_base;
  486. int i, portid;
  487. u64 control;
  488. pr = of_get_property(dp, "reg", NULL);
  489. if (!pr) {
  490. prom_printf("sbus_iommu_init: Cannot map SYSIO "
  491. "control registers.\n");
  492. prom_halt();
  493. }
  494. regs = pr->phys_addr;
  495. iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
  496. strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC);
  497. if (!iommu || !strbuf)
  498. goto fatal_memory_error;
  499. op->dev.archdata.iommu = iommu;
  500. op->dev.archdata.stc = strbuf;
  501. op->dev.archdata.numa_node = NUMA_NO_NODE;
  502. reg_base = regs + SYSIO_IOMMUREG_BASE;
  503. iommu->iommu_control = reg_base + IOMMU_CONTROL;
  504. iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE;
  505. iommu->iommu_flush = reg_base + IOMMU_FLUSH;
  506. iommu->iommu_tags = iommu->iommu_control +
  507. (IOMMU_TAGDIAG - IOMMU_CONTROL);
  508. reg_base = regs + SYSIO_STRBUFREG_BASE;
  509. strbuf->strbuf_control = reg_base + STRBUF_CONTROL;
  510. strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH;
  511. strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC;
  512. strbuf->strbuf_enabled = 1;
  513. strbuf->strbuf_flushflag = (volatile unsigned long *)
  514. ((((unsigned long)&strbuf->__flushflag_buf[0])
  515. + 63UL)
  516. & ~63UL);
  517. strbuf->strbuf_flushflag_pa = (unsigned long)
  518. __pa(strbuf->strbuf_flushflag);
  519. /* The SYSIO SBUS control register is used for dummy reads
  520. * in order to ensure write completion.
  521. */
  522. iommu->write_complete_reg = regs + 0x2000UL;
  523. portid = of_getintprop_default(op->dev.of_node, "portid", -1);
  524. printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n",
  525. portid, regs);
  526. /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
  527. if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
  528. goto fatal_memory_error;
  529. control = upa_readq(iommu->iommu_control);
  530. control = ((7UL << 16UL) |
  531. (0UL << 2UL) |
  532. (1UL << 1UL) |
  533. (1UL << 0UL));
  534. upa_writeq(control, iommu->iommu_control);
  535. /* Clean out any cruft in the IOMMU using
  536. * diagnostic accesses.
  537. */
  538. for (i = 0; i < 16; i++) {
  539. unsigned long dram, tag;
  540. dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL);
  541. tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
  542. dram += (unsigned long)i * 8UL;
  543. tag += (unsigned long)i * 8UL;
  544. upa_writeq(0, dram);
  545. upa_writeq(0, tag);
  546. }
  547. upa_readq(iommu->write_complete_reg);
  548. /* Give the TSB to SYSIO. */
  549. upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
  550. /* Setup streaming buffer, DE=1 SB_EN=1 */
  551. control = (1UL << 1UL) | (1UL << 0UL);
  552. upa_writeq(control, strbuf->strbuf_control);
  553. /* Clear out the tags using diagnostics. */
  554. for (i = 0; i < 16; i++) {
  555. unsigned long ptag, ltag;
  556. ptag = strbuf->strbuf_control +
  557. (STRBUF_PTAGDIAG - STRBUF_CONTROL);
  558. ltag = strbuf->strbuf_control +
  559. (STRBUF_LTAGDIAG - STRBUF_CONTROL);
  560. ptag += (unsigned long)i * 8UL;
  561. ltag += (unsigned long)i * 8UL;
  562. upa_writeq(0UL, ptag);
  563. upa_writeq(0UL, ltag);
  564. }
  565. /* Enable DVMA arbitration for all devices/slots. */
  566. control = upa_readq(iommu->write_complete_reg);
  567. control |= 0x3fUL;
  568. upa_writeq(control, iommu->write_complete_reg);
  569. /* Now some Xfire specific grot... */
  570. if (this_is_starfire)
  571. starfire_hookup(portid);
  572. sysio_register_error_handlers(op);
  573. return;
  574. fatal_memory_error:
  575. kfree(iommu);
  576. kfree(strbuf);
  577. prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
  578. }
  579. static int __init sbus_init(void)
  580. {
  581. struct device_node *dp;
  582. for_each_node_by_name(dp, "sbus") {
  583. struct platform_device *op = of_find_device_by_node(dp);
  584. sbus_iommu_init(op);
  585. of_propagate_archdata(op);
  586. }
  587. return 0;
  588. }
  589. subsys_initcall(sbus_init);