prom_irqtrans.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/kernel.h>
  3. #include <linux/string.h>
  4. #include <linux/init.h>
  5. #include <linux/of.h>
  6. #include <linux/of_platform.h>
  7. #include <asm/oplib.h>
  8. #include <asm/prom.h>
  9. #include <asm/irq.h>
  10. #include <asm/upa.h>
  11. #include "prom.h"
  12. #ifdef CONFIG_PCI
  13. /* PSYCHO interrupt mapping support. */
  14. #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
  15. #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
  16. static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
  17. {
  18. unsigned int bus = (ino & 0x10) >> 4;
  19. unsigned int slot = (ino & 0x0c) >> 2;
  20. if (bus == 0)
  21. return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
  22. else
  23. return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
  24. }
  25. #define PSYCHO_OBIO_IMAP_BASE 0x1000UL
  26. #define PSYCHO_ONBOARD_IRQ_BASE 0x20
  27. #define psycho_onboard_imap_offset(__ino) \
  28. (PSYCHO_OBIO_IMAP_BASE + (((__ino) & 0x1f) << 3))
  29. #define PSYCHO_ICLR_A_SLOT0 0x1400UL
  30. #define PSYCHO_ICLR_SCSI 0x1800UL
  31. #define psycho_iclr_offset(ino) \
  32. ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
  33. (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
  34. static unsigned int psycho_irq_build(struct device_node *dp,
  35. unsigned int ino,
  36. void *_data)
  37. {
  38. unsigned long controller_regs = (unsigned long) _data;
  39. unsigned long imap, iclr;
  40. unsigned long imap_off, iclr_off;
  41. int inofixup = 0;
  42. ino &= 0x3f;
  43. if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
  44. /* PCI slot */
  45. imap_off = psycho_pcislot_imap_offset(ino);
  46. } else {
  47. /* Onboard device */
  48. imap_off = psycho_onboard_imap_offset(ino);
  49. }
  50. /* Now build the IRQ bucket. */
  51. imap = controller_regs + imap_off;
  52. iclr_off = psycho_iclr_offset(ino);
  53. iclr = controller_regs + iclr_off;
  54. if ((ino & 0x20) == 0)
  55. inofixup = ino & 0x03;
  56. return build_irq(inofixup, iclr, imap);
  57. }
  58. static void __init psycho_irq_trans_init(struct device_node *dp)
  59. {
  60. const struct linux_prom64_registers *regs;
  61. dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
  62. dp->irq_trans->irq_build = psycho_irq_build;
  63. regs = of_get_property(dp, "reg", NULL);
  64. dp->irq_trans->data = (void *) regs[2].phys_addr;
  65. }
  66. #define sabre_read(__reg) \
  67. ({ u64 __ret; \
  68. __asm__ __volatile__("ldxa [%1] %2, %0" \
  69. : "=r" (__ret) \
  70. : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  71. : "memory"); \
  72. __ret; \
  73. })
  74. struct sabre_irq_data {
  75. unsigned long controller_regs;
  76. unsigned int pci_first_busno;
  77. };
  78. #define SABRE_CONFIGSPACE 0x001000000UL
  79. #define SABRE_WRSYNC 0x1c20UL
  80. #define SABRE_CONFIG_BASE(CONFIG_SPACE) \
  81. (CONFIG_SPACE | (1UL << 24))
  82. #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
  83. (((unsigned long)(BUS) << 16) | \
  84. ((unsigned long)(DEVFN) << 8) | \
  85. ((unsigned long)(REG)))
  86. /* When a device lives behind a bridge deeper in the PCI bus topology
  87. * than APB, a special sequence must run to make sure all pending DMA
  88. * transfers at the time of IRQ delivery are visible in the coherency
  89. * domain by the cpu. This sequence is to perform a read on the far
  90. * side of the non-APB bridge, then perform a read of Sabre's DMA
  91. * write-sync register.
  92. */
  93. static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
  94. {
  95. unsigned int phys_hi = (unsigned int) (unsigned long) _arg1;
  96. struct sabre_irq_data *irq_data = _arg2;
  97. unsigned long controller_regs = irq_data->controller_regs;
  98. unsigned long sync_reg = controller_regs + SABRE_WRSYNC;
  99. unsigned long config_space = controller_regs + SABRE_CONFIGSPACE;
  100. unsigned int bus, devfn;
  101. u16 _unused;
  102. config_space = SABRE_CONFIG_BASE(config_space);
  103. bus = (phys_hi >> 16) & 0xff;
  104. devfn = (phys_hi >> 8) & 0xff;
  105. config_space |= SABRE_CONFIG_ENCODE(bus, devfn, 0x00);
  106. __asm__ __volatile__("membar #Sync\n\t"
  107. "lduha [%1] %2, %0\n\t"
  108. "membar #Sync"
  109. : "=r" (_unused)
  110. : "r" ((u16 *) config_space),
  111. "i" (ASI_PHYS_BYPASS_EC_E_L)
  112. : "memory");
  113. sabre_read(sync_reg);
  114. }
  115. #define SABRE_IMAP_A_SLOT0 0x0c00UL
  116. #define SABRE_IMAP_B_SLOT0 0x0c20UL
  117. #define SABRE_ICLR_A_SLOT0 0x1400UL
  118. #define SABRE_ICLR_B_SLOT0 0x1480UL
  119. #define SABRE_ICLR_SCSI 0x1800UL
  120. #define SABRE_ICLR_ETH 0x1808UL
  121. #define SABRE_ICLR_BPP 0x1810UL
  122. #define SABRE_ICLR_AU_REC 0x1818UL
  123. #define SABRE_ICLR_AU_PLAY 0x1820UL
  124. #define SABRE_ICLR_PFAIL 0x1828UL
  125. #define SABRE_ICLR_KMS 0x1830UL
  126. #define SABRE_ICLR_FLPY 0x1838UL
  127. #define SABRE_ICLR_SHW 0x1840UL
  128. #define SABRE_ICLR_KBD 0x1848UL
  129. #define SABRE_ICLR_MS 0x1850UL
  130. #define SABRE_ICLR_SER 0x1858UL
  131. #define SABRE_ICLR_UE 0x1870UL
  132. #define SABRE_ICLR_CE 0x1878UL
  133. #define SABRE_ICLR_PCIERR 0x1880UL
  134. static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
  135. {
  136. unsigned int bus = (ino & 0x10) >> 4;
  137. unsigned int slot = (ino & 0x0c) >> 2;
  138. if (bus == 0)
  139. return SABRE_IMAP_A_SLOT0 + (slot * 8);
  140. else
  141. return SABRE_IMAP_B_SLOT0 + (slot * 8);
  142. }
  143. #define SABRE_OBIO_IMAP_BASE 0x1000UL
  144. #define SABRE_ONBOARD_IRQ_BASE 0x20
  145. #define sabre_onboard_imap_offset(__ino) \
  146. (SABRE_OBIO_IMAP_BASE + (((__ino) & 0x1f) << 3))
  147. #define sabre_iclr_offset(ino) \
  148. ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
  149. (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
  150. static int sabre_device_needs_wsync(struct device_node *dp)
  151. {
  152. struct device_node *parent = dp->parent;
  153. const char *parent_model, *parent_compat;
  154. /* This traversal up towards the root is meant to
  155. * handle two cases:
  156. *
  157. * 1) non-PCI bus sitting under PCI, such as 'ebus'
  158. * 2) the PCI controller interrupts themselves, which
  159. * will use the sabre_irq_build but do not need
  160. * the DMA synchronization handling
  161. */
  162. while (parent) {
  163. if (of_node_is_type(parent, "pci"))
  164. break;
  165. parent = parent->parent;
  166. }
  167. if (!parent)
  168. return 0;
  169. parent_model = of_get_property(parent,
  170. "model", NULL);
  171. if (parent_model &&
  172. (!strcmp(parent_model, "SUNW,sabre") ||
  173. !strcmp(parent_model, "SUNW,simba")))
  174. return 0;
  175. parent_compat = of_get_property(parent,
  176. "compatible", NULL);
  177. if (parent_compat &&
  178. (!strcmp(parent_compat, "pci108e,a000") ||
  179. !strcmp(parent_compat, "pci108e,a001")))
  180. return 0;
  181. return 1;
  182. }
  183. static unsigned int sabre_irq_build(struct device_node *dp,
  184. unsigned int ino,
  185. void *_data)
  186. {
  187. struct sabre_irq_data *irq_data = _data;
  188. unsigned long controller_regs = irq_data->controller_regs;
  189. const struct linux_prom_pci_registers *regs;
  190. unsigned long imap, iclr;
  191. unsigned long imap_off, iclr_off;
  192. int inofixup = 0;
  193. int irq;
  194. ino &= 0x3f;
  195. if (ino < SABRE_ONBOARD_IRQ_BASE) {
  196. /* PCI slot */
  197. imap_off = sabre_pcislot_imap_offset(ino);
  198. } else {
  199. /* onboard device */
  200. imap_off = sabre_onboard_imap_offset(ino);
  201. }
  202. /* Now build the IRQ bucket. */
  203. imap = controller_regs + imap_off;
  204. iclr_off = sabre_iclr_offset(ino);
  205. iclr = controller_regs + iclr_off;
  206. if ((ino & 0x20) == 0)
  207. inofixup = ino & 0x03;
  208. irq = build_irq(inofixup, iclr, imap);
  209. /* If the parent device is a PCI<->PCI bridge other than
  210. * APB, we have to install a pre-handler to ensure that
  211. * all pending DMA is drained before the interrupt handler
  212. * is run.
  213. */
  214. regs = of_get_property(dp, "reg", NULL);
  215. if (regs && sabre_device_needs_wsync(dp)) {
  216. irq_install_pre_handler(irq,
  217. sabre_wsync_handler,
  218. (void *) (long) regs->phys_hi,
  219. (void *) irq_data);
  220. }
  221. return irq;
  222. }
  223. static void __init sabre_irq_trans_init(struct device_node *dp)
  224. {
  225. const struct linux_prom64_registers *regs;
  226. struct sabre_irq_data *irq_data;
  227. const u32 *busrange;
  228. dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
  229. dp->irq_trans->irq_build = sabre_irq_build;
  230. irq_data = prom_early_alloc(sizeof(struct sabre_irq_data));
  231. regs = of_get_property(dp, "reg", NULL);
  232. irq_data->controller_regs = regs[0].phys_addr;
  233. busrange = of_get_property(dp, "bus-range", NULL);
  234. irq_data->pci_first_busno = busrange[0];
  235. dp->irq_trans->data = irq_data;
  236. }
  237. /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
  238. * imap/iclr registers are per-PBM.
  239. */
  240. #define SCHIZO_IMAP_BASE 0x1000UL
  241. #define SCHIZO_ICLR_BASE 0x1400UL
  242. static unsigned long schizo_imap_offset(unsigned long ino)
  243. {
  244. return SCHIZO_IMAP_BASE + (ino * 8UL);
  245. }
  246. static unsigned long schizo_iclr_offset(unsigned long ino)
  247. {
  248. return SCHIZO_ICLR_BASE + (ino * 8UL);
  249. }
  250. static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
  251. unsigned int ino)
  252. {
  253. return pbm_regs + schizo_iclr_offset(ino);
  254. }
  255. static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
  256. unsigned int ino)
  257. {
  258. return pbm_regs + schizo_imap_offset(ino);
  259. }
  260. #define schizo_read(__reg) \
  261. ({ u64 __ret; \
  262. __asm__ __volatile__("ldxa [%1] %2, %0" \
  263. : "=r" (__ret) \
  264. : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  265. : "memory"); \
  266. __ret; \
  267. })
  268. #define schizo_write(__reg, __val) \
  269. __asm__ __volatile__("stxa %0, [%1] %2" \
  270. : /* no outputs */ \
  271. : "r" (__val), "r" (__reg), \
  272. "i" (ASI_PHYS_BYPASS_EC_E) \
  273. : "memory")
  274. static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
  275. {
  276. unsigned long sync_reg = (unsigned long) _arg2;
  277. u64 mask = 1UL << (ino & IMAP_INO);
  278. u64 val;
  279. int limit;
  280. schizo_write(sync_reg, mask);
  281. limit = 100000;
  282. val = 0;
  283. while (--limit) {
  284. val = schizo_read(sync_reg);
  285. if (!(val & mask))
  286. break;
  287. }
  288. if (limit <= 0) {
  289. printk("tomatillo_wsync_handler: DMA won't sync [%llx:%llx]\n",
  290. val, mask);
  291. }
  292. if (_arg1) {
  293. static unsigned char cacheline[64]
  294. __attribute__ ((aligned (64)));
  295. __asm__ __volatile__("rd %%fprs, %0\n\t"
  296. "or %0, %4, %1\n\t"
  297. "wr %1, 0x0, %%fprs\n\t"
  298. "stda %%f0, [%5] %6\n\t"
  299. "wr %0, 0x0, %%fprs\n\t"
  300. "membar #Sync"
  301. : "=&r" (mask), "=&r" (val)
  302. : "0" (mask), "1" (val),
  303. "i" (FPRS_FEF), "r" (&cacheline[0]),
  304. "i" (ASI_BLK_COMMIT_P));
  305. }
  306. }
  307. struct schizo_irq_data {
  308. unsigned long pbm_regs;
  309. unsigned long sync_reg;
  310. u32 portid;
  311. int chip_version;
  312. };
  313. static unsigned int schizo_irq_build(struct device_node *dp,
  314. unsigned int ino,
  315. void *_data)
  316. {
  317. struct schizo_irq_data *irq_data = _data;
  318. unsigned long pbm_regs = irq_data->pbm_regs;
  319. unsigned long imap, iclr;
  320. int ign_fixup;
  321. int irq;
  322. int is_tomatillo;
  323. ino &= 0x3f;
  324. /* Now build the IRQ bucket. */
  325. imap = schizo_ino_to_imap(pbm_regs, ino);
  326. iclr = schizo_ino_to_iclr(pbm_regs, ino);
  327. /* On Schizo, no inofixup occurs. This is because each
  328. * INO has it's own IMAP register. On Psycho and Sabre
  329. * there is only one IMAP register for each PCI slot even
  330. * though four different INOs can be generated by each
  331. * PCI slot.
  332. *
  333. * But, for JBUS variants (essentially, Tomatillo), we have
  334. * to fixup the lowest bit of the interrupt group number.
  335. */
  336. ign_fixup = 0;
  337. is_tomatillo = (irq_data->sync_reg != 0UL);
  338. if (is_tomatillo) {
  339. if (irq_data->portid & 1)
  340. ign_fixup = (1 << 6);
  341. }
  342. irq = build_irq(ign_fixup, iclr, imap);
  343. if (is_tomatillo) {
  344. irq_install_pre_handler(irq,
  345. tomatillo_wsync_handler,
  346. ((irq_data->chip_version <= 4) ?
  347. (void *) 1 : (void *) 0),
  348. (void *) irq_data->sync_reg);
  349. }
  350. return irq;
  351. }
  352. static void __init __schizo_irq_trans_init(struct device_node *dp,
  353. int is_tomatillo)
  354. {
  355. const struct linux_prom64_registers *regs;
  356. struct schizo_irq_data *irq_data;
  357. dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
  358. dp->irq_trans->irq_build = schizo_irq_build;
  359. irq_data = prom_early_alloc(sizeof(struct schizo_irq_data));
  360. regs = of_get_property(dp, "reg", NULL);
  361. dp->irq_trans->data = irq_data;
  362. irq_data->pbm_regs = regs[0].phys_addr;
  363. if (is_tomatillo)
  364. irq_data->sync_reg = regs[3].phys_addr + 0x1a18UL;
  365. else
  366. irq_data->sync_reg = 0UL;
  367. irq_data->portid = of_getintprop_default(dp, "portid", 0);
  368. irq_data->chip_version = of_getintprop_default(dp, "version#", 0);
  369. }
  370. static void __init schizo_irq_trans_init(struct device_node *dp)
  371. {
  372. __schizo_irq_trans_init(dp, 0);
  373. }
  374. static void __init tomatillo_irq_trans_init(struct device_node *dp)
  375. {
  376. __schizo_irq_trans_init(dp, 1);
  377. }
  378. static unsigned int pci_sun4v_irq_build(struct device_node *dp,
  379. unsigned int devino,
  380. void *_data)
  381. {
  382. u32 devhandle = (u32) (unsigned long) _data;
  383. return sun4v_build_irq(devhandle, devino);
  384. }
  385. static void __init pci_sun4v_irq_trans_init(struct device_node *dp)
  386. {
  387. const struct linux_prom64_registers *regs;
  388. dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
  389. dp->irq_trans->irq_build = pci_sun4v_irq_build;
  390. regs = of_get_property(dp, "reg", NULL);
  391. dp->irq_trans->data = (void *) (unsigned long)
  392. ((regs->phys_addr >> 32UL) & 0x0fffffff);
  393. }
  394. struct fire_irq_data {
  395. unsigned long pbm_regs;
  396. u32 portid;
  397. };
  398. #define FIRE_IMAP_BASE 0x001000
  399. #define FIRE_ICLR_BASE 0x001400
  400. static unsigned long fire_imap_offset(unsigned long ino)
  401. {
  402. return FIRE_IMAP_BASE + (ino * 8UL);
  403. }
  404. static unsigned long fire_iclr_offset(unsigned long ino)
  405. {
  406. return FIRE_ICLR_BASE + (ino * 8UL);
  407. }
  408. static unsigned long fire_ino_to_iclr(unsigned long pbm_regs,
  409. unsigned int ino)
  410. {
  411. return pbm_regs + fire_iclr_offset(ino);
  412. }
  413. static unsigned long fire_ino_to_imap(unsigned long pbm_regs,
  414. unsigned int ino)
  415. {
  416. return pbm_regs + fire_imap_offset(ino);
  417. }
  418. static unsigned int fire_irq_build(struct device_node *dp,
  419. unsigned int ino,
  420. void *_data)
  421. {
  422. struct fire_irq_data *irq_data = _data;
  423. unsigned long pbm_regs = irq_data->pbm_regs;
  424. unsigned long imap, iclr;
  425. unsigned long int_ctrlr;
  426. ino &= 0x3f;
  427. /* Now build the IRQ bucket. */
  428. imap = fire_ino_to_imap(pbm_regs, ino);
  429. iclr = fire_ino_to_iclr(pbm_regs, ino);
  430. /* Set the interrupt controller number. */
  431. int_ctrlr = 1 << 6;
  432. upa_writeq(int_ctrlr, imap);
  433. /* The interrupt map registers do not have an INO field
  434. * like other chips do. They return zero in the INO
  435. * field, and the interrupt controller number is controlled
  436. * in bits 6 to 9. So in order for build_irq() to get
  437. * the INO right we pass it in as part of the fixup
  438. * which will get added to the map register zero value
  439. * read by build_irq().
  440. */
  441. ino |= (irq_data->portid << 6);
  442. ino -= int_ctrlr;
  443. return build_irq(ino, iclr, imap);
  444. }
  445. static void __init fire_irq_trans_init(struct device_node *dp)
  446. {
  447. const struct linux_prom64_registers *regs;
  448. struct fire_irq_data *irq_data;
  449. dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
  450. dp->irq_trans->irq_build = fire_irq_build;
  451. irq_data = prom_early_alloc(sizeof(struct fire_irq_data));
  452. regs = of_get_property(dp, "reg", NULL);
  453. dp->irq_trans->data = irq_data;
  454. irq_data->pbm_regs = regs[0].phys_addr;
  455. irq_data->portid = of_getintprop_default(dp, "portid", 0);
  456. }
  457. #endif /* CONFIG_PCI */
  458. #ifdef CONFIG_SBUS
  459. /* INO number to IMAP register offset for SYSIO external IRQ's.
  460. * This should conform to both Sunfire/Wildfire server and Fusion
  461. * desktop designs.
  462. */
  463. #define SYSIO_IMAP_SLOT0 0x2c00UL
  464. #define SYSIO_IMAP_SLOT1 0x2c08UL
  465. #define SYSIO_IMAP_SLOT2 0x2c10UL
  466. #define SYSIO_IMAP_SLOT3 0x2c18UL
  467. #define SYSIO_IMAP_SCSI 0x3000UL
  468. #define SYSIO_IMAP_ETH 0x3008UL
  469. #define SYSIO_IMAP_BPP 0x3010UL
  470. #define SYSIO_IMAP_AUDIO 0x3018UL
  471. #define SYSIO_IMAP_PFAIL 0x3020UL
  472. #define SYSIO_IMAP_KMS 0x3028UL
  473. #define SYSIO_IMAP_FLPY 0x3030UL
  474. #define SYSIO_IMAP_SHW 0x3038UL
  475. #define SYSIO_IMAP_KBD 0x3040UL
  476. #define SYSIO_IMAP_MS 0x3048UL
  477. #define SYSIO_IMAP_SER 0x3050UL
  478. #define SYSIO_IMAP_TIM0 0x3060UL
  479. #define SYSIO_IMAP_TIM1 0x3068UL
  480. #define SYSIO_IMAP_UE 0x3070UL
  481. #define SYSIO_IMAP_CE 0x3078UL
  482. #define SYSIO_IMAP_SBERR 0x3080UL
  483. #define SYSIO_IMAP_PMGMT 0x3088UL
  484. #define SYSIO_IMAP_GFX 0x3090UL
  485. #define SYSIO_IMAP_EUPA 0x3098UL
  486. #define bogon ((unsigned long) -1)
  487. static unsigned long sysio_irq_offsets[] = {
  488. /* SBUS Slot 0 --> 3, level 1 --> 7 */
  489. SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
  490. SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
  491. SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
  492. SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
  493. SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
  494. SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
  495. SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
  496. SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
  497. /* Onboard devices (not relevant/used on SunFire). */
  498. SYSIO_IMAP_SCSI,
  499. SYSIO_IMAP_ETH,
  500. SYSIO_IMAP_BPP,
  501. bogon,
  502. SYSIO_IMAP_AUDIO,
  503. SYSIO_IMAP_PFAIL,
  504. bogon,
  505. bogon,
  506. SYSIO_IMAP_KMS,
  507. SYSIO_IMAP_FLPY,
  508. SYSIO_IMAP_SHW,
  509. SYSIO_IMAP_KBD,
  510. SYSIO_IMAP_MS,
  511. SYSIO_IMAP_SER,
  512. bogon,
  513. bogon,
  514. SYSIO_IMAP_TIM0,
  515. SYSIO_IMAP_TIM1,
  516. bogon,
  517. bogon,
  518. SYSIO_IMAP_UE,
  519. SYSIO_IMAP_CE,
  520. SYSIO_IMAP_SBERR,
  521. SYSIO_IMAP_PMGMT,
  522. SYSIO_IMAP_GFX,
  523. SYSIO_IMAP_EUPA,
  524. };
  525. #undef bogon
  526. #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
  527. /* Convert Interrupt Mapping register pointer to associated
  528. * Interrupt Clear register pointer, SYSIO specific version.
  529. */
  530. #define SYSIO_ICLR_UNUSED0 0x3400UL
  531. #define SYSIO_ICLR_SLOT0 0x3408UL
  532. #define SYSIO_ICLR_SLOT1 0x3448UL
  533. #define SYSIO_ICLR_SLOT2 0x3488UL
  534. #define SYSIO_ICLR_SLOT3 0x34c8UL
  535. static unsigned long sysio_imap_to_iclr(unsigned long imap)
  536. {
  537. unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
  538. return imap + diff;
  539. }
  540. static unsigned int sbus_of_build_irq(struct device_node *dp,
  541. unsigned int ino,
  542. void *_data)
  543. {
  544. unsigned long reg_base = (unsigned long) _data;
  545. const struct linux_prom_registers *regs;
  546. unsigned long imap, iclr;
  547. int sbus_slot = 0;
  548. int sbus_level = 0;
  549. ino &= 0x3f;
  550. regs = of_get_property(dp, "reg", NULL);
  551. if (regs)
  552. sbus_slot = regs->which_io;
  553. if (ino < 0x20)
  554. ino += (sbus_slot * 8);
  555. imap = sysio_irq_offsets[ino];
  556. if (imap == ((unsigned long)-1)) {
  557. prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
  558. ino);
  559. prom_halt();
  560. }
  561. imap += reg_base;
  562. /* SYSIO inconsistency. For external SLOTS, we have to select
  563. * the right ICLR register based upon the lower SBUS irq level
  564. * bits.
  565. */
  566. if (ino >= 0x20) {
  567. iclr = sysio_imap_to_iclr(imap);
  568. } else {
  569. sbus_level = ino & 0x7;
  570. switch(sbus_slot) {
  571. case 0:
  572. iclr = reg_base + SYSIO_ICLR_SLOT0;
  573. break;
  574. case 1:
  575. iclr = reg_base + SYSIO_ICLR_SLOT1;
  576. break;
  577. case 2:
  578. iclr = reg_base + SYSIO_ICLR_SLOT2;
  579. break;
  580. default:
  581. case 3:
  582. iclr = reg_base + SYSIO_ICLR_SLOT3;
  583. break;
  584. }
  585. iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
  586. }
  587. return build_irq(sbus_level, iclr, imap);
  588. }
  589. static void __init sbus_irq_trans_init(struct device_node *dp)
  590. {
  591. const struct linux_prom64_registers *regs;
  592. dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
  593. dp->irq_trans->irq_build = sbus_of_build_irq;
  594. regs = of_get_property(dp, "reg", NULL);
  595. dp->irq_trans->data = (void *) (unsigned long) regs->phys_addr;
  596. }
  597. #endif /* CONFIG_SBUS */
  598. static unsigned int central_build_irq(struct device_node *dp,
  599. unsigned int ino,
  600. void *_data)
  601. {
  602. struct device_node *central_dp = _data;
  603. struct platform_device *central_op = of_find_device_by_node(central_dp);
  604. struct resource *res;
  605. unsigned long imap, iclr;
  606. u32 tmp;
  607. if (of_node_name_eq(dp, "eeprom")) {
  608. res = &central_op->resource[5];
  609. } else if (of_node_name_eq(dp, "zs")) {
  610. res = &central_op->resource[4];
  611. } else if (of_node_name_eq(dp, "clock-board")) {
  612. res = &central_op->resource[3];
  613. } else {
  614. return ino;
  615. }
  616. imap = res->start + 0x00UL;
  617. iclr = res->start + 0x10UL;
  618. /* Set the INO state to idle, and disable. */
  619. upa_writel(0, iclr);
  620. upa_readl(iclr);
  621. tmp = upa_readl(imap);
  622. tmp &= ~0x80000000;
  623. upa_writel(tmp, imap);
  624. return build_irq(0, iclr, imap);
  625. }
  626. static void __init central_irq_trans_init(struct device_node *dp)
  627. {
  628. dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
  629. dp->irq_trans->irq_build = central_build_irq;
  630. dp->irq_trans->data = dp;
  631. }
  632. struct irq_trans {
  633. const char *name;
  634. void (*init)(struct device_node *);
  635. };
  636. #ifdef CONFIG_PCI
  637. static struct irq_trans __initdata pci_irq_trans_table[] = {
  638. { "SUNW,sabre", sabre_irq_trans_init },
  639. { "pci108e,a000", sabre_irq_trans_init },
  640. { "pci108e,a001", sabre_irq_trans_init },
  641. { "SUNW,psycho", psycho_irq_trans_init },
  642. { "pci108e,8000", psycho_irq_trans_init },
  643. { "SUNW,schizo", schizo_irq_trans_init },
  644. { "pci108e,8001", schizo_irq_trans_init },
  645. { "SUNW,schizo+", schizo_irq_trans_init },
  646. { "pci108e,8002", schizo_irq_trans_init },
  647. { "SUNW,tomatillo", tomatillo_irq_trans_init },
  648. { "pci108e,a801", tomatillo_irq_trans_init },
  649. { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
  650. { "pciex108e,80f0", fire_irq_trans_init },
  651. };
  652. #endif
  653. static unsigned int sun4v_vdev_irq_build(struct device_node *dp,
  654. unsigned int devino,
  655. void *_data)
  656. {
  657. u32 devhandle = (u32) (unsigned long) _data;
  658. return sun4v_build_irq(devhandle, devino);
  659. }
  660. static void __init sun4v_vdev_irq_trans_init(struct device_node *dp)
  661. {
  662. const struct linux_prom64_registers *regs;
  663. dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
  664. dp->irq_trans->irq_build = sun4v_vdev_irq_build;
  665. regs = of_get_property(dp, "reg", NULL);
  666. dp->irq_trans->data = (void *) (unsigned long)
  667. ((regs->phys_addr >> 32UL) & 0x0fffffff);
  668. }
  669. void __init irq_trans_init(struct device_node *dp)
  670. {
  671. #ifdef CONFIG_PCI
  672. const char *model;
  673. int i;
  674. #endif
  675. #ifdef CONFIG_PCI
  676. model = of_get_property(dp, "model", NULL);
  677. if (!model)
  678. model = of_get_property(dp, "compatible", NULL);
  679. if (model) {
  680. for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) {
  681. struct irq_trans *t = &pci_irq_trans_table[i];
  682. if (!strcmp(model, t->name)) {
  683. t->init(dp);
  684. return;
  685. }
  686. }
  687. }
  688. #endif
  689. #ifdef CONFIG_SBUS
  690. if (of_node_name_eq(dp, "sbus") ||
  691. of_node_name_eq(dp, "sbi")) {
  692. sbus_irq_trans_init(dp);
  693. return;
  694. }
  695. #endif
  696. if (of_node_name_eq(dp, "fhc") &&
  697. of_node_name_eq(dp->parent, "central")) {
  698. central_irq_trans_init(dp);
  699. return;
  700. }
  701. if (of_node_name_eq(dp, "virtual-devices") ||
  702. of_node_name_eq(dp, "niu")) {
  703. sun4v_vdev_irq_trans_init(dp);
  704. return;
  705. }
  706. }