pcic.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * pcic.c: MicroSPARC-IIep PCI controller support
  4. *
  5. * Copyright (C) 1998 V. Roganov and G. Raiko
  6. *
  7. * Code is derived from Ultra/PCI PSYCHO controller support, see that
  8. * for author info.
  9. *
  10. * Support for diverse IIep based platforms by Pete Zaitcev.
  11. * CP-1200 by Eric Brower.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/init.h>
  16. #include <linux/mm.h>
  17. #include <linux/slab.h>
  18. #include <linux/jiffies.h>
  19. #include <asm/swift.h> /* for cache flushing. */
  20. #include <asm/io.h>
  21. #include <linux/ctype.h>
  22. #include <linux/pci.h>
  23. #include <linux/time.h>
  24. #include <linux/timex.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/export.h>
  27. #include <asm/irq.h>
  28. #include <asm/oplib.h>
  29. #include <asm/prom.h>
  30. #include <asm/pcic.h>
  31. #include <asm/timex.h>
  32. #include <asm/timer.h>
  33. #include <linux/uaccess.h>
  34. #include <asm/irq_regs.h>
  35. #include "kernel.h"
  36. #include "irq.h"
  37. /*
  38. * I studied different documents and many live PROMs both from 2.30
  39. * family and 3.xx versions. I came to the amazing conclusion: there is
  40. * absolutely no way to route interrupts in IIep systems relying on
  41. * information which PROM presents. We must hardcode interrupt routing
  42. * schematics. And this actually sucks. -- zaitcev 1999/05/12
  43. *
  44. * To find irq for a device we determine which routing map
  45. * is in effect or, in other words, on which machine we are running.
  46. * We use PROM name for this although other techniques may be used
  47. * in special cases (Gleb reports a PROMless IIep based system).
  48. * Once we know the map we take device configuration address and
  49. * find PCIC pin number where INT line goes. Then we may either program
  50. * preferred irq into the PCIC or supply the preexisting irq to the device.
  51. */
  52. struct pcic_ca2irq {
  53. unsigned char busno; /* PCI bus number */
  54. unsigned char devfn; /* Configuration address */
  55. unsigned char pin; /* PCIC external interrupt pin */
  56. unsigned char irq; /* Preferred IRQ (mappable in PCIC) */
  57. unsigned int force; /* Enforce preferred IRQ */
  58. };
  59. struct pcic_sn2list {
  60. char *sysname;
  61. struct pcic_ca2irq *intmap;
  62. int mapdim;
  63. };
  64. /*
  65. * JavaEngine-1 apparently has different versions.
  66. *
  67. * According to communications with Sun folks, for P2 build 501-4628-03:
  68. * pin 0 - parallel, audio;
  69. * pin 1 - Ethernet;
  70. * pin 2 - su;
  71. * pin 3 - PS/2 kbd and mouse.
  72. *
  73. * OEM manual (805-1486):
  74. * pin 0: Ethernet
  75. * pin 1: All EBus
  76. * pin 2: IGA (unused)
  77. * pin 3: Not connected
  78. * OEM manual says that 501-4628 & 501-4811 are the same thing,
  79. * only the latter has NAND flash in place.
  80. *
  81. * So far unofficial Sun wins over the OEM manual. Poor OEMs...
  82. */
  83. static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */
  84. { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */
  85. { 0, 0x01, 1, 6, 1 }, /* Happy Meal */
  86. { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */
  87. };
  88. /* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
  89. static struct pcic_ca2irq pcic_i_jse[] = {
  90. { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
  91. { 0, 0x01, 1, 6, 0 }, /* hme */
  92. { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */
  93. { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */
  94. { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */
  95. { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */
  96. { 0, 0x80, 5, 11, 0 }, /* EIDE */
  97. /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
  98. { 0, 0xA0, 4, 9, 0 }, /* USB */
  99. /*
  100. * Some pins belong to non-PCI devices, we hardcode them in drivers.
  101. * sun4m timers - irq 10, 14
  102. * PC style RTC - pin 7, irq 4 ?
  103. * Smart card, Parallel - pin 4 shared with USB, ISA
  104. * audio - pin 3, irq 5 ?
  105. */
  106. };
  107. /* SPARCengine-6 was the original release name of CP1200.
  108. * The documentation differs between the two versions
  109. */
  110. static struct pcic_ca2irq pcic_i_se6[] = {
  111. { 0, 0x08, 0, 2, 0 }, /* SCSI */
  112. { 0, 0x01, 1, 6, 0 }, /* HME */
  113. { 0, 0x00, 3, 13, 0 }, /* EBus */
  114. };
  115. /*
  116. * Krups (courtesy of Varol Kaptan)
  117. * No documentation available, but it was easy to guess
  118. * because it was very similar to Espresso.
  119. *
  120. * pin 0 - kbd, mouse, serial;
  121. * pin 1 - Ethernet;
  122. * pin 2 - igs (we do not use it);
  123. * pin 3 - audio;
  124. * pin 4,5,6 - unused;
  125. * pin 7 - RTC (from P2 onwards as David B. says).
  126. */
  127. static struct pcic_ca2irq pcic_i_jk[] = {
  128. { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
  129. { 0, 0x01, 1, 6, 0 }, /* hme */
  130. };
  131. /*
  132. * Several entries in this list may point to the same routing map
  133. * as several PROMs may be installed on the same physical board.
  134. */
  135. #define SN2L_INIT(name, map) \
  136. { name, map, ARRAY_SIZE(map) }
  137. static struct pcic_sn2list pcic_known_sysnames[] = {
  138. SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */
  139. SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */
  140. SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
  141. SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */
  142. SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */
  143. { NULL, NULL, 0 }
  144. };
  145. /*
  146. * Only one PCIC per IIep,
  147. * and since we have no SMP IIep, only one per system.
  148. */
  149. static int pcic0_up;
  150. static struct linux_pcic pcic0;
  151. void __iomem *pcic_regs;
  152. static volatile int pcic_speculative;
  153. static volatile int pcic_trapped;
  154. /* forward */
  155. unsigned int pcic_build_device_irq(struct platform_device *op,
  156. unsigned int real_irq);
  157. #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
  158. static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
  159. int where, u32 *value)
  160. {
  161. struct linux_pcic *pcic;
  162. unsigned long flags;
  163. pcic = &pcic0;
  164. local_irq_save(flags);
  165. #if 0 /* does not fail here */
  166. pcic_speculative = 1;
  167. pcic_trapped = 0;
  168. #endif
  169. writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
  170. #if 0 /* does not fail here */
  171. nop();
  172. if (pcic_trapped) {
  173. local_irq_restore(flags);
  174. *value = ~0;
  175. return 0;
  176. }
  177. #endif
  178. pcic_speculative = 2;
  179. pcic_trapped = 0;
  180. *value = readl(pcic->pcic_config_space_data + (where&4));
  181. nop();
  182. if (pcic_trapped) {
  183. pcic_speculative = 0;
  184. local_irq_restore(flags);
  185. *value = ~0;
  186. return 0;
  187. }
  188. pcic_speculative = 0;
  189. local_irq_restore(flags);
  190. return 0;
  191. }
  192. static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
  193. int where, int size, u32 *val)
  194. {
  195. unsigned int v;
  196. if (bus->number != 0) return -EINVAL;
  197. switch (size) {
  198. case 1:
  199. pcic_read_config_dword(bus->number, devfn, where&~3, &v);
  200. *val = 0xff & (v >> (8*(where & 3)));
  201. return 0;
  202. case 2:
  203. if (where&1) return -EINVAL;
  204. pcic_read_config_dword(bus->number, devfn, where&~3, &v);
  205. *val = 0xffff & (v >> (8*(where & 3)));
  206. return 0;
  207. case 4:
  208. if (where&3) return -EINVAL;
  209. pcic_read_config_dword(bus->number, devfn, where&~3, val);
  210. return 0;
  211. }
  212. return -EINVAL;
  213. }
  214. static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
  215. int where, u32 value)
  216. {
  217. struct linux_pcic *pcic;
  218. unsigned long flags;
  219. pcic = &pcic0;
  220. local_irq_save(flags);
  221. writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
  222. writel(value, pcic->pcic_config_space_data + (where&4));
  223. local_irq_restore(flags);
  224. return 0;
  225. }
  226. static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
  227. int where, int size, u32 val)
  228. {
  229. unsigned int v;
  230. if (bus->number != 0) return -EINVAL;
  231. switch (size) {
  232. case 1:
  233. pcic_read_config_dword(bus->number, devfn, where&~3, &v);
  234. v = (v & ~(0xff << (8*(where&3)))) |
  235. ((0xff&val) << (8*(where&3)));
  236. return pcic_write_config_dword(bus->number, devfn, where&~3, v);
  237. case 2:
  238. if (where&1) return -EINVAL;
  239. pcic_read_config_dword(bus->number, devfn, where&~3, &v);
  240. v = (v & ~(0xffff << (8*(where&3)))) |
  241. ((0xffff&val) << (8*(where&3)));
  242. return pcic_write_config_dword(bus->number, devfn, where&~3, v);
  243. case 4:
  244. if (where&3) return -EINVAL;
  245. return pcic_write_config_dword(bus->number, devfn, where, val);
  246. }
  247. return -EINVAL;
  248. }
  249. static struct pci_ops pcic_ops = {
  250. .read = pcic_read_config,
  251. .write = pcic_write_config,
  252. };
  253. /*
  254. * On sparc64 pcibios_init() calls pci_controller_probe().
  255. * We want PCIC probed little ahead so that interrupt controller
  256. * would be operational.
  257. */
  258. int __init pcic_probe(void)
  259. {
  260. struct linux_pcic *pcic;
  261. struct linux_prom_registers regs[PROMREG_MAX];
  262. struct linux_pbm_info* pbm;
  263. char namebuf[64];
  264. phandle node;
  265. int err;
  266. if (pcic0_up) {
  267. prom_printf("PCIC: called twice!\n");
  268. prom_halt();
  269. }
  270. pcic = &pcic0;
  271. node = prom_getchild (prom_root_node);
  272. node = prom_searchsiblings (node, "pci");
  273. if (node == 0)
  274. return -ENODEV;
  275. /*
  276. * Map in PCIC register set, config space, and IO base
  277. */
  278. err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
  279. if (err == 0 || err == -1) {
  280. prom_printf("PCIC: Error, cannot get PCIC registers "
  281. "from PROM.\n");
  282. prom_halt();
  283. }
  284. pcic0_up = 1;
  285. pcic->pcic_res_regs.name = "pcic_registers";
  286. pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
  287. if (!pcic->pcic_regs) {
  288. prom_printf("PCIC: Error, cannot map PCIC registers.\n");
  289. prom_halt();
  290. }
  291. pcic->pcic_res_io.name = "pcic_io";
  292. if ((pcic->pcic_io = (unsigned long)
  293. ioremap(regs[1].phys_addr, 0x10000)) == 0) {
  294. prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
  295. prom_halt();
  296. }
  297. pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
  298. if ((pcic->pcic_config_space_addr =
  299. ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == NULL) {
  300. prom_printf("PCIC: Error, cannot map "
  301. "PCI Configuration Space Address.\n");
  302. prom_halt();
  303. }
  304. /*
  305. * Docs say three least significant bits in address and data
  306. * must be the same. Thus, we need adjust size of data.
  307. */
  308. pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
  309. if ((pcic->pcic_config_space_data =
  310. ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == NULL) {
  311. prom_printf("PCIC: Error, cannot map "
  312. "PCI Configuration Space Data.\n");
  313. prom_halt();
  314. }
  315. pbm = &pcic->pbm;
  316. pbm->prom_node = node;
  317. prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
  318. strcpy(pbm->prom_name, namebuf);
  319. {
  320. extern int pcic_nmi_trap_patch[4];
  321. t_nmi[0] = pcic_nmi_trap_patch[0];
  322. t_nmi[1] = pcic_nmi_trap_patch[1];
  323. t_nmi[2] = pcic_nmi_trap_patch[2];
  324. t_nmi[3] = pcic_nmi_trap_patch[3];
  325. swift_flush_dcache();
  326. pcic_regs = pcic->pcic_regs;
  327. }
  328. prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0;
  329. {
  330. struct pcic_sn2list *p;
  331. for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
  332. if (strcmp(namebuf, p->sysname) == 0)
  333. break;
  334. }
  335. pcic->pcic_imap = p->intmap;
  336. pcic->pcic_imdim = p->mapdim;
  337. }
  338. if (pcic->pcic_imap == NULL) {
  339. /*
  340. * We do not panic here for the sake of embedded systems.
  341. */
  342. printk("PCIC: System %s is unknown, cannot route interrupts\n",
  343. namebuf);
  344. }
  345. return 0;
  346. }
  347. static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
  348. {
  349. struct linux_pbm_info *pbm = &pcic->pbm;
  350. pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
  351. if (!pbm->pci_bus)
  352. return;
  353. #if 0 /* deadwood transplanted from sparc64 */
  354. pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
  355. pci_record_assignments(pbm, pbm->pci_bus);
  356. pci_assign_unassigned(pbm, pbm->pci_bus);
  357. pci_fixup_irq(pbm, pbm->pci_bus);
  358. #endif
  359. pci_bus_add_devices(pbm->pci_bus);
  360. }
  361. /*
  362. * Main entry point from the PCI subsystem.
  363. */
  364. static int __init pcic_init(void)
  365. {
  366. struct linux_pcic *pcic;
  367. /*
  368. * PCIC should be initialized at start of the timer.
  369. * So, here we report the presence of PCIC and do some magic passes.
  370. */
  371. if(!pcic0_up)
  372. return 0;
  373. pcic = &pcic0;
  374. /*
  375. * Switch off IOTLB translation.
  376. */
  377. writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
  378. pcic->pcic_regs+PCI_DVMA_CONTROL);
  379. /*
  380. * Increase mapped size for PCI memory space (DMA access).
  381. * Should be done in that order (size first, address second).
  382. * Why we couldn't set up 4GB and forget about it? XXX
  383. */
  384. writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
  385. writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
  386. pcic->pcic_regs+PCI_BASE_ADDRESS_0);
  387. pcic_pbm_scan_bus(pcic);
  388. return 0;
  389. }
  390. int pcic_present(void)
  391. {
  392. return pcic0_up;
  393. }
  394. static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev)
  395. {
  396. struct linux_prom_pci_registers regs[PROMREG_MAX];
  397. int err;
  398. phandle node = prom_getchild(pbm->prom_node);
  399. while(node) {
  400. err = prom_getproperty(node, "reg",
  401. (char *)&regs[0], sizeof(regs));
  402. if(err != 0 && err != -1) {
  403. unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
  404. if(devfn == pdev->devfn)
  405. return node;
  406. }
  407. node = prom_getsibling(node);
  408. }
  409. return 0;
  410. }
  411. static inline struct pcidev_cookie *pci_devcookie_alloc(void)
  412. {
  413. return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
  414. }
  415. static void pcic_map_pci_device(struct linux_pcic *pcic,
  416. struct pci_dev *dev, int node)
  417. {
  418. char namebuf[64];
  419. unsigned long address;
  420. unsigned long flags;
  421. int j;
  422. if (node == 0 || node == -1) {
  423. strcpy(namebuf, "???");
  424. } else {
  425. prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
  426. }
  427. for (j = 0; j < 6; j++) {
  428. address = dev->resource[j].start;
  429. if (address == 0) break; /* are sequential */
  430. flags = dev->resource[j].flags;
  431. if ((flags & IORESOURCE_IO) != 0) {
  432. if (address < 0x10000) {
  433. /*
  434. * A device responds to I/O cycles on PCI.
  435. * We generate these cycles with memory
  436. * access into the fixed map (phys 0x30000000).
  437. *
  438. * Since a device driver does not want to
  439. * do ioremap() before accessing PC-style I/O,
  440. * we supply virtual, ready to access address.
  441. *
  442. * Note that request_region()
  443. * works for these devices.
  444. *
  445. * XXX Neat trick, but it's a *bad* idea
  446. * to shit into regions like that.
  447. * What if we want to allocate one more
  448. * PCI base address...
  449. */
  450. dev->resource[j].start =
  451. pcic->pcic_io + address;
  452. dev->resource[j].end = 1; /* XXX */
  453. dev->resource[j].flags =
  454. (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
  455. } else {
  456. /*
  457. * OOPS... PCI Spec allows this. Sun does
  458. * not have any devices getting above 64K
  459. * so it must be user with a weird I/O
  460. * board in a PCI slot. We must remap it
  461. * under 64K but it is not done yet. XXX
  462. */
  463. pci_info(dev, "PCIC: Skipping I/O space at "
  464. "0x%lx, this will Oops if a driver "
  465. "attaches device '%s'\n", address,
  466. namebuf);
  467. }
  468. }
  469. }
  470. }
  471. static void
  472. pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
  473. {
  474. struct pcic_ca2irq *p;
  475. unsigned int real_irq;
  476. int i, ivec;
  477. char namebuf[64];
  478. if (node == 0 || node == -1) {
  479. strcpy(namebuf, "???");
  480. } else {
  481. prom_getstring(node, "name", namebuf, sizeof(namebuf));
  482. }
  483. if ((p = pcic->pcic_imap) == NULL) {
  484. dev->irq = 0;
  485. return;
  486. }
  487. for (i = 0; i < pcic->pcic_imdim; i++) {
  488. if (p->busno == dev->bus->number && p->devfn == dev->devfn)
  489. break;
  490. p++;
  491. }
  492. if (i >= pcic->pcic_imdim) {
  493. pci_info(dev, "PCIC: device %s not found in %d\n", namebuf,
  494. pcic->pcic_imdim);
  495. dev->irq = 0;
  496. return;
  497. }
  498. i = p->pin;
  499. if (i >= 0 && i < 4) {
  500. ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
  501. real_irq = ivec >> (i << 2) & 0xF;
  502. } else if (i >= 4 && i < 8) {
  503. ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
  504. real_irq = ivec >> ((i-4) << 2) & 0xF;
  505. } else { /* Corrupted map */
  506. pci_info(dev, "PCIC: BAD PIN %d\n", i); for (;;) {}
  507. }
  508. /* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
  509. /* real_irq means PROM did not bother to program the upper
  510. * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
  511. */
  512. if (real_irq == 0 || p->force) {
  513. if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */
  514. pci_info(dev, "PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
  515. }
  516. pci_info(dev, "PCIC: setting irq %d at pin %d\n", p->irq,
  517. p->pin);
  518. real_irq = p->irq;
  519. i = p->pin;
  520. if (i >= 4) {
  521. ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
  522. ivec &= ~(0xF << ((i - 4) << 2));
  523. ivec |= p->irq << ((i - 4) << 2);
  524. writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
  525. } else {
  526. ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
  527. ivec &= ~(0xF << (i << 2));
  528. ivec |= p->irq << (i << 2);
  529. writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
  530. }
  531. }
  532. dev->irq = pcic_build_device_irq(NULL, real_irq);
  533. }
  534. /*
  535. * Normally called from {do_}pci_scan_bus...
  536. */
  537. void pcibios_fixup_bus(struct pci_bus *bus)
  538. {
  539. struct pci_dev *dev;
  540. struct linux_pcic *pcic;
  541. /* struct linux_pbm_info* pbm = &pcic->pbm; */
  542. int node;
  543. struct pcidev_cookie *pcp;
  544. if (!pcic0_up) {
  545. pci_info(bus, "pcibios_fixup_bus: no PCIC\n");
  546. return;
  547. }
  548. pcic = &pcic0;
  549. /*
  550. * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
  551. */
  552. if (bus->number != 0) {
  553. pci_info(bus, "pcibios_fixup_bus: nonzero bus 0x%x\n",
  554. bus->number);
  555. return;
  556. }
  557. list_for_each_entry(dev, &bus->devices, bus_list) {
  558. node = pdev_to_pnode(&pcic->pbm, dev);
  559. if(node == 0)
  560. node = -1;
  561. /* cookies */
  562. pcp = pci_devcookie_alloc();
  563. pcp->pbm = &pcic->pbm;
  564. pcp->prom_node = of_find_node_by_phandle(node);
  565. dev->sysdata = pcp;
  566. /* fixing I/O to look like memory */
  567. if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
  568. pcic_map_pci_device(pcic, dev, node);
  569. pcic_fill_irq(pcic, dev, node);
  570. }
  571. }
  572. int pcibios_enable_device(struct pci_dev *dev, int mask)
  573. {
  574. u16 cmd, oldcmd;
  575. int i;
  576. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  577. oldcmd = cmd;
  578. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  579. struct resource *res = &dev->resource[i];
  580. /* Only set up the requested stuff */
  581. if (!(mask & (1<<i)))
  582. continue;
  583. if (res->flags & IORESOURCE_IO)
  584. cmd |= PCI_COMMAND_IO;
  585. if (res->flags & IORESOURCE_MEM)
  586. cmd |= PCI_COMMAND_MEMORY;
  587. }
  588. if (cmd != oldcmd) {
  589. pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
  590. pci_write_config_word(dev, PCI_COMMAND, cmd);
  591. }
  592. return 0;
  593. }
  594. /* Makes compiler happy */
  595. static volatile int pcic_timer_dummy;
  596. static void pcic_clear_clock_irq(void)
  597. {
  598. pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
  599. }
  600. /* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
  601. #define USECS_PER_JIFFY (1000000 / HZ)
  602. #define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
  603. static unsigned int pcic_cycles_offset(void)
  604. {
  605. u32 value, count;
  606. value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
  607. count = value & ~PCI_SYS_COUNTER_OVERFLOW;
  608. if (value & PCI_SYS_COUNTER_OVERFLOW)
  609. count += TICK_TIMER_LIMIT;
  610. /*
  611. * We divide all by HZ
  612. * to have microsecond resolution and to avoid overflow
  613. */
  614. count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
  615. /* Coordinate with the sparc_config.clock_rate setting */
  616. return count * 2;
  617. }
  618. void __init pci_time_init(void)
  619. {
  620. struct linux_pcic *pcic = &pcic0;
  621. unsigned long v;
  622. int timer_irq, irq;
  623. int err;
  624. #ifndef CONFIG_SMP
  625. /*
  626. * The clock_rate is in SBUS dimension.
  627. * We take into account this in pcic_cycles_offset()
  628. */
  629. sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
  630. sparc_config.features |= FEAT_L10_CLOCKEVENT;
  631. #endif
  632. sparc_config.features |= FEAT_L10_CLOCKSOURCE;
  633. sparc_config.get_cycles_offset = pcic_cycles_offset;
  634. writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
  635. /* PROM should set appropriate irq */
  636. v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
  637. timer_irq = PCI_COUNTER_IRQ_SYS(v);
  638. writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
  639. pcic->pcic_regs+PCI_COUNTER_IRQ);
  640. irq = pcic_build_device_irq(NULL, timer_irq);
  641. err = request_irq(irq, timer_interrupt,
  642. IRQF_TIMER, "timer", NULL);
  643. if (err) {
  644. prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
  645. prom_halt();
  646. }
  647. local_irq_enable();
  648. }
  649. #if 0
  650. static void watchdog_reset() {
  651. writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
  652. }
  653. #endif
  654. /*
  655. * NMI
  656. */
  657. void pcic_nmi(unsigned int pend, struct pt_regs *regs)
  658. {
  659. pend = swab32(pend);
  660. if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
  661. /*
  662. * XXX On CP-1200 PCI #SERR may happen, we do not know
  663. * what to do about it yet.
  664. */
  665. printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
  666. pend, (int)regs->pc, pcic_speculative);
  667. for (;;) { }
  668. }
  669. pcic_speculative = 0;
  670. pcic_trapped = 1;
  671. regs->pc = regs->npc;
  672. regs->npc += 4;
  673. }
  674. static inline unsigned long get_irqmask(int irq_nr)
  675. {
  676. return 1 << irq_nr;
  677. }
  678. static void pcic_mask_irq(struct irq_data *data)
  679. {
  680. unsigned long mask, flags;
  681. mask = (unsigned long)data->chip_data;
  682. local_irq_save(flags);
  683. writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
  684. local_irq_restore(flags);
  685. }
  686. static void pcic_unmask_irq(struct irq_data *data)
  687. {
  688. unsigned long mask, flags;
  689. mask = (unsigned long)data->chip_data;
  690. local_irq_save(flags);
  691. writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
  692. local_irq_restore(flags);
  693. }
  694. static unsigned int pcic_startup_irq(struct irq_data *data)
  695. {
  696. irq_link(data->irq);
  697. pcic_unmask_irq(data);
  698. return 0;
  699. }
  700. static struct irq_chip pcic_irq = {
  701. .name = "pcic",
  702. .irq_startup = pcic_startup_irq,
  703. .irq_mask = pcic_mask_irq,
  704. .irq_unmask = pcic_unmask_irq,
  705. };
  706. unsigned int pcic_build_device_irq(struct platform_device *op,
  707. unsigned int real_irq)
  708. {
  709. unsigned int irq;
  710. unsigned long mask;
  711. irq = 0;
  712. mask = get_irqmask(real_irq);
  713. if (mask == 0)
  714. goto out;
  715. irq = irq_alloc(real_irq, real_irq);
  716. if (irq == 0)
  717. goto out;
  718. irq_set_chip_and_handler_name(irq, &pcic_irq,
  719. handle_level_irq, "PCIC");
  720. irq_set_chip_data(irq, (void *)mask);
  721. out:
  722. return irq;
  723. }
  724. static void pcic_load_profile_irq(int cpu, unsigned int limit)
  725. {
  726. printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
  727. }
  728. void __init sun4m_pci_init_IRQ(void)
  729. {
  730. sparc_config.build_device_irq = pcic_build_device_irq;
  731. sparc_config.clear_clock_irq = pcic_clear_clock_irq;
  732. sparc_config.load_profile_irq = pcic_load_profile_irq;
  733. }
  734. subsys_initcall(pcic_init);