pci_schizo.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net)
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/types.h>
  8. #include <linux/pci.h>
  9. #include <linux/init.h>
  10. #include <linux/slab.h>
  11. #include <linux/export.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/of_device.h>
  14. #include <linux/numa.h>
  15. #include <asm/iommu.h>
  16. #include <asm/irq.h>
  17. #include <asm/pstate.h>
  18. #include <asm/prom.h>
  19. #include <asm/upa.h>
  20. #include "pci_impl.h"
  21. #include "iommu_common.h"
  22. #define DRIVER_NAME "schizo"
  23. #define PFX DRIVER_NAME ": "
  24. /* This is a convention that at least Excalibur and Merlin
  25. * follow. I suppose the SCHIZO used in Starcat and friends
  26. * will do similar.
  27. *
  28. * The only way I could see this changing is if the newlink
  29. * block requires more space in Schizo's address space than
  30. * they predicted, thus requiring an address space reorg when
  31. * the newer Schizo is taped out.
  32. */
  33. /* Streaming buffer control register. */
  34. #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
  35. #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
  36. #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
  37. #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
  38. #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
  39. /* IOMMU control register. */
  40. #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
  41. #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
  42. #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
  43. #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
  44. #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
  45. #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
  46. #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
  47. #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
  48. #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
  49. #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
  50. #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
  51. #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
  52. #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
  53. #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
  54. #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
  55. #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
  56. #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
  57. #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
  58. /* Schizo config space address format is nearly identical to
  59. * that of PSYCHO:
  60. *
  61. * 32 24 23 16 15 11 10 8 7 2 1 0
  62. * ---------------------------------------------------------
  63. * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
  64. * ---------------------------------------------------------
  65. */
  66. #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
  67. #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
  68. (((unsigned long)(BUS) << 16) | \
  69. ((unsigned long)(DEVFN) << 8) | \
  70. ((unsigned long)(REG)))
  71. static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
  72. unsigned char bus,
  73. unsigned int devfn,
  74. int where)
  75. {
  76. if (!pbm)
  77. return NULL;
  78. bus -= pbm->pci_first_busno;
  79. return (void *)
  80. (SCHIZO_CONFIG_BASE(pbm) |
  81. SCHIZO_CONFIG_ENCODE(bus, devfn, where));
  82. }
  83. /* SCHIZO error handling support. */
  84. enum schizo_error_type {
  85. UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
  86. };
  87. static DEFINE_SPINLOCK(stc_buf_lock);
  88. static unsigned long stc_error_buf[128];
  89. static unsigned long stc_tag_buf[16];
  90. static unsigned long stc_line_buf[16];
  91. #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
  92. #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
  93. #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
  94. #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
  95. #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
  96. #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
  97. #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
  98. #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
  99. #define SCHIZO_STCERR_WRITE 0x2UL
  100. #define SCHIZO_STCERR_READ 0x1UL
  101. #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
  102. #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
  103. #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
  104. #define SCHIZO_STCTAG_READ 0x4000000000000000UL
  105. #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
  106. #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
  107. #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
  108. #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
  109. #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
  110. #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
  111. static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
  112. enum schizo_error_type type)
  113. {
  114. struct strbuf *strbuf = &pbm->stc;
  115. unsigned long regbase = pbm->pbm_regs;
  116. unsigned long err_base, tag_base, line_base;
  117. u64 control;
  118. int i;
  119. err_base = regbase + SCHIZO_STC_ERR;
  120. tag_base = regbase + SCHIZO_STC_TAG;
  121. line_base = regbase + SCHIZO_STC_LINE;
  122. spin_lock(&stc_buf_lock);
  123. /* This is __REALLY__ dangerous. When we put the
  124. * streaming buffer into diagnostic mode to probe
  125. * it's tags and error status, we _must_ clear all
  126. * of the line tag valid bits before re-enabling
  127. * the streaming buffer. If any dirty data lives
  128. * in the STC when we do this, we will end up
  129. * invalidating it before it has a chance to reach
  130. * main memory.
  131. */
  132. control = upa_readq(strbuf->strbuf_control);
  133. upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB),
  134. strbuf->strbuf_control);
  135. for (i = 0; i < 128; i++) {
  136. unsigned long val;
  137. val = upa_readq(err_base + (i * 8UL));
  138. upa_writeq(0UL, err_base + (i * 8UL));
  139. stc_error_buf[i] = val;
  140. }
  141. for (i = 0; i < 16; i++) {
  142. stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
  143. stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
  144. upa_writeq(0UL, tag_base + (i * 8UL));
  145. upa_writeq(0UL, line_base + (i * 8UL));
  146. }
  147. /* OK, state is logged, exit diagnostic mode. */
  148. upa_writeq(control, strbuf->strbuf_control);
  149. for (i = 0; i < 16; i++) {
  150. int j, saw_error, first, last;
  151. saw_error = 0;
  152. first = i * 8;
  153. last = first + 8;
  154. for (j = first; j < last; j++) {
  155. unsigned long errval = stc_error_buf[j];
  156. if (errval != 0) {
  157. saw_error++;
  158. printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
  159. pbm->name,
  160. j,
  161. (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
  162. (errval & SCHIZO_STCERR_READ) ? 1 : 0);
  163. }
  164. }
  165. if (saw_error != 0) {
  166. unsigned long tagval = stc_tag_buf[i];
  167. unsigned long lineval = stc_line_buf[i];
  168. printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
  169. pbm->name,
  170. i,
  171. ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
  172. (tagval & SCHIZO_STCTAG_VPN),
  173. ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
  174. ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
  175. /* XXX Should spit out per-bank error information... -DaveM */
  176. printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
  177. "V(%d)FOFN(%d)]\n",
  178. pbm->name,
  179. i,
  180. ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
  181. ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
  182. ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
  183. ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
  184. ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
  185. ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
  186. }
  187. }
  188. spin_unlock(&stc_buf_lock);
  189. }
  190. /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
  191. * controller level errors.
  192. */
  193. #define SCHIZO_IOMMU_TAG 0xa580UL
  194. #define SCHIZO_IOMMU_DATA 0xa600UL
  195. #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
  196. #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
  197. #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
  198. #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
  199. #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
  200. #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
  201. #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
  202. #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
  203. #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
  204. #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
  205. static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
  206. enum schizo_error_type type)
  207. {
  208. struct iommu *iommu = pbm->iommu;
  209. unsigned long iommu_tag[16];
  210. unsigned long iommu_data[16];
  211. unsigned long flags;
  212. u64 control;
  213. int i;
  214. spin_lock_irqsave(&iommu->lock, flags);
  215. control = upa_readq(iommu->iommu_control);
  216. if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
  217. unsigned long base;
  218. char *type_string;
  219. /* Clear the error encountered bit. */
  220. control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
  221. upa_writeq(control, iommu->iommu_control);
  222. switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
  223. case 0:
  224. type_string = "Protection Error";
  225. break;
  226. case 1:
  227. type_string = "Invalid Error";
  228. break;
  229. case 2:
  230. type_string = "TimeOut Error";
  231. break;
  232. case 3:
  233. default:
  234. type_string = "ECC Error";
  235. break;
  236. }
  237. printk("%s: IOMMU Error, type[%s]\n",
  238. pbm->name, type_string);
  239. /* Put the IOMMU into diagnostic mode and probe
  240. * it's TLB for entries with error status.
  241. *
  242. * It is very possible for another DVMA to occur
  243. * while we do this probe, and corrupt the system
  244. * further. But we are so screwed at this point
  245. * that we are likely to crash hard anyways, so
  246. * get as much diagnostic information to the
  247. * console as we can.
  248. */
  249. upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB,
  250. iommu->iommu_control);
  251. base = pbm->pbm_regs;
  252. for (i = 0; i < 16; i++) {
  253. iommu_tag[i] =
  254. upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL));
  255. iommu_data[i] =
  256. upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL));
  257. /* Now clear out the entry. */
  258. upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL));
  259. upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL));
  260. }
  261. /* Leave diagnostic mode. */
  262. upa_writeq(control, iommu->iommu_control);
  263. for (i = 0; i < 16; i++) {
  264. unsigned long tag, data;
  265. tag = iommu_tag[i];
  266. if (!(tag & SCHIZO_IOMMU_TAG_ERR))
  267. continue;
  268. data = iommu_data[i];
  269. switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
  270. case 0:
  271. type_string = "Protection Error";
  272. break;
  273. case 1:
  274. type_string = "Invalid Error";
  275. break;
  276. case 2:
  277. type_string = "TimeOut Error";
  278. break;
  279. case 3:
  280. default:
  281. type_string = "ECC Error";
  282. break;
  283. }
  284. printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
  285. "sz(%dK) vpg(%08lx)]\n",
  286. pbm->name, i, type_string,
  287. (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
  288. ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
  289. ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
  290. ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
  291. (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
  292. printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
  293. pbm->name, i,
  294. ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
  295. ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
  296. (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
  297. }
  298. }
  299. if (pbm->stc.strbuf_enabled)
  300. __schizo_check_stc_error_pbm(pbm, type);
  301. spin_unlock_irqrestore(&iommu->lock, flags);
  302. }
  303. static void schizo_check_iommu_error(struct pci_pbm_info *pbm,
  304. enum schizo_error_type type)
  305. {
  306. schizo_check_iommu_error_pbm(pbm, type);
  307. if (pbm->sibling)
  308. schizo_check_iommu_error_pbm(pbm->sibling, type);
  309. }
  310. /* Uncorrectable ECC error status gathering. */
  311. #define SCHIZO_UE_AFSR 0x10030UL
  312. #define SCHIZO_UE_AFAR 0x10038UL
  313. #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
  314. #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
  315. #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
  316. #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
  317. #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
  318. #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
  319. #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
  320. #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
  321. #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
  322. #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
  323. #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
  324. #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
  325. #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
  326. #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
  327. static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
  328. {
  329. struct pci_pbm_info *pbm = dev_id;
  330. unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
  331. unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
  332. unsigned long afsr, afar, error_bits;
  333. int reported, limit;
  334. /* Latch uncorrectable error status. */
  335. afar = upa_readq(afar_reg);
  336. /* If either of the error pending bits are set in the
  337. * AFSR, the error status is being actively updated by
  338. * the hardware and we must re-read to get a clean value.
  339. */
  340. limit = 1000;
  341. do {
  342. afsr = upa_readq(afsr_reg);
  343. } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
  344. /* Clear the primary/secondary error status bits. */
  345. error_bits = afsr &
  346. (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
  347. SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
  348. if (!error_bits)
  349. return IRQ_NONE;
  350. upa_writeq(error_bits, afsr_reg);
  351. /* Log the error. */
  352. printk("%s: Uncorrectable Error, primary error type[%s]\n",
  353. pbm->name,
  354. (((error_bits & SCHIZO_UEAFSR_PPIO) ?
  355. "PIO" :
  356. ((error_bits & SCHIZO_UEAFSR_PDRD) ?
  357. "DMA Read" :
  358. ((error_bits & SCHIZO_UEAFSR_PDWR) ?
  359. "DMA Write" : "???")))));
  360. printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
  361. pbm->name,
  362. (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
  363. (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
  364. (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
  365. printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
  366. pbm->name,
  367. (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
  368. (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
  369. (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
  370. (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
  371. (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
  372. printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
  373. printk("%s: UE Secondary errors [", pbm->name);
  374. reported = 0;
  375. if (afsr & SCHIZO_UEAFSR_SPIO) {
  376. reported++;
  377. printk("(PIO)");
  378. }
  379. if (afsr & SCHIZO_UEAFSR_SDMA) {
  380. reported++;
  381. printk("(DMA)");
  382. }
  383. if (!reported)
  384. printk("(none)");
  385. printk("]\n");
  386. /* Interrogate IOMMU for error status. */
  387. schizo_check_iommu_error(pbm, UE_ERR);
  388. return IRQ_HANDLED;
  389. }
  390. #define SCHIZO_CE_AFSR 0x10040UL
  391. #define SCHIZO_CE_AFAR 0x10048UL
  392. #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
  393. #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
  394. #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
  395. #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
  396. #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
  397. #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
  398. #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
  399. #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
  400. #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
  401. #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
  402. #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
  403. #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
  404. #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
  405. #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
  406. static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
  407. {
  408. struct pci_pbm_info *pbm = dev_id;
  409. unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
  410. unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
  411. unsigned long afsr, afar, error_bits;
  412. int reported, limit;
  413. /* Latch error status. */
  414. afar = upa_readq(afar_reg);
  415. /* If either of the error pending bits are set in the
  416. * AFSR, the error status is being actively updated by
  417. * the hardware and we must re-read to get a clean value.
  418. */
  419. limit = 1000;
  420. do {
  421. afsr = upa_readq(afsr_reg);
  422. } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
  423. /* Clear primary/secondary error status bits. */
  424. error_bits = afsr &
  425. (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
  426. SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
  427. if (!error_bits)
  428. return IRQ_NONE;
  429. upa_writeq(error_bits, afsr_reg);
  430. /* Log the error. */
  431. printk("%s: Correctable Error, primary error type[%s]\n",
  432. pbm->name,
  433. (((error_bits & SCHIZO_CEAFSR_PPIO) ?
  434. "PIO" :
  435. ((error_bits & SCHIZO_CEAFSR_PDRD) ?
  436. "DMA Read" :
  437. ((error_bits & SCHIZO_CEAFSR_PDWR) ?
  438. "DMA Write" : "???")))));
  439. /* XXX Use syndrome and afar to print out module string just like
  440. * XXX UDB CE trap handler does... -DaveM
  441. */
  442. printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
  443. pbm->name,
  444. (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
  445. (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
  446. (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
  447. printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
  448. pbm->name,
  449. (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
  450. (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
  451. (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
  452. (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
  453. (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
  454. printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
  455. printk("%s: CE Secondary errors [", pbm->name);
  456. reported = 0;
  457. if (afsr & SCHIZO_CEAFSR_SPIO) {
  458. reported++;
  459. printk("(PIO)");
  460. }
  461. if (afsr & SCHIZO_CEAFSR_SDMA) {
  462. reported++;
  463. printk("(DMA)");
  464. }
  465. if (!reported)
  466. printk("(none)");
  467. printk("]\n");
  468. return IRQ_HANDLED;
  469. }
  470. #define SCHIZO_PCI_AFSR 0x2010UL
  471. #define SCHIZO_PCI_AFAR 0x2018UL
  472. #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
  473. #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
  474. #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
  475. #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
  476. #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
  477. #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
  478. #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
  479. #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
  480. #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
  481. #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
  482. #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
  483. #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
  484. #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
  485. #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
  486. #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
  487. #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
  488. #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
  489. #define SCHIZO_PCI_CTRL (0x2000UL)
  490. #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
  491. #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
  492. #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
  493. #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
  494. #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
  495. #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
  496. #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
  497. #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
  498. #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
  499. #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
  500. #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
  501. #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
  502. #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
  503. #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
  504. #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
  505. #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
  506. #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
  507. #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
  508. #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
  509. #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
  510. #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
  511. #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
  512. #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
  513. #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
  514. #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
  515. #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
  516. #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
  517. static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
  518. {
  519. unsigned long csr_reg, csr, csr_error_bits;
  520. irqreturn_t ret = IRQ_NONE;
  521. u32 stat;
  522. csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
  523. csr = upa_readq(csr_reg);
  524. csr_error_bits =
  525. csr & (SCHIZO_PCICTRL_BUS_UNUS |
  526. SCHIZO_PCICTRL_TTO_ERR |
  527. SCHIZO_PCICTRL_RTRY_ERR |
  528. SCHIZO_PCICTRL_DTO_ERR |
  529. SCHIZO_PCICTRL_SBH_ERR |
  530. SCHIZO_PCICTRL_SERR);
  531. if (csr_error_bits) {
  532. /* Clear the errors. */
  533. upa_writeq(csr, csr_reg);
  534. /* Log 'em. */
  535. if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
  536. printk("%s: Bus unusable error asserted.\n",
  537. pbm->name);
  538. if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
  539. printk("%s: PCI TRDY# timeout error asserted.\n",
  540. pbm->name);
  541. if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
  542. printk("%s: PCI excessive retry error asserted.\n",
  543. pbm->name);
  544. if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
  545. printk("%s: PCI discard timeout error asserted.\n",
  546. pbm->name);
  547. if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
  548. printk("%s: PCI streaming byte hole error asserted.\n",
  549. pbm->name);
  550. if (csr_error_bits & SCHIZO_PCICTRL_SERR)
  551. printk("%s: PCI SERR signal asserted.\n",
  552. pbm->name);
  553. ret = IRQ_HANDLED;
  554. }
  555. pbm->pci_ops->read(pbm->pci_bus, 0, PCI_STATUS, 2, &stat);
  556. if (stat & (PCI_STATUS_PARITY |
  557. PCI_STATUS_SIG_TARGET_ABORT |
  558. PCI_STATUS_REC_TARGET_ABORT |
  559. PCI_STATUS_REC_MASTER_ABORT |
  560. PCI_STATUS_SIG_SYSTEM_ERROR)) {
  561. printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
  562. pbm->name, stat);
  563. pbm->pci_ops->write(pbm->pci_bus, 0, PCI_STATUS, 2, 0xffff);
  564. ret = IRQ_HANDLED;
  565. }
  566. return ret;
  567. }
  568. static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
  569. {
  570. struct pci_pbm_info *pbm = dev_id;
  571. unsigned long afsr_reg, afar_reg, base;
  572. unsigned long afsr, afar, error_bits;
  573. int reported;
  574. base = pbm->pbm_regs;
  575. afsr_reg = base + SCHIZO_PCI_AFSR;
  576. afar_reg = base + SCHIZO_PCI_AFAR;
  577. /* Latch error status. */
  578. afar = upa_readq(afar_reg);
  579. afsr = upa_readq(afsr_reg);
  580. /* Clear primary/secondary error status bits. */
  581. error_bits = afsr &
  582. (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
  583. SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
  584. SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
  585. SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
  586. SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
  587. SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
  588. if (!error_bits)
  589. return schizo_pcierr_intr_other(pbm);
  590. upa_writeq(error_bits, afsr_reg);
  591. /* Log the error. */
  592. printk("%s: PCI Error, primary error type[%s]\n",
  593. pbm->name,
  594. (((error_bits & SCHIZO_PCIAFSR_PMA) ?
  595. "Master Abort" :
  596. ((error_bits & SCHIZO_PCIAFSR_PTA) ?
  597. "Target Abort" :
  598. ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
  599. "Excessive Retries" :
  600. ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
  601. "Parity Error" :
  602. ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
  603. "Timeout" :
  604. ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
  605. "Bus Unusable" : "???"))))))));
  606. printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
  607. pbm->name,
  608. (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
  609. (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
  610. ((afsr & SCHIZO_PCIAFSR_CFG) ?
  611. "Config" :
  612. ((afsr & SCHIZO_PCIAFSR_MEM) ?
  613. "Memory" :
  614. ((afsr & SCHIZO_PCIAFSR_IO) ?
  615. "I/O" : "???"))));
  616. printk("%s: PCI AFAR [%016lx]\n",
  617. pbm->name, afar);
  618. printk("%s: PCI Secondary errors [",
  619. pbm->name);
  620. reported = 0;
  621. if (afsr & SCHIZO_PCIAFSR_SMA) {
  622. reported++;
  623. printk("(Master Abort)");
  624. }
  625. if (afsr & SCHIZO_PCIAFSR_STA) {
  626. reported++;
  627. printk("(Target Abort)");
  628. }
  629. if (afsr & SCHIZO_PCIAFSR_SRTRY) {
  630. reported++;
  631. printk("(Excessive Retries)");
  632. }
  633. if (afsr & SCHIZO_PCIAFSR_SPERR) {
  634. reported++;
  635. printk("(Parity Error)");
  636. }
  637. if (afsr & SCHIZO_PCIAFSR_STTO) {
  638. reported++;
  639. printk("(Timeout)");
  640. }
  641. if (afsr & SCHIZO_PCIAFSR_SUNUS) {
  642. reported++;
  643. printk("(Bus Unusable)");
  644. }
  645. if (!reported)
  646. printk("(none)");
  647. printk("]\n");
  648. /* For the error types shown, scan PBM's PCI bus for devices
  649. * which have logged that error type.
  650. */
  651. /* If we see a Target Abort, this could be the result of an
  652. * IOMMU translation error of some sort. It is extremely
  653. * useful to log this information as usually it indicates
  654. * a bug in the IOMMU support code or a PCI device driver.
  655. */
  656. if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
  657. schizo_check_iommu_error(pbm, PCI_ERR);
  658. pci_scan_for_target_abort(pbm, pbm->pci_bus);
  659. }
  660. if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
  661. pci_scan_for_master_abort(pbm, pbm->pci_bus);
  662. /* For excessive retries, PSYCHO/PBM will abort the device
  663. * and there is no way to specifically check for excessive
  664. * retries in the config space status registers. So what
  665. * we hope is that we'll catch it via the master/target
  666. * abort events.
  667. */
  668. if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
  669. pci_scan_for_parity_error(pbm, pbm->pci_bus);
  670. return IRQ_HANDLED;
  671. }
  672. #define SCHIZO_SAFARI_ERRLOG 0x10018UL
  673. #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
  674. #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
  675. #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
  676. #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
  677. #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
  678. #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
  679. #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
  680. #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
  681. #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
  682. #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
  683. #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
  684. #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
  685. #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
  686. #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
  687. #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
  688. #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
  689. #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
  690. #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
  691. #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
  692. #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
  693. #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
  694. #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
  695. #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
  696. #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
  697. #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
  698. #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
  699. #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
  700. #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
  701. #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
  702. #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
  703. #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
  704. #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
  705. /* We only expect UNMAP errors here. The rest of the Safari errors
  706. * are marked fatal and thus cause a system reset.
  707. */
  708. static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
  709. {
  710. struct pci_pbm_info *pbm = dev_id;
  711. u64 errlog;
  712. errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
  713. upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT),
  714. pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
  715. if (!(errlog & BUS_ERROR_UNMAP)) {
  716. printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n",
  717. pbm->name, errlog);
  718. return IRQ_HANDLED;
  719. }
  720. printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
  721. pbm->name);
  722. schizo_check_iommu_error(pbm, SAFARI_ERR);
  723. return IRQ_HANDLED;
  724. }
  725. /* Nearly identical to PSYCHO equivalents... */
  726. #define SCHIZO_ECC_CTRL 0x10020UL
  727. #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
  728. #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
  729. #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
  730. #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
  731. #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
  732. #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
  733. #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
  734. static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
  735. {
  736. ino &= IMAP_INO;
  737. if (pbm->ino_bitmap & (1UL << ino))
  738. return 1;
  739. return 0;
  740. }
  741. /* How the Tomatillo IRQs are routed around is pure guesswork here.
  742. *
  743. * All the Tomatillo devices I see in prtconf dumps seem to have only
  744. * a single PCI bus unit attached to it. It would seem they are separate
  745. * devices because their PortID (ie. JBUS ID) values are all different
  746. * and thus the registers are mapped to totally different locations.
  747. *
  748. * However, two Tomatillo's look "similar" in that the only difference
  749. * in their PortID is the lowest bit.
  750. *
  751. * So if we were to ignore this lower bit, it certainly looks like two
  752. * PCI bus units of the same Tomatillo. I still have not really
  753. * figured this out...
  754. */
  755. static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
  756. {
  757. struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
  758. u64 tmp, err_mask, err_no_mask;
  759. int err;
  760. /* Tomatillo IRQ property layout is:
  761. * 0: PCIERR
  762. * 1: UE ERR
  763. * 2: CE ERR
  764. * 3: SERR
  765. * 4: POWER FAIL?
  766. */
  767. if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
  768. err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
  769. "TOMATILLO_UE", pbm);
  770. if (err)
  771. printk(KERN_WARNING "%s: Could not register UE, "
  772. "err=%d\n", pbm->name, err);
  773. }
  774. if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
  775. err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
  776. "TOMATILLO_CE", pbm);
  777. if (err)
  778. printk(KERN_WARNING "%s: Could not register CE, "
  779. "err=%d\n", pbm->name, err);
  780. }
  781. err = 0;
  782. if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
  783. err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
  784. "TOMATILLO_PCIERR", pbm);
  785. } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
  786. err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
  787. "TOMATILLO_PCIERR", pbm);
  788. }
  789. if (err)
  790. printk(KERN_WARNING "%s: Could not register PCIERR, "
  791. "err=%d\n", pbm->name, err);
  792. if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
  793. err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
  794. "TOMATILLO_SERR", pbm);
  795. if (err)
  796. printk(KERN_WARNING "%s: Could not register SERR, "
  797. "err=%d\n", pbm->name, err);
  798. }
  799. /* Enable UE and CE interrupts for controller. */
  800. upa_writeq((SCHIZO_ECCCTRL_EE |
  801. SCHIZO_ECCCTRL_UE |
  802. SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
  803. /* Enable PCI Error interrupts and clear error
  804. * bits.
  805. */
  806. err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
  807. SCHIZO_PCICTRL_TTO_ERR |
  808. SCHIZO_PCICTRL_RTRY_ERR |
  809. SCHIZO_PCICTRL_SERR |
  810. SCHIZO_PCICTRL_EEN);
  811. err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
  812. tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
  813. tmp |= err_mask;
  814. tmp &= ~err_no_mask;
  815. upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
  816. err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
  817. SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
  818. SCHIZO_PCIAFSR_PTTO |
  819. SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
  820. SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
  821. SCHIZO_PCIAFSR_STTO);
  822. upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR);
  823. err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
  824. BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
  825. BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
  826. BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
  827. BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
  828. BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
  829. BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
  830. BUS_ERROR_APERR | BUS_ERROR_UNMAP |
  831. BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
  832. upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
  833. pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
  834. upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)),
  835. pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL);
  836. }
  837. static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
  838. {
  839. struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
  840. u64 tmp, err_mask, err_no_mask;
  841. int err;
  842. /* Schizo IRQ property layout is:
  843. * 0: PCIERR
  844. * 1: UE ERR
  845. * 2: CE ERR
  846. * 3: SERR
  847. * 4: POWER FAIL?
  848. */
  849. if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
  850. err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
  851. "SCHIZO_UE", pbm);
  852. if (err)
  853. printk(KERN_WARNING "%s: Could not register UE, "
  854. "err=%d\n", pbm->name, err);
  855. }
  856. if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
  857. err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
  858. "SCHIZO_CE", pbm);
  859. if (err)
  860. printk(KERN_WARNING "%s: Could not register CE, "
  861. "err=%d\n", pbm->name, err);
  862. }
  863. err = 0;
  864. if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
  865. err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
  866. "SCHIZO_PCIERR", pbm);
  867. } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
  868. err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
  869. "SCHIZO_PCIERR", pbm);
  870. }
  871. if (err)
  872. printk(KERN_WARNING "%s: Could not register PCIERR, "
  873. "err=%d\n", pbm->name, err);
  874. if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
  875. err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
  876. "SCHIZO_SERR", pbm);
  877. if (err)
  878. printk(KERN_WARNING "%s: Could not register SERR, "
  879. "err=%d\n", pbm->name, err);
  880. }
  881. /* Enable UE and CE interrupts for controller. */
  882. upa_writeq((SCHIZO_ECCCTRL_EE |
  883. SCHIZO_ECCCTRL_UE |
  884. SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
  885. err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
  886. SCHIZO_PCICTRL_ESLCK |
  887. SCHIZO_PCICTRL_TTO_ERR |
  888. SCHIZO_PCICTRL_RTRY_ERR |
  889. SCHIZO_PCICTRL_SBH_ERR |
  890. SCHIZO_PCICTRL_SERR |
  891. SCHIZO_PCICTRL_EEN);
  892. err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
  893. SCHIZO_PCICTRL_SBH_INT);
  894. /* Enable PCI Error interrupts and clear error
  895. * bits for each PBM.
  896. */
  897. tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
  898. tmp |= err_mask;
  899. tmp &= ~err_no_mask;
  900. upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
  901. upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
  902. SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
  903. SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
  904. SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
  905. SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
  906. SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS),
  907. pbm->pbm_regs + SCHIZO_PCI_AFSR);
  908. /* Make all Safari error conditions fatal except unmapped
  909. * errors which we make generate interrupts.
  910. */
  911. err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
  912. BUS_ERROR_BADMA | BUS_ERROR_BADMB |
  913. BUS_ERROR_BADMC |
  914. BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
  915. BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
  916. BUS_ERROR_CIQTO |
  917. BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
  918. BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
  919. BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
  920. BUS_ERROR_ILL);
  921. #if 1
  922. /* XXX Something wrong with some Excalibur systems
  923. * XXX Sun is shipping. The behavior on a 2-cpu
  924. * XXX machine is that both CPU1 parity error bits
  925. * XXX are set and are immediately set again when
  926. * XXX their error status bits are cleared. Just
  927. * XXX ignore them for now. -DaveM
  928. */
  929. err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
  930. BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
  931. #endif
  932. upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
  933. pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
  934. }
  935. static void pbm_config_busmastering(struct pci_pbm_info *pbm)
  936. {
  937. u8 *addr;
  938. /* Set cache-line size to 64 bytes, this is actually
  939. * a nop but I do it for completeness.
  940. */
  941. addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
  942. 0, PCI_CACHE_LINE_SIZE);
  943. pci_config_write8(addr, 64 / sizeof(u32));
  944. /* Set PBM latency timer to 64 PCI clocks. */
  945. addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
  946. 0, PCI_LATENCY_TIMER);
  947. pci_config_write8(addr, 64);
  948. }
  949. static void schizo_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
  950. {
  951. pbm_config_busmastering(pbm);
  952. pbm->is_66mhz_capable =
  953. (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL)
  954. != NULL);
  955. pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
  956. if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
  957. tomatillo_register_error_handlers(pbm);
  958. else
  959. schizo_register_error_handlers(pbm);
  960. }
  961. #define SCHIZO_STRBUF_CONTROL (0x02800UL)
  962. #define SCHIZO_STRBUF_FLUSH (0x02808UL)
  963. #define SCHIZO_STRBUF_FSYNC (0x02810UL)
  964. #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
  965. #define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
  966. static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
  967. {
  968. unsigned long base = pbm->pbm_regs;
  969. u64 control;
  970. if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
  971. /* TOMATILLO lacks streaming cache. */
  972. return;
  973. }
  974. /* SCHIZO has context flushing. */
  975. pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
  976. pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
  977. pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
  978. pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
  979. pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
  980. pbm->stc.strbuf_flushflag = (volatile unsigned long *)
  981. ((((unsigned long)&pbm->stc.__flushflag_buf[0])
  982. + 63UL)
  983. & ~63UL);
  984. pbm->stc.strbuf_flushflag_pa = (unsigned long)
  985. __pa(pbm->stc.strbuf_flushflag);
  986. /* Turn off LRU locking and diag mode, enable the
  987. * streaming buffer and leave the rerun-disable
  988. * setting however OBP set it.
  989. */
  990. control = upa_readq(pbm->stc.strbuf_control);
  991. control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
  992. SCHIZO_STRBUF_CTRL_LENAB |
  993. SCHIZO_STRBUF_CTRL_DENAB);
  994. control |= SCHIZO_STRBUF_CTRL_ENAB;
  995. upa_writeq(control, pbm->stc.strbuf_control);
  996. pbm->stc.strbuf_enabled = 1;
  997. }
  998. #define SCHIZO_IOMMU_CONTROL (0x00200UL)
  999. #define SCHIZO_IOMMU_TSBBASE (0x00208UL)
  1000. #define SCHIZO_IOMMU_FLUSH (0x00210UL)
  1001. #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
  1002. static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
  1003. {
  1004. static const u32 vdma_default[] = { 0xc0000000, 0x40000000 };
  1005. unsigned long i, tagbase, database;
  1006. struct iommu *iommu = pbm->iommu;
  1007. int tsbsize, err;
  1008. const u32 *vdma;
  1009. u32 dma_mask;
  1010. u64 control;
  1011. vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
  1012. if (!vdma)
  1013. vdma = vdma_default;
  1014. dma_mask = vdma[0];
  1015. switch (vdma[1]) {
  1016. case 0x20000000:
  1017. dma_mask |= 0x1fffffff;
  1018. tsbsize = 64;
  1019. break;
  1020. case 0x40000000:
  1021. dma_mask |= 0x3fffffff;
  1022. tsbsize = 128;
  1023. break;
  1024. case 0x80000000:
  1025. dma_mask |= 0x7fffffff;
  1026. tsbsize = 128;
  1027. break;
  1028. default:
  1029. printk(KERN_ERR PFX "Strange virtual-dma size.\n");
  1030. return -EINVAL;
  1031. }
  1032. /* Register addresses, SCHIZO has iommu ctx flushing. */
  1033. iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
  1034. iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
  1035. iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
  1036. iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
  1037. iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
  1038. /* We use the main control/status register of SCHIZO as the write
  1039. * completion register.
  1040. */
  1041. iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
  1042. /*
  1043. * Invalidate TLB Entries.
  1044. */
  1045. control = upa_readq(iommu->iommu_control);
  1046. control |= SCHIZO_IOMMU_CTRL_DENAB;
  1047. upa_writeq(control, iommu->iommu_control);
  1048. tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
  1049. for (i = 0; i < 16; i++) {
  1050. upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL));
  1051. upa_writeq(0, pbm->pbm_regs + database + (i * 8UL));
  1052. }
  1053. /* Leave diag mode enabled for full-flushing done
  1054. * in pci_iommu.c
  1055. */
  1056. err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
  1057. pbm->numa_node);
  1058. if (err) {
  1059. printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err);
  1060. return err;
  1061. }
  1062. upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
  1063. control = upa_readq(iommu->iommu_control);
  1064. control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
  1065. switch (tsbsize) {
  1066. case 64:
  1067. control |= SCHIZO_IOMMU_TSBSZ_64K;
  1068. break;
  1069. case 128:
  1070. control |= SCHIZO_IOMMU_TSBSZ_128K;
  1071. break;
  1072. }
  1073. control |= SCHIZO_IOMMU_CTRL_ENAB;
  1074. upa_writeq(control, iommu->iommu_control);
  1075. return 0;
  1076. }
  1077. #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
  1078. #define SCHIZO_IRQ_RETRY_INF 0xffUL
  1079. #define SCHIZO_PCI_DIAG (0x2020UL)
  1080. #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
  1081. #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
  1082. #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
  1083. #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
  1084. #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
  1085. #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
  1086. #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
  1087. #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
  1088. #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
  1089. #define TOMATILLO_PCI_IOC_CSR (0x2248UL)
  1090. #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
  1091. #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
  1092. #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
  1093. #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
  1094. #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
  1095. #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
  1096. #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
  1097. #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
  1098. #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
  1099. #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
  1100. #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
  1101. #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
  1102. #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
  1103. #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
  1104. #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
  1105. #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
  1106. #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
  1107. static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
  1108. {
  1109. u64 tmp;
  1110. upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY);
  1111. tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
  1112. /* Enable arbiter for all PCI slots. */
  1113. tmp |= 0xff;
  1114. if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
  1115. pbm->chip_version >= 0x2)
  1116. tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
  1117. if (!of_find_property(pbm->op->dev.of_node, "no-bus-parking", NULL))
  1118. tmp |= SCHIZO_PCICTRL_PARK;
  1119. else
  1120. tmp &= ~SCHIZO_PCICTRL_PARK;
  1121. if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
  1122. pbm->chip_version <= 0x1)
  1123. tmp |= SCHIZO_PCICTRL_DTO_INT;
  1124. else
  1125. tmp &= ~SCHIZO_PCICTRL_DTO_INT;
  1126. if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
  1127. tmp |= (SCHIZO_PCICTRL_MRM_PREF |
  1128. SCHIZO_PCICTRL_RDO_PREF |
  1129. SCHIZO_PCICTRL_RDL_PREF);
  1130. upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
  1131. tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG);
  1132. tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
  1133. SCHIZO_PCIDIAG_D_RETRY |
  1134. SCHIZO_PCIDIAG_D_INTSYNC);
  1135. upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG);
  1136. if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
  1137. /* Clear prefetch lengths to workaround a bug in
  1138. * Jalapeno...
  1139. */
  1140. tmp = (TOMATILLO_IOC_PART_WPENAB |
  1141. (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
  1142. TOMATILLO_IOC_RDMULT_CPENAB |
  1143. TOMATILLO_IOC_RDONE_CPENAB |
  1144. TOMATILLO_IOC_RDLINE_CPENAB);
  1145. upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR);
  1146. }
  1147. }
  1148. static int schizo_pbm_init(struct pci_pbm_info *pbm,
  1149. struct platform_device *op, u32 portid,
  1150. int chip_type)
  1151. {
  1152. const struct linux_prom64_registers *regs;
  1153. struct device_node *dp = op->dev.of_node;
  1154. const char *chipset_name;
  1155. int err;
  1156. switch (chip_type) {
  1157. case PBM_CHIP_TYPE_TOMATILLO:
  1158. chipset_name = "TOMATILLO";
  1159. break;
  1160. case PBM_CHIP_TYPE_SCHIZO_PLUS:
  1161. chipset_name = "SCHIZO+";
  1162. break;
  1163. case PBM_CHIP_TYPE_SCHIZO:
  1164. default:
  1165. chipset_name = "SCHIZO";
  1166. break;
  1167. }
  1168. /* For SCHIZO, three OBP regs:
  1169. * 1) PBM controller regs
  1170. * 2) Schizo front-end controller regs (same for both PBMs)
  1171. * 3) PBM PCI config space
  1172. *
  1173. * For TOMATILLO, four OBP regs:
  1174. * 1) PBM controller regs
  1175. * 2) Tomatillo front-end controller regs
  1176. * 3) PBM PCI config space
  1177. * 4) Ichip regs
  1178. */
  1179. regs = of_get_property(dp, "reg", NULL);
  1180. pbm->next = pci_pbm_root;
  1181. pci_pbm_root = pbm;
  1182. pbm->numa_node = NUMA_NO_NODE;
  1183. pbm->pci_ops = &sun4u_pci_ops;
  1184. pbm->config_space_reg_bits = 8;
  1185. pbm->index = pci_num_pbms++;
  1186. pbm->portid = portid;
  1187. pbm->op = op;
  1188. pbm->chip_type = chip_type;
  1189. pbm->chip_version = of_getintprop_default(dp, "version#", 0);
  1190. pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
  1191. pbm->pbm_regs = regs[0].phys_addr;
  1192. pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
  1193. if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
  1194. pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
  1195. pbm->name = dp->full_name;
  1196. printk("%s: %s PCI Bus Module ver[%x:%x]\n",
  1197. pbm->name, chipset_name,
  1198. pbm->chip_version, pbm->chip_revision);
  1199. schizo_pbm_hw_init(pbm);
  1200. pci_determine_mem_io_space(pbm);
  1201. pci_get_pbm_props(pbm);
  1202. err = schizo_pbm_iommu_init(pbm);
  1203. if (err)
  1204. return err;
  1205. schizo_pbm_strbuf_init(pbm);
  1206. schizo_scan_bus(pbm, &op->dev);
  1207. return 0;
  1208. }
  1209. static inline int portid_compare(u32 x, u32 y, int chip_type)
  1210. {
  1211. if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
  1212. if (x == (y ^ 1))
  1213. return 1;
  1214. return 0;
  1215. }
  1216. return (x == y);
  1217. }
  1218. static struct pci_pbm_info *schizo_find_sibling(u32 portid, int chip_type)
  1219. {
  1220. struct pci_pbm_info *pbm;
  1221. for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
  1222. if (portid_compare(pbm->portid, portid, chip_type))
  1223. return pbm;
  1224. }
  1225. return NULL;
  1226. }
  1227. static int __schizo_init(struct platform_device *op, unsigned long chip_type)
  1228. {
  1229. struct device_node *dp = op->dev.of_node;
  1230. struct pci_pbm_info *pbm;
  1231. struct iommu *iommu;
  1232. u32 portid;
  1233. int err;
  1234. portid = of_getintprop_default(dp, "portid", 0xff);
  1235. err = -ENOMEM;
  1236. pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
  1237. if (!pbm) {
  1238. printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
  1239. goto out_err;
  1240. }
  1241. pbm->sibling = schizo_find_sibling(portid, chip_type);
  1242. iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
  1243. if (!iommu) {
  1244. printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
  1245. goto out_free_pbm;
  1246. }
  1247. pbm->iommu = iommu;
  1248. if (schizo_pbm_init(pbm, op, portid, chip_type))
  1249. goto out_free_iommu;
  1250. if (pbm->sibling)
  1251. pbm->sibling->sibling = pbm;
  1252. dev_set_drvdata(&op->dev, pbm);
  1253. return 0;
  1254. out_free_iommu:
  1255. kfree(pbm->iommu);
  1256. out_free_pbm:
  1257. kfree(pbm);
  1258. out_err:
  1259. return err;
  1260. }
  1261. static const struct of_device_id schizo_match[];
  1262. static int schizo_probe(struct platform_device *op)
  1263. {
  1264. const struct of_device_id *match;
  1265. match = of_match_device(schizo_match, &op->dev);
  1266. if (!match)
  1267. return -EINVAL;
  1268. return __schizo_init(op, (unsigned long)match->data);
  1269. }
  1270. /* The ordering of this table is very important. Some Tomatillo
  1271. * nodes announce that they are compatible with both pci108e,a801
  1272. * and pci108e,8001. So list the chips in reverse chronological
  1273. * order.
  1274. */
  1275. static const struct of_device_id schizo_match[] = {
  1276. {
  1277. .name = "pci",
  1278. .compatible = "pci108e,a801",
  1279. .data = (void *) PBM_CHIP_TYPE_TOMATILLO,
  1280. },
  1281. {
  1282. .name = "pci",
  1283. .compatible = "pci108e,8002",
  1284. .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS,
  1285. },
  1286. {
  1287. .name = "pci",
  1288. .compatible = "pci108e,8001",
  1289. .data = (void *) PBM_CHIP_TYPE_SCHIZO,
  1290. },
  1291. {},
  1292. };
  1293. static struct platform_driver schizo_driver = {
  1294. .driver = {
  1295. .name = DRIVER_NAME,
  1296. .of_match_table = schizo_match,
  1297. },
  1298. .probe = schizo_probe,
  1299. };
  1300. static int __init schizo_init(void)
  1301. {
  1302. return platform_driver_register(&schizo_driver);
  1303. }
  1304. subsys_initcall(schizo_init);