pci_psycho.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
  3. *
  4. * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
  5. * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
  6. * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/types.h>
  10. #include <linux/pci.h>
  11. #include <linux/init.h>
  12. #include <linux/export.h>
  13. #include <linux/slab.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/of_device.h>
  16. #include <asm/iommu.h>
  17. #include <asm/irq.h>
  18. #include <asm/starfire.h>
  19. #include <asm/prom.h>
  20. #include <asm/upa.h>
  21. #include "pci_impl.h"
  22. #include "iommu_common.h"
  23. #include "psycho_common.h"
  24. #define DRIVER_NAME "psycho"
  25. #define PFX DRIVER_NAME ": "
  26. /* Misc. PSYCHO PCI controller register offsets and definitions. */
  27. #define PSYCHO_CONTROL 0x0010UL
  28. #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
  29. #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
  30. #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
  31. #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
  32. #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
  33. #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
  34. #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
  35. #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
  36. #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
  37. #define PSYCHO_PCIA_CTRL 0x2000UL
  38. #define PSYCHO_PCIB_CTRL 0x4000UL
  39. #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
  40. #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
  41. #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
  42. #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
  43. #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
  44. #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
  45. #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
  46. #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
  47. #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
  48. #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
  49. #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
  50. #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
  51. /* PSYCHO error handling support. */
  52. /* Helper function of IOMMU error checking, which checks out
  53. * the state of the streaming buffers. The IOMMU lock is
  54. * held when this is called.
  55. *
  56. * For the PCI error case we know which PBM (and thus which
  57. * streaming buffer) caused the error, but for the uncorrectable
  58. * error case we do not. So we always check both streaming caches.
  59. */
  60. #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
  61. #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
  62. #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
  63. #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
  64. #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
  65. #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
  66. #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
  67. #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
  68. #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
  69. #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
  70. #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
  71. #define PSYCHO_STC_DATA_A 0xb000UL
  72. #define PSYCHO_STC_DATA_B 0xc000UL
  73. #define PSYCHO_STC_ERR_A 0xb400UL
  74. #define PSYCHO_STC_ERR_B 0xc400UL
  75. #define PSYCHO_STC_TAG_A 0xb800UL
  76. #define PSYCHO_STC_TAG_B 0xc800UL
  77. #define PSYCHO_STC_LINE_A 0xb900UL
  78. #define PSYCHO_STC_LINE_B 0xc900UL
  79. /* When an Uncorrectable Error or a PCI Error happens, we
  80. * interrogate the IOMMU state to see if it is the cause.
  81. */
  82. #define PSYCHO_IOMMU_CONTROL 0x0200UL
  83. #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
  84. #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
  85. #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
  86. #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
  87. #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
  88. #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
  89. #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
  90. #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
  91. #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
  92. #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
  93. #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
  94. #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
  95. #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
  96. #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
  97. #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
  98. #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
  99. #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
  100. #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
  101. #define PSYCHO_IOMMU_TSBBASE 0x0208UL
  102. #define PSYCHO_IOMMU_FLUSH 0x0210UL
  103. #define PSYCHO_IOMMU_TAG 0xa580UL
  104. #define PSYCHO_IOMMU_DATA 0xa600UL
  105. /* Uncorrectable Errors. Cause of the error and the address are
  106. * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
  107. * relating to UPA interface transactions.
  108. */
  109. #define PSYCHO_UE_AFSR 0x0030UL
  110. #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
  111. #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
  112. #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
  113. #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
  114. #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
  115. #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
  116. #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
  117. #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
  118. #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
  119. #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
  120. #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
  121. #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
  122. #define PSYCHO_UE_AFAR 0x0038UL
  123. static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
  124. {
  125. struct pci_pbm_info *pbm = dev_id;
  126. unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
  127. unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
  128. unsigned long afsr, afar, error_bits;
  129. int reported;
  130. /* Latch uncorrectable error status. */
  131. afar = upa_readq(afar_reg);
  132. afsr = upa_readq(afsr_reg);
  133. /* Clear the primary/secondary error status bits. */
  134. error_bits = afsr &
  135. (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
  136. PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
  137. if (!error_bits)
  138. return IRQ_NONE;
  139. upa_writeq(error_bits, afsr_reg);
  140. /* Log the error. */
  141. printk("%s: Uncorrectable Error, primary error type[%s]\n",
  142. pbm->name,
  143. (((error_bits & PSYCHO_UEAFSR_PPIO) ?
  144. "PIO" :
  145. ((error_bits & PSYCHO_UEAFSR_PDRD) ?
  146. "DMA Read" :
  147. ((error_bits & PSYCHO_UEAFSR_PDWR) ?
  148. "DMA Write" : "???")))));
  149. printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
  150. pbm->name,
  151. (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
  152. (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
  153. (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
  154. ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
  155. printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
  156. printk("%s: UE Secondary errors [", pbm->name);
  157. reported = 0;
  158. if (afsr & PSYCHO_UEAFSR_SPIO) {
  159. reported++;
  160. printk("(PIO)");
  161. }
  162. if (afsr & PSYCHO_UEAFSR_SDRD) {
  163. reported++;
  164. printk("(DMA Read)");
  165. }
  166. if (afsr & PSYCHO_UEAFSR_SDWR) {
  167. reported++;
  168. printk("(DMA Write)");
  169. }
  170. if (!reported)
  171. printk("(none)");
  172. printk("]\n");
  173. /* Interrogate both IOMMUs for error status. */
  174. psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
  175. if (pbm->sibling)
  176. psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR);
  177. return IRQ_HANDLED;
  178. }
  179. /* Correctable Errors. */
  180. #define PSYCHO_CE_AFSR 0x0040UL
  181. #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
  182. #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
  183. #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
  184. #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
  185. #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
  186. #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
  187. #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
  188. #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
  189. #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
  190. #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
  191. #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
  192. #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
  193. #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
  194. #define PSYCHO_CE_AFAR 0x0040UL
  195. static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
  196. {
  197. struct pci_pbm_info *pbm = dev_id;
  198. unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
  199. unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
  200. unsigned long afsr, afar, error_bits;
  201. int reported;
  202. /* Latch error status. */
  203. afar = upa_readq(afar_reg);
  204. afsr = upa_readq(afsr_reg);
  205. /* Clear primary/secondary error status bits. */
  206. error_bits = afsr &
  207. (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
  208. PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
  209. if (!error_bits)
  210. return IRQ_NONE;
  211. upa_writeq(error_bits, afsr_reg);
  212. /* Log the error. */
  213. printk("%s: Correctable Error, primary error type[%s]\n",
  214. pbm->name,
  215. (((error_bits & PSYCHO_CEAFSR_PPIO) ?
  216. "PIO" :
  217. ((error_bits & PSYCHO_CEAFSR_PDRD) ?
  218. "DMA Read" :
  219. ((error_bits & PSYCHO_CEAFSR_PDWR) ?
  220. "DMA Write" : "???")))));
  221. /* XXX Use syndrome and afar to print out module string just like
  222. * XXX UDB CE trap handler does... -DaveM
  223. */
  224. printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
  225. "UPA_MID[%02lx] was_block(%d)\n",
  226. pbm->name,
  227. (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
  228. (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
  229. (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
  230. (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
  231. ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
  232. printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
  233. printk("%s: CE Secondary errors [", pbm->name);
  234. reported = 0;
  235. if (afsr & PSYCHO_CEAFSR_SPIO) {
  236. reported++;
  237. printk("(PIO)");
  238. }
  239. if (afsr & PSYCHO_CEAFSR_SDRD) {
  240. reported++;
  241. printk("(DMA Read)");
  242. }
  243. if (afsr & PSYCHO_CEAFSR_SDWR) {
  244. reported++;
  245. printk("(DMA Write)");
  246. }
  247. if (!reported)
  248. printk("(none)");
  249. printk("]\n");
  250. return IRQ_HANDLED;
  251. }
  252. /* PCI Errors. They are signalled by the PCI bus module since they
  253. * are associated with a specific bus segment.
  254. */
  255. #define PSYCHO_PCI_AFSR_A 0x2010UL
  256. #define PSYCHO_PCI_AFSR_B 0x4010UL
  257. #define PSYCHO_PCI_AFAR_A 0x2018UL
  258. #define PSYCHO_PCI_AFAR_B 0x4018UL
  259. /* XXX What about PowerFail/PowerManagement??? -DaveM */
  260. #define PSYCHO_ECC_CTRL 0x0020
  261. #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
  262. #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
  263. #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
  264. static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
  265. {
  266. struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
  267. unsigned long base = pbm->controller_regs;
  268. u64 tmp;
  269. int err;
  270. if (!op)
  271. return;
  272. /* Psycho interrupt property order is:
  273. * 0: PCIERR INO for this PBM
  274. * 1: UE ERR
  275. * 2: CE ERR
  276. * 3: POWER FAIL
  277. * 4: SPARE HARDWARE
  278. * 5: POWER MANAGEMENT
  279. */
  280. if (op->archdata.num_irqs < 6)
  281. return;
  282. /* We really mean to ignore the return result here. Two
  283. * PCI controller share the same interrupt numbers and
  284. * drive the same front-end hardware.
  285. */
  286. err = request_irq(op->archdata.irqs[1], psycho_ue_intr, IRQF_SHARED,
  287. "PSYCHO_UE", pbm);
  288. err = request_irq(op->archdata.irqs[2], psycho_ce_intr, IRQF_SHARED,
  289. "PSYCHO_CE", pbm);
  290. /* This one, however, ought not to fail. We can just warn
  291. * about it since the system can still operate properly even
  292. * if this fails.
  293. */
  294. err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, IRQF_SHARED,
  295. "PSYCHO_PCIERR", pbm);
  296. if (err)
  297. printk(KERN_WARNING "%s: Could not register PCIERR, "
  298. "err=%d\n", pbm->name, err);
  299. /* Enable UE and CE interrupts for controller. */
  300. upa_writeq((PSYCHO_ECCCTRL_EE |
  301. PSYCHO_ECCCTRL_UE |
  302. PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL);
  303. /* Enable PCI Error interrupts and clear error
  304. * bits for each PBM.
  305. */
  306. tmp = upa_readq(base + PSYCHO_PCIA_CTRL);
  307. tmp |= (PSYCHO_PCICTRL_SERR |
  308. PSYCHO_PCICTRL_SBH_ERR |
  309. PSYCHO_PCICTRL_EEN);
  310. tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
  311. upa_writeq(tmp, base + PSYCHO_PCIA_CTRL);
  312. tmp = upa_readq(base + PSYCHO_PCIB_CTRL);
  313. tmp |= (PSYCHO_PCICTRL_SERR |
  314. PSYCHO_PCICTRL_SBH_ERR |
  315. PSYCHO_PCICTRL_EEN);
  316. tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
  317. upa_writeq(tmp, base + PSYCHO_PCIB_CTRL);
  318. }
  319. /* PSYCHO boot time probing and initialization. */
  320. static void pbm_config_busmastering(struct pci_pbm_info *pbm)
  321. {
  322. u8 *addr;
  323. /* Set cache-line size to 64 bytes, this is actually
  324. * a nop but I do it for completeness.
  325. */
  326. addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
  327. 0, PCI_CACHE_LINE_SIZE);
  328. pci_config_write8(addr, 64 / sizeof(u32));
  329. /* Set PBM latency timer to 64 PCI clocks. */
  330. addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
  331. 0, PCI_LATENCY_TIMER);
  332. pci_config_write8(addr, 64);
  333. }
  334. static void psycho_scan_bus(struct pci_pbm_info *pbm,
  335. struct device *parent)
  336. {
  337. pbm_config_busmastering(pbm);
  338. pbm->is_66mhz_capable = 0;
  339. pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
  340. /* After the PCI bus scan is complete, we can register
  341. * the error interrupt handlers.
  342. */
  343. psycho_register_error_handlers(pbm);
  344. }
  345. #define PSYCHO_IRQ_RETRY 0x1a00UL
  346. #define PSYCHO_PCIA_DIAG 0x2020UL
  347. #define PSYCHO_PCIB_DIAG 0x4020UL
  348. #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
  349. #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
  350. #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
  351. #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
  352. #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
  353. #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
  354. #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
  355. #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
  356. static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
  357. {
  358. u64 tmp;
  359. upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY);
  360. /* Enable arbiter for all PCI slots. */
  361. tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL);
  362. tmp |= PSYCHO_PCICTRL_AEN;
  363. upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL);
  364. tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL);
  365. tmp |= PSYCHO_PCICTRL_AEN;
  366. upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL);
  367. /* Disable DMA write / PIO read synchronization on
  368. * both PCI bus segments.
  369. * [ U2P Erratum 1243770, STP2223BGA data sheet ]
  370. */
  371. tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG);
  372. tmp |= PSYCHO_PCIDIAG_DDWSYNC;
  373. upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG);
  374. tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG);
  375. tmp |= PSYCHO_PCIDIAG_DDWSYNC;
  376. upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG);
  377. }
  378. static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
  379. int is_pbm_a)
  380. {
  381. unsigned long base = pbm->controller_regs;
  382. u64 control;
  383. if (is_pbm_a) {
  384. pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
  385. pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
  386. pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
  387. pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A;
  388. pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A;
  389. pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A;
  390. } else {
  391. pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
  392. pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
  393. pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
  394. pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B;
  395. pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B;
  396. pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B;
  397. }
  398. /* PSYCHO's streaming buffer lacks ctx flushing. */
  399. pbm->stc.strbuf_ctxflush = 0;
  400. pbm->stc.strbuf_ctxmatch_base = 0;
  401. pbm->stc.strbuf_flushflag = (volatile unsigned long *)
  402. ((((unsigned long)&pbm->stc.__flushflag_buf[0])
  403. + 63UL)
  404. & ~63UL);
  405. pbm->stc.strbuf_flushflag_pa = (unsigned long)
  406. __pa(pbm->stc.strbuf_flushflag);
  407. /* Enable the streaming buffer. We have to be careful
  408. * just in case OBP left it with LRU locking enabled.
  409. *
  410. * It is possible to control if PBM will be rerun on
  411. * line misses. Currently I just retain whatever setting
  412. * OBP left us with. All checks so far show it having
  413. * a value of zero.
  414. */
  415. #undef PSYCHO_STRBUF_RERUN_ENABLE
  416. #undef PSYCHO_STRBUF_RERUN_DISABLE
  417. control = upa_readq(pbm->stc.strbuf_control);
  418. control |= PSYCHO_STRBUF_CTRL_ENAB;
  419. control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
  420. #ifdef PSYCHO_STRBUF_RERUN_ENABLE
  421. control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
  422. #else
  423. #ifdef PSYCHO_STRBUF_RERUN_DISABLE
  424. control |= PSYCHO_STRBUF_CTRL_RRDIS;
  425. #endif
  426. #endif
  427. upa_writeq(control, pbm->stc.strbuf_control);
  428. pbm->stc.strbuf_enabled = 1;
  429. }
  430. #define PSYCHO_IOSPACE_A 0x002000000UL
  431. #define PSYCHO_IOSPACE_B 0x002010000UL
  432. #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
  433. #define PSYCHO_MEMSPACE_A 0x100000000UL
  434. #define PSYCHO_MEMSPACE_B 0x180000000UL
  435. #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
  436. static void psycho_pbm_init(struct pci_pbm_info *pbm,
  437. struct platform_device *op, int is_pbm_a)
  438. {
  439. psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO);
  440. psycho_pbm_strbuf_init(pbm, is_pbm_a);
  441. psycho_scan_bus(pbm, &op->dev);
  442. }
  443. static struct pci_pbm_info *psycho_find_sibling(u32 upa_portid)
  444. {
  445. struct pci_pbm_info *pbm;
  446. for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
  447. if (pbm->portid == upa_portid)
  448. return pbm;
  449. }
  450. return NULL;
  451. }
  452. #define PSYCHO_CONFIGSPACE 0x001000000UL
  453. static int psycho_probe(struct platform_device *op)
  454. {
  455. const struct linux_prom64_registers *pr_regs;
  456. struct device_node *dp = op->dev.of_node;
  457. struct pci_pbm_info *pbm;
  458. struct iommu *iommu;
  459. int is_pbm_a, err;
  460. u32 upa_portid;
  461. upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
  462. err = -ENOMEM;
  463. pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
  464. if (!pbm) {
  465. printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
  466. goto out_err;
  467. }
  468. pbm->sibling = psycho_find_sibling(upa_portid);
  469. if (pbm->sibling) {
  470. iommu = pbm->sibling->iommu;
  471. } else {
  472. iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
  473. if (!iommu) {
  474. printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
  475. goto out_free_controller;
  476. }
  477. }
  478. pbm->iommu = iommu;
  479. pbm->portid = upa_portid;
  480. pr_regs = of_get_property(dp, "reg", NULL);
  481. err = -ENODEV;
  482. if (!pr_regs) {
  483. printk(KERN_ERR PFX "No reg property.\n");
  484. goto out_free_iommu;
  485. }
  486. is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
  487. pbm->controller_regs = pr_regs[2].phys_addr;
  488. pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
  489. if (is_pbm_a) {
  490. pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A;
  491. pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A;
  492. pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL;
  493. } else {
  494. pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B;
  495. pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B;
  496. pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL;
  497. }
  498. psycho_controller_hwinit(pbm);
  499. if (!pbm->sibling) {
  500. err = psycho_iommu_init(pbm, 128, 0xc0000000,
  501. 0xffffffff, PSYCHO_CONTROL);
  502. if (err)
  503. goto out_free_iommu;
  504. /* If necessary, hook us up for starfire IRQ translations. */
  505. if (this_is_starfire)
  506. starfire_hookup(pbm->portid);
  507. }
  508. psycho_pbm_init(pbm, op, is_pbm_a);
  509. pbm->next = pci_pbm_root;
  510. pci_pbm_root = pbm;
  511. if (pbm->sibling)
  512. pbm->sibling->sibling = pbm;
  513. dev_set_drvdata(&op->dev, pbm);
  514. return 0;
  515. out_free_iommu:
  516. if (!pbm->sibling)
  517. kfree(pbm->iommu);
  518. out_free_controller:
  519. kfree(pbm);
  520. out_err:
  521. return err;
  522. }
  523. static const struct of_device_id psycho_match[] = {
  524. {
  525. .name = "pci",
  526. .compatible = "pci108e,8000",
  527. },
  528. {},
  529. };
  530. static struct platform_driver psycho_driver = {
  531. .driver = {
  532. .name = DRIVER_NAME,
  533. .of_match_table = psycho_match,
  534. },
  535. .probe = psycho_probe,
  536. };
  537. static int __init psycho_init(void)
  538. {
  539. return platform_driver_register(&psycho_driver);
  540. }
  541. subsys_initcall(psycho_init);