pci_msi.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* pci_msi.c: Sparc64 MSI support common layer.
  3. *
  4. * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/slab.h>
  9. #include <linux/irq.h>
  10. #include "pci_impl.h"
  11. static irqreturn_t sparc64_msiq_interrupt(int irq, void *cookie)
  12. {
  13. struct sparc64_msiq_cookie *msiq_cookie = cookie;
  14. struct pci_pbm_info *pbm = msiq_cookie->pbm;
  15. unsigned long msiqid = msiq_cookie->msiqid;
  16. const struct sparc64_msiq_ops *ops;
  17. unsigned long orig_head, head;
  18. int err;
  19. ops = pbm->msi_ops;
  20. err = ops->get_head(pbm, msiqid, &head);
  21. if (unlikely(err < 0))
  22. goto err_get_head;
  23. orig_head = head;
  24. for (;;) {
  25. unsigned long msi;
  26. err = ops->dequeue_msi(pbm, msiqid, &head, &msi);
  27. if (likely(err > 0)) {
  28. unsigned int irq;
  29. irq = pbm->msi_irq_table[msi - pbm->msi_first];
  30. generic_handle_irq(irq);
  31. }
  32. if (unlikely(err < 0))
  33. goto err_dequeue;
  34. if (err == 0)
  35. break;
  36. }
  37. if (likely(head != orig_head)) {
  38. err = ops->set_head(pbm, msiqid, head);
  39. if (unlikely(err < 0))
  40. goto err_set_head;
  41. }
  42. return IRQ_HANDLED;
  43. err_get_head:
  44. printk(KERN_EMERG "MSI: Get head on msiqid[%lu] gives error %d\n",
  45. msiqid, err);
  46. goto err_out;
  47. err_dequeue:
  48. printk(KERN_EMERG "MSI: Dequeue head[%lu] from msiqid[%lu] "
  49. "gives error %d\n",
  50. head, msiqid, err);
  51. goto err_out;
  52. err_set_head:
  53. printk(KERN_EMERG "MSI: Set head[%lu] on msiqid[%lu] "
  54. "gives error %d\n",
  55. head, msiqid, err);
  56. goto err_out;
  57. err_out:
  58. return IRQ_NONE;
  59. }
  60. static u32 pick_msiq(struct pci_pbm_info *pbm)
  61. {
  62. static DEFINE_SPINLOCK(rotor_lock);
  63. unsigned long flags;
  64. u32 ret, rotor;
  65. spin_lock_irqsave(&rotor_lock, flags);
  66. rotor = pbm->msiq_rotor;
  67. ret = pbm->msiq_first + rotor;
  68. if (++rotor >= pbm->msiq_num)
  69. rotor = 0;
  70. pbm->msiq_rotor = rotor;
  71. spin_unlock_irqrestore(&rotor_lock, flags);
  72. return ret;
  73. }
  74. static int alloc_msi(struct pci_pbm_info *pbm)
  75. {
  76. int i;
  77. for (i = 0; i < pbm->msi_num; i++) {
  78. if (!test_and_set_bit(i, pbm->msi_bitmap))
  79. return i + pbm->msi_first;
  80. }
  81. return -ENOENT;
  82. }
  83. static void free_msi(struct pci_pbm_info *pbm, int msi_num)
  84. {
  85. msi_num -= pbm->msi_first;
  86. clear_bit(msi_num, pbm->msi_bitmap);
  87. }
  88. static struct irq_chip msi_irq = {
  89. .name = "PCI-MSI",
  90. .irq_mask = pci_msi_mask_irq,
  91. .irq_unmask = pci_msi_unmask_irq,
  92. .irq_enable = pci_msi_unmask_irq,
  93. .irq_disable = pci_msi_mask_irq,
  94. /* XXX affinity XXX */
  95. };
  96. static int sparc64_setup_msi_irq(unsigned int *irq_p,
  97. struct pci_dev *pdev,
  98. struct msi_desc *entry)
  99. {
  100. struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
  101. const struct sparc64_msiq_ops *ops = pbm->msi_ops;
  102. struct msi_msg msg;
  103. int msi, err;
  104. u32 msiqid;
  105. *irq_p = irq_alloc(0, 0);
  106. err = -ENOMEM;
  107. if (!*irq_p)
  108. goto out_err;
  109. irq_set_chip_and_handler_name(*irq_p, &msi_irq, handle_simple_irq,
  110. "MSI");
  111. err = alloc_msi(pbm);
  112. if (unlikely(err < 0))
  113. goto out_irq_free;
  114. msi = err;
  115. msiqid = pick_msiq(pbm);
  116. err = ops->msi_setup(pbm, msiqid, msi,
  117. (entry->msi_attrib.is_64 ? 1 : 0));
  118. if (err)
  119. goto out_msi_free;
  120. pbm->msi_irq_table[msi - pbm->msi_first] = *irq_p;
  121. if (entry->msi_attrib.is_64) {
  122. msg.address_hi = pbm->msi64_start >> 32;
  123. msg.address_lo = pbm->msi64_start & 0xffffffff;
  124. } else {
  125. msg.address_hi = 0;
  126. msg.address_lo = pbm->msi32_start;
  127. }
  128. msg.data = msi;
  129. irq_set_msi_desc(*irq_p, entry);
  130. pci_write_msi_msg(*irq_p, &msg);
  131. return 0;
  132. out_msi_free:
  133. free_msi(pbm, msi);
  134. out_irq_free:
  135. irq_set_chip(*irq_p, NULL);
  136. irq_free(*irq_p);
  137. *irq_p = 0;
  138. out_err:
  139. return err;
  140. }
  141. static void sparc64_teardown_msi_irq(unsigned int irq,
  142. struct pci_dev *pdev)
  143. {
  144. struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
  145. const struct sparc64_msiq_ops *ops = pbm->msi_ops;
  146. unsigned int msi_num;
  147. int i, err;
  148. for (i = 0; i < pbm->msi_num; i++) {
  149. if (pbm->msi_irq_table[i] == irq)
  150. break;
  151. }
  152. if (i >= pbm->msi_num) {
  153. pci_err(pdev, "%s: teardown: No MSI for irq %u\n", pbm->name,
  154. irq);
  155. return;
  156. }
  157. msi_num = pbm->msi_first + i;
  158. pbm->msi_irq_table[i] = ~0U;
  159. err = ops->msi_teardown(pbm, msi_num);
  160. if (err) {
  161. pci_err(pdev, "%s: teardown: ops->teardown() on MSI %u, "
  162. "irq %u, gives error %d\n", pbm->name, msi_num, irq,
  163. err);
  164. return;
  165. }
  166. free_msi(pbm, msi_num);
  167. irq_set_chip(irq, NULL);
  168. irq_free(irq);
  169. }
  170. static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
  171. {
  172. unsigned long size, bits_per_ulong;
  173. bits_per_ulong = sizeof(unsigned long) * 8;
  174. size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
  175. size /= 8;
  176. BUG_ON(size % sizeof(unsigned long));
  177. pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
  178. if (!pbm->msi_bitmap)
  179. return -ENOMEM;
  180. return 0;
  181. }
  182. static void msi_bitmap_free(struct pci_pbm_info *pbm)
  183. {
  184. kfree(pbm->msi_bitmap);
  185. pbm->msi_bitmap = NULL;
  186. }
  187. static int msi_table_alloc(struct pci_pbm_info *pbm)
  188. {
  189. int size, i;
  190. size = pbm->msiq_num * sizeof(struct sparc64_msiq_cookie);
  191. pbm->msiq_irq_cookies = kzalloc(size, GFP_KERNEL);
  192. if (!pbm->msiq_irq_cookies)
  193. return -ENOMEM;
  194. for (i = 0; i < pbm->msiq_num; i++) {
  195. struct sparc64_msiq_cookie *p;
  196. p = &pbm->msiq_irq_cookies[i];
  197. p->pbm = pbm;
  198. p->msiqid = pbm->msiq_first + i;
  199. }
  200. size = pbm->msi_num * sizeof(unsigned int);
  201. pbm->msi_irq_table = kzalloc(size, GFP_KERNEL);
  202. if (!pbm->msi_irq_table) {
  203. kfree(pbm->msiq_irq_cookies);
  204. pbm->msiq_irq_cookies = NULL;
  205. return -ENOMEM;
  206. }
  207. return 0;
  208. }
  209. static void msi_table_free(struct pci_pbm_info *pbm)
  210. {
  211. kfree(pbm->msiq_irq_cookies);
  212. pbm->msiq_irq_cookies = NULL;
  213. kfree(pbm->msi_irq_table);
  214. pbm->msi_irq_table = NULL;
  215. }
  216. static int bringup_one_msi_queue(struct pci_pbm_info *pbm,
  217. const struct sparc64_msiq_ops *ops,
  218. unsigned long msiqid,
  219. unsigned long devino)
  220. {
  221. int irq = ops->msiq_build_irq(pbm, msiqid, devino);
  222. int err, nid;
  223. if (irq < 0)
  224. return irq;
  225. nid = pbm->numa_node;
  226. if (nid != -1) {
  227. cpumask_t numa_mask;
  228. cpumask_copy(&numa_mask, cpumask_of_node(nid));
  229. irq_set_affinity(irq, &numa_mask);
  230. }
  231. err = request_irq(irq, sparc64_msiq_interrupt, 0,
  232. "MSIQ",
  233. &pbm->msiq_irq_cookies[msiqid - pbm->msiq_first]);
  234. if (err)
  235. return err;
  236. return 0;
  237. }
  238. static int sparc64_bringup_msi_queues(struct pci_pbm_info *pbm,
  239. const struct sparc64_msiq_ops *ops)
  240. {
  241. int i;
  242. for (i = 0; i < pbm->msiq_num; i++) {
  243. unsigned long msiqid = i + pbm->msiq_first;
  244. unsigned long devino = i + pbm->msiq_first_devino;
  245. int err;
  246. err = bringup_one_msi_queue(pbm, ops, msiqid, devino);
  247. if (err)
  248. return err;
  249. }
  250. return 0;
  251. }
  252. void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
  253. const struct sparc64_msiq_ops *ops)
  254. {
  255. const u32 *val;
  256. int len;
  257. val = of_get_property(pbm->op->dev.of_node, "#msi-eqs", &len);
  258. if (!val || len != 4)
  259. goto no_msi;
  260. pbm->msiq_num = *val;
  261. if (pbm->msiq_num) {
  262. const struct msiq_prop {
  263. u32 first_msiq;
  264. u32 num_msiq;
  265. u32 first_devino;
  266. } *mqp;
  267. const struct msi_range_prop {
  268. u32 first_msi;
  269. u32 num_msi;
  270. } *mrng;
  271. const struct addr_range_prop {
  272. u32 msi32_high;
  273. u32 msi32_low;
  274. u32 msi32_len;
  275. u32 msi64_high;
  276. u32 msi64_low;
  277. u32 msi64_len;
  278. } *arng;
  279. val = of_get_property(pbm->op->dev.of_node, "msi-eq-size", &len);
  280. if (!val || len != 4)
  281. goto no_msi;
  282. pbm->msiq_ent_count = *val;
  283. mqp = of_get_property(pbm->op->dev.of_node,
  284. "msi-eq-to-devino", &len);
  285. if (!mqp)
  286. mqp = of_get_property(pbm->op->dev.of_node,
  287. "msi-eq-devino", &len);
  288. if (!mqp || len != sizeof(struct msiq_prop))
  289. goto no_msi;
  290. pbm->msiq_first = mqp->first_msiq;
  291. pbm->msiq_first_devino = mqp->first_devino;
  292. val = of_get_property(pbm->op->dev.of_node, "#msi", &len);
  293. if (!val || len != 4)
  294. goto no_msi;
  295. pbm->msi_num = *val;
  296. mrng = of_get_property(pbm->op->dev.of_node, "msi-ranges", &len);
  297. if (!mrng || len != sizeof(struct msi_range_prop))
  298. goto no_msi;
  299. pbm->msi_first = mrng->first_msi;
  300. val = of_get_property(pbm->op->dev.of_node, "msi-data-mask", &len);
  301. if (!val || len != 4)
  302. goto no_msi;
  303. pbm->msi_data_mask = *val;
  304. val = of_get_property(pbm->op->dev.of_node, "msix-data-width", &len);
  305. if (!val || len != 4)
  306. goto no_msi;
  307. pbm->msix_data_width = *val;
  308. arng = of_get_property(pbm->op->dev.of_node, "msi-address-ranges",
  309. &len);
  310. if (!arng || len != sizeof(struct addr_range_prop))
  311. goto no_msi;
  312. pbm->msi32_start = ((u64)arng->msi32_high << 32) |
  313. (u64) arng->msi32_low;
  314. pbm->msi64_start = ((u64)arng->msi64_high << 32) |
  315. (u64) arng->msi64_low;
  316. pbm->msi32_len = arng->msi32_len;
  317. pbm->msi64_len = arng->msi64_len;
  318. if (msi_bitmap_alloc(pbm))
  319. goto no_msi;
  320. if (msi_table_alloc(pbm)) {
  321. msi_bitmap_free(pbm);
  322. goto no_msi;
  323. }
  324. if (ops->msiq_alloc(pbm)) {
  325. msi_table_free(pbm);
  326. msi_bitmap_free(pbm);
  327. goto no_msi;
  328. }
  329. if (sparc64_bringup_msi_queues(pbm, ops)) {
  330. ops->msiq_free(pbm);
  331. msi_table_free(pbm);
  332. msi_bitmap_free(pbm);
  333. goto no_msi;
  334. }
  335. printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
  336. "devino[0x%x]\n",
  337. pbm->name,
  338. pbm->msiq_first, pbm->msiq_num,
  339. pbm->msiq_ent_count,
  340. pbm->msiq_first_devino);
  341. printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
  342. "width[%u]\n",
  343. pbm->name,
  344. pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
  345. pbm->msix_data_width);
  346. printk(KERN_INFO "%s: MSI addr32[0x%llx:0x%x] "
  347. "addr64[0x%llx:0x%x]\n",
  348. pbm->name,
  349. pbm->msi32_start, pbm->msi32_len,
  350. pbm->msi64_start, pbm->msi64_len);
  351. printk(KERN_INFO "%s: MSI queues at RA [%016lx]\n",
  352. pbm->name,
  353. __pa(pbm->msi_queues));
  354. pbm->msi_ops = ops;
  355. pbm->setup_msi_irq = sparc64_setup_msi_irq;
  356. pbm->teardown_msi_irq = sparc64_teardown_msi_irq;
  357. }
  358. return;
  359. no_msi:
  360. pbm->msiq_num = 0;
  361. printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
  362. }