pci_common.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* pci_common.c: PCI controller common support.
  3. *
  4. * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
  5. */
  6. #include <linux/string.h>
  7. #include <linux/slab.h>
  8. #include <linux/pci.h>
  9. #include <linux/device.h>
  10. #include <linux/of_device.h>
  11. #include <asm/prom.h>
  12. #include <asm/oplib.h>
  13. #include "pci_impl.h"
  14. #include "pci_sun4v.h"
  15. static int config_out_of_range(struct pci_pbm_info *pbm,
  16. unsigned long bus,
  17. unsigned long devfn,
  18. unsigned long reg)
  19. {
  20. if (bus < pbm->pci_first_busno ||
  21. bus > pbm->pci_last_busno)
  22. return 1;
  23. return 0;
  24. }
  25. static void *sun4u_config_mkaddr(struct pci_pbm_info *pbm,
  26. unsigned long bus,
  27. unsigned long devfn,
  28. unsigned long reg)
  29. {
  30. unsigned long rbits = pbm->config_space_reg_bits;
  31. if (config_out_of_range(pbm, bus, devfn, reg))
  32. return NULL;
  33. reg = (reg & ((1 << rbits) - 1));
  34. devfn <<= rbits;
  35. bus <<= rbits + 8;
  36. return (void *) (pbm->config_space | bus | devfn | reg);
  37. }
  38. /* At least on Sabre, it is necessary to access all PCI host controller
  39. * registers at their natural size, otherwise zeros are returned.
  40. * Strange but true, and I see no language in the UltraSPARC-IIi
  41. * programmer's manual that mentions this even indirectly.
  42. */
  43. static int sun4u_read_pci_cfg_host(struct pci_pbm_info *pbm,
  44. unsigned char bus, unsigned int devfn,
  45. int where, int size, u32 *value)
  46. {
  47. u32 tmp32, *addr;
  48. u16 tmp16;
  49. u8 tmp8;
  50. addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
  51. if (!addr)
  52. return PCIBIOS_SUCCESSFUL;
  53. switch (size) {
  54. case 1:
  55. if (where < 8) {
  56. unsigned long align = (unsigned long) addr;
  57. align &= ~1;
  58. pci_config_read16((u16 *)align, &tmp16);
  59. if (where & 1)
  60. *value = tmp16 >> 8;
  61. else
  62. *value = tmp16 & 0xff;
  63. } else {
  64. pci_config_read8((u8 *)addr, &tmp8);
  65. *value = (u32) tmp8;
  66. }
  67. break;
  68. case 2:
  69. if (where < 8) {
  70. pci_config_read16((u16 *)addr, &tmp16);
  71. *value = (u32) tmp16;
  72. } else {
  73. pci_config_read8((u8 *)addr, &tmp8);
  74. *value = (u32) tmp8;
  75. pci_config_read8(((u8 *)addr) + 1, &tmp8);
  76. *value |= ((u32) tmp8) << 8;
  77. }
  78. break;
  79. case 4:
  80. tmp32 = 0xffffffff;
  81. sun4u_read_pci_cfg_host(pbm, bus, devfn,
  82. where, 2, &tmp32);
  83. *value = tmp32;
  84. tmp32 = 0xffffffff;
  85. sun4u_read_pci_cfg_host(pbm, bus, devfn,
  86. where + 2, 2, &tmp32);
  87. *value |= tmp32 << 16;
  88. break;
  89. }
  90. return PCIBIOS_SUCCESSFUL;
  91. }
  92. static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
  93. int where, int size, u32 *value)
  94. {
  95. struct pci_pbm_info *pbm = bus_dev->sysdata;
  96. unsigned char bus = bus_dev->number;
  97. u32 *addr;
  98. u16 tmp16;
  99. u8 tmp8;
  100. switch (size) {
  101. case 1:
  102. *value = 0xff;
  103. break;
  104. case 2:
  105. *value = 0xffff;
  106. break;
  107. case 4:
  108. *value = 0xffffffff;
  109. break;
  110. }
  111. if (!bus_dev->number && !PCI_SLOT(devfn))
  112. return sun4u_read_pci_cfg_host(pbm, bus, devfn, where,
  113. size, value);
  114. addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
  115. if (!addr)
  116. return PCIBIOS_SUCCESSFUL;
  117. switch (size) {
  118. case 1:
  119. pci_config_read8((u8 *)addr, &tmp8);
  120. *value = (u32) tmp8;
  121. break;
  122. case 2:
  123. if (where & 0x01) {
  124. printk("pci_read_config_word: misaligned reg [%x]\n",
  125. where);
  126. return PCIBIOS_SUCCESSFUL;
  127. }
  128. pci_config_read16((u16 *)addr, &tmp16);
  129. *value = (u32) tmp16;
  130. break;
  131. case 4:
  132. if (where & 0x03) {
  133. printk("pci_read_config_dword: misaligned reg [%x]\n",
  134. where);
  135. return PCIBIOS_SUCCESSFUL;
  136. }
  137. pci_config_read32(addr, value);
  138. break;
  139. }
  140. return PCIBIOS_SUCCESSFUL;
  141. }
  142. static int sun4u_write_pci_cfg_host(struct pci_pbm_info *pbm,
  143. unsigned char bus, unsigned int devfn,
  144. int where, int size, u32 value)
  145. {
  146. u32 *addr;
  147. addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
  148. if (!addr)
  149. return PCIBIOS_SUCCESSFUL;
  150. switch (size) {
  151. case 1:
  152. if (where < 8) {
  153. unsigned long align = (unsigned long) addr;
  154. u16 tmp16;
  155. align &= ~1;
  156. pci_config_read16((u16 *)align, &tmp16);
  157. if (where & 1) {
  158. tmp16 &= 0x00ff;
  159. tmp16 |= value << 8;
  160. } else {
  161. tmp16 &= 0xff00;
  162. tmp16 |= value;
  163. }
  164. pci_config_write16((u16 *)align, tmp16);
  165. } else
  166. pci_config_write8((u8 *)addr, value);
  167. break;
  168. case 2:
  169. if (where < 8) {
  170. pci_config_write16((u16 *)addr, value);
  171. } else {
  172. pci_config_write8((u8 *)addr, value & 0xff);
  173. pci_config_write8(((u8 *)addr) + 1, value >> 8);
  174. }
  175. break;
  176. case 4:
  177. sun4u_write_pci_cfg_host(pbm, bus, devfn,
  178. where, 2, value & 0xffff);
  179. sun4u_write_pci_cfg_host(pbm, bus, devfn,
  180. where + 2, 2, value >> 16);
  181. break;
  182. }
  183. return PCIBIOS_SUCCESSFUL;
  184. }
  185. static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
  186. int where, int size, u32 value)
  187. {
  188. struct pci_pbm_info *pbm = bus_dev->sysdata;
  189. unsigned char bus = bus_dev->number;
  190. u32 *addr;
  191. if (!bus_dev->number && !PCI_SLOT(devfn))
  192. return sun4u_write_pci_cfg_host(pbm, bus, devfn, where,
  193. size, value);
  194. addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
  195. if (!addr)
  196. return PCIBIOS_SUCCESSFUL;
  197. switch (size) {
  198. case 1:
  199. pci_config_write8((u8 *)addr, value);
  200. break;
  201. case 2:
  202. if (where & 0x01) {
  203. printk("pci_write_config_word: misaligned reg [%x]\n",
  204. where);
  205. return PCIBIOS_SUCCESSFUL;
  206. }
  207. pci_config_write16((u16 *)addr, value);
  208. break;
  209. case 4:
  210. if (where & 0x03) {
  211. printk("pci_write_config_dword: misaligned reg [%x]\n",
  212. where);
  213. return PCIBIOS_SUCCESSFUL;
  214. }
  215. pci_config_write32(addr, value);
  216. }
  217. return PCIBIOS_SUCCESSFUL;
  218. }
  219. struct pci_ops sun4u_pci_ops = {
  220. .read = sun4u_read_pci_cfg,
  221. .write = sun4u_write_pci_cfg,
  222. };
  223. static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
  224. int where, int size, u32 *value)
  225. {
  226. struct pci_pbm_info *pbm = bus_dev->sysdata;
  227. u32 devhandle = pbm->devhandle;
  228. unsigned int bus = bus_dev->number;
  229. unsigned int device = PCI_SLOT(devfn);
  230. unsigned int func = PCI_FUNC(devfn);
  231. unsigned long ret;
  232. if (config_out_of_range(pbm, bus, devfn, where)) {
  233. ret = ~0UL;
  234. } else {
  235. ret = pci_sun4v_config_get(devhandle,
  236. HV_PCI_DEVICE_BUILD(bus, device, func),
  237. where, size);
  238. }
  239. switch (size) {
  240. case 1:
  241. *value = ret & 0xff;
  242. break;
  243. case 2:
  244. *value = ret & 0xffff;
  245. break;
  246. case 4:
  247. *value = ret & 0xffffffff;
  248. break;
  249. }
  250. return PCIBIOS_SUCCESSFUL;
  251. }
  252. static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
  253. int where, int size, u32 value)
  254. {
  255. struct pci_pbm_info *pbm = bus_dev->sysdata;
  256. u32 devhandle = pbm->devhandle;
  257. unsigned int bus = bus_dev->number;
  258. unsigned int device = PCI_SLOT(devfn);
  259. unsigned int func = PCI_FUNC(devfn);
  260. if (config_out_of_range(pbm, bus, devfn, where)) {
  261. /* Do nothing. */
  262. } else {
  263. /* We don't check for hypervisor errors here, but perhaps
  264. * we should and influence our return value depending upon
  265. * what kind of error is thrown.
  266. */
  267. pci_sun4v_config_put(devhandle,
  268. HV_PCI_DEVICE_BUILD(bus, device, func),
  269. where, size, value);
  270. }
  271. return PCIBIOS_SUCCESSFUL;
  272. }
  273. struct pci_ops sun4v_pci_ops = {
  274. .read = sun4v_read_pci_cfg,
  275. .write = sun4v_write_pci_cfg,
  276. };
  277. void pci_get_pbm_props(struct pci_pbm_info *pbm)
  278. {
  279. const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL);
  280. pbm->pci_first_busno = val[0];
  281. pbm->pci_last_busno = val[1];
  282. val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL);
  283. if (val) {
  284. pbm->ino_bitmap = (((u64)val[1] << 32UL) |
  285. ((u64)val[0] << 0UL));
  286. }
  287. }
  288. static void pci_register_iommu_region(struct pci_pbm_info *pbm)
  289. {
  290. const u32 *vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma",
  291. NULL);
  292. if (vdma) {
  293. struct resource *rp = kzalloc(sizeof(*rp), GFP_KERNEL);
  294. if (!rp) {
  295. pr_info("%s: Cannot allocate IOMMU resource.\n",
  296. pbm->name);
  297. return;
  298. }
  299. rp->name = "IOMMU";
  300. rp->start = pbm->mem_space.start + (unsigned long) vdma[0];
  301. rp->end = rp->start + (unsigned long) vdma[1] - 1UL;
  302. rp->flags = IORESOURCE_BUSY;
  303. if (request_resource(&pbm->mem_space, rp)) {
  304. pr_info("%s: Unable to request IOMMU resource.\n",
  305. pbm->name);
  306. kfree(rp);
  307. }
  308. }
  309. }
  310. void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
  311. {
  312. const struct linux_prom_pci_ranges *pbm_ranges;
  313. int i, saw_mem, saw_io;
  314. int num_pbm_ranges;
  315. /* Corresponding generic code in of_pci_get_host_bridge_resources() */
  316. saw_mem = saw_io = 0;
  317. pbm_ranges = of_get_property(pbm->op->dev.of_node, "ranges", &i);
  318. if (!pbm_ranges) {
  319. prom_printf("PCI: Fatal error, missing PBM ranges property "
  320. " for %s\n",
  321. pbm->name);
  322. prom_halt();
  323. }
  324. num_pbm_ranges = i / sizeof(*pbm_ranges);
  325. memset(&pbm->mem64_space, 0, sizeof(struct resource));
  326. for (i = 0; i < num_pbm_ranges; i++) {
  327. const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
  328. unsigned long a, size, region_a;
  329. u32 parent_phys_hi, parent_phys_lo;
  330. u32 child_phys_mid, child_phys_lo;
  331. u32 size_hi, size_lo;
  332. int type;
  333. parent_phys_hi = pr->parent_phys_hi;
  334. parent_phys_lo = pr->parent_phys_lo;
  335. child_phys_mid = pr->child_phys_mid;
  336. child_phys_lo = pr->child_phys_lo;
  337. if (tlb_type == hypervisor)
  338. parent_phys_hi &= 0x0fffffff;
  339. size_hi = pr->size_hi;
  340. size_lo = pr->size_lo;
  341. type = (pr->child_phys_hi >> 24) & 0x3;
  342. a = (((unsigned long)parent_phys_hi << 32UL) |
  343. ((unsigned long)parent_phys_lo << 0UL));
  344. region_a = (((unsigned long)child_phys_mid << 32UL) |
  345. ((unsigned long)child_phys_lo << 0UL));
  346. size = (((unsigned long)size_hi << 32UL) |
  347. ((unsigned long)size_lo << 0UL));
  348. switch (type) {
  349. case 0:
  350. /* PCI config space, 16MB */
  351. pbm->config_space = a;
  352. break;
  353. case 1:
  354. /* 16-bit IO space, 16MB */
  355. pbm->io_space.start = a;
  356. pbm->io_space.end = a + size - 1UL;
  357. pbm->io_space.flags = IORESOURCE_IO;
  358. pbm->io_offset = a - region_a;
  359. saw_io = 1;
  360. break;
  361. case 2:
  362. /* 32-bit MEM space, 2GB */
  363. pbm->mem_space.start = a;
  364. pbm->mem_space.end = a + size - 1UL;
  365. pbm->mem_space.flags = IORESOURCE_MEM;
  366. pbm->mem_offset = a - region_a;
  367. saw_mem = 1;
  368. break;
  369. case 3:
  370. /* 64-bit MEM handling */
  371. pbm->mem64_space.start = a;
  372. pbm->mem64_space.end = a + size - 1UL;
  373. pbm->mem64_space.flags = IORESOURCE_MEM;
  374. pbm->mem64_offset = a - region_a;
  375. saw_mem = 1;
  376. break;
  377. default:
  378. break;
  379. }
  380. }
  381. if (!saw_io || !saw_mem) {
  382. prom_printf("%s: Fatal error, missing %s PBM range.\n",
  383. pbm->name,
  384. (!saw_io ? "IO" : "MEM"));
  385. prom_halt();
  386. }
  387. if (pbm->io_space.flags)
  388. printk("%s: PCI IO %pR offset %llx\n",
  389. pbm->name, &pbm->io_space, pbm->io_offset);
  390. if (pbm->mem_space.flags)
  391. printk("%s: PCI MEM %pR offset %llx\n",
  392. pbm->name, &pbm->mem_space, pbm->mem_offset);
  393. if (pbm->mem64_space.flags && pbm->mem_space.flags) {
  394. if (pbm->mem64_space.start <= pbm->mem_space.end)
  395. pbm->mem64_space.start = pbm->mem_space.end + 1;
  396. if (pbm->mem64_space.start > pbm->mem64_space.end)
  397. pbm->mem64_space.flags = 0;
  398. }
  399. if (pbm->mem64_space.flags)
  400. printk("%s: PCI MEM64 %pR offset %llx\n",
  401. pbm->name, &pbm->mem64_space, pbm->mem64_offset);
  402. pbm->io_space.name = pbm->mem_space.name = pbm->name;
  403. pbm->mem64_space.name = pbm->name;
  404. request_resource(&ioport_resource, &pbm->io_space);
  405. request_resource(&iomem_resource, &pbm->mem_space);
  406. if (pbm->mem64_space.flags)
  407. request_resource(&iomem_resource, &pbm->mem64_space);
  408. pci_register_iommu_region(pbm);
  409. }
  410. /* Generic helper routines for PCI error reporting. */
  411. void pci_scan_for_target_abort(struct pci_pbm_info *pbm,
  412. struct pci_bus *pbus)
  413. {
  414. struct pci_dev *pdev;
  415. struct pci_bus *bus;
  416. list_for_each_entry(pdev, &pbus->devices, bus_list) {
  417. u16 status, error_bits;
  418. pci_read_config_word(pdev, PCI_STATUS, &status);
  419. error_bits =
  420. (status & (PCI_STATUS_SIG_TARGET_ABORT |
  421. PCI_STATUS_REC_TARGET_ABORT));
  422. if (error_bits) {
  423. pci_write_config_word(pdev, PCI_STATUS, error_bits);
  424. pci_info(pdev, "%s: Device saw Target Abort [%016x]\n",
  425. pbm->name, status);
  426. }
  427. }
  428. list_for_each_entry(bus, &pbus->children, node)
  429. pci_scan_for_target_abort(pbm, bus);
  430. }
  431. void pci_scan_for_master_abort(struct pci_pbm_info *pbm,
  432. struct pci_bus *pbus)
  433. {
  434. struct pci_dev *pdev;
  435. struct pci_bus *bus;
  436. list_for_each_entry(pdev, &pbus->devices, bus_list) {
  437. u16 status, error_bits;
  438. pci_read_config_word(pdev, PCI_STATUS, &status);
  439. error_bits =
  440. (status & (PCI_STATUS_REC_MASTER_ABORT));
  441. if (error_bits) {
  442. pci_write_config_word(pdev, PCI_STATUS, error_bits);
  443. pci_info(pdev, "%s: Device received Master Abort "
  444. "[%016x]\n", pbm->name, status);
  445. }
  446. }
  447. list_for_each_entry(bus, &pbus->children, node)
  448. pci_scan_for_master_abort(pbm, bus);
  449. }
  450. void pci_scan_for_parity_error(struct pci_pbm_info *pbm,
  451. struct pci_bus *pbus)
  452. {
  453. struct pci_dev *pdev;
  454. struct pci_bus *bus;
  455. list_for_each_entry(pdev, &pbus->devices, bus_list) {
  456. u16 status, error_bits;
  457. pci_read_config_word(pdev, PCI_STATUS, &status);
  458. error_bits =
  459. (status & (PCI_STATUS_PARITY |
  460. PCI_STATUS_DETECTED_PARITY));
  461. if (error_bits) {
  462. pci_write_config_word(pdev, PCI_STATUS, error_bits);
  463. pci_info(pdev, "%s: Device saw Parity Error [%016x]\n",
  464. pbm->name, status);
  465. }
  466. }
  467. list_for_each_entry(bus, &pbus->children, node)
  468. pci_scan_for_parity_error(pbm, bus);
  469. }