leon_pci_grpci2.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * leon_pci_grpci2.c: GRPCI2 Host PCI driver
  4. *
  5. * Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
  6. *
  7. */
  8. #include <linux/of_device.h>
  9. #include <linux/kernel.h>
  10. #include <linux/pci.h>
  11. #include <linux/slab.h>
  12. #include <linux/delay.h>
  13. #include <linux/export.h>
  14. #include <asm/io.h>
  15. #include <asm/leon.h>
  16. #include <asm/vaddrs.h>
  17. #include <asm/sections.h>
  18. #include <asm/leon_pci.h>
  19. #include "irq.h"
  20. struct grpci2_barcfg {
  21. unsigned long pciadr; /* PCI Space Address */
  22. unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */
  23. };
  24. /* Device Node Configuration options:
  25. * - barcfgs : Custom Configuration of Host's 6 target BARs
  26. * - irq_mask : Limit which PCI interrupts are enabled
  27. * - do_reset : Force PCI Reset on startup
  28. *
  29. * barcfgs
  30. * =======
  31. *
  32. * Optional custom Target BAR configuration (see struct grpci2_barcfg). All
  33. * addresses are physical. Array always contains 6 elements (len=2*4*6 bytes)
  34. *
  35. * -1 means not configured (let host driver do default setup).
  36. *
  37. * [i*2+0] = PCI Address of BAR[i] on target interface
  38. * [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
  39. *
  40. *
  41. * irq_mask
  42. * ========
  43. *
  44. * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
  45. * all are enabled. Use this when PCI interrupt pins are floating on PCB.
  46. * int, len=4.
  47. * bit0 = PCI INTA#
  48. * bit1 = PCI INTB#
  49. * bit2 = PCI INTC#
  50. * bit3 = PCI INTD#
  51. *
  52. *
  53. * reset
  54. * =====
  55. *
  56. * Force PCI reset on startup. int, len=4
  57. */
  58. /* Enable Debugging Configuration Space Access */
  59. #undef GRPCI2_DEBUG_CFGACCESS
  60. /*
  61. * GRPCI2 APB Register MAP
  62. */
  63. struct grpci2_regs {
  64. unsigned int ctrl; /* 0x00 Control */
  65. unsigned int sts_cap; /* 0x04 Status / Capabilities */
  66. int res1; /* 0x08 */
  67. unsigned int io_map; /* 0x0C I/O Map address */
  68. unsigned int dma_ctrl; /* 0x10 DMA */
  69. unsigned int dma_bdbase; /* 0x14 DMA */
  70. int res2[2]; /* 0x18 */
  71. unsigned int bars[6]; /* 0x20 read-only PCI BARs */
  72. int res3[2]; /* 0x38 */
  73. unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
  74. /* PCI Trace Buffer Registers (OPTIONAL) */
  75. unsigned int t_ctrl; /* 0x80 */
  76. unsigned int t_cnt; /* 0x84 */
  77. unsigned int t_adpat; /* 0x88 */
  78. unsigned int t_admask; /* 0x8C */
  79. unsigned int t_sigpat; /* 0x90 */
  80. unsigned int t_sigmask; /* 0x94 */
  81. unsigned int t_adstate; /* 0x98 */
  82. unsigned int t_sigstate; /* 0x9C */
  83. };
  84. #define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
  85. #define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
  86. #define CTRL_BUS_BIT 16
  87. #define CTRL_RESET (1<<31)
  88. #define CTRL_SI (1<<27)
  89. #define CTRL_PE (1<<26)
  90. #define CTRL_EI (1<<25)
  91. #define CTRL_ER (1<<24)
  92. #define CTRL_BUS (0xff<<CTRL_BUS_BIT)
  93. #define CTRL_HOSTINT 0xf
  94. #define STS_HOST_BIT 31
  95. #define STS_MST_BIT 30
  96. #define STS_TAR_BIT 29
  97. #define STS_DMA_BIT 28
  98. #define STS_DI_BIT 27
  99. #define STS_HI_BIT 26
  100. #define STS_IRQMODE_BIT 24
  101. #define STS_TRACE_BIT 23
  102. #define STS_CFGERRVALID_BIT 20
  103. #define STS_CFGERR_BIT 19
  104. #define STS_INTTYPE_BIT 12
  105. #define STS_INTSTS_BIT 8
  106. #define STS_FDEPTH_BIT 2
  107. #define STS_FNUM_BIT 0
  108. #define STS_HOST (1<<STS_HOST_BIT)
  109. #define STS_MST (1<<STS_MST_BIT)
  110. #define STS_TAR (1<<STS_TAR_BIT)
  111. #define STS_DMA (1<<STS_DMA_BIT)
  112. #define STS_DI (1<<STS_DI_BIT)
  113. #define STS_HI (1<<STS_HI_BIT)
  114. #define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
  115. #define STS_TRACE (1<<STS_TRACE_BIT)
  116. #define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
  117. #define STS_CFGERR (1<<STS_CFGERR_BIT)
  118. #define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
  119. #define STS_INTSTS (0xf<<STS_INTSTS_BIT)
  120. #define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
  121. #define STS_FNUM (0x3<<STS_FNUM_BIT)
  122. #define STS_ISYSERR (1<<17)
  123. #define STS_IDMA (1<<16)
  124. #define STS_IDMAERR (1<<15)
  125. #define STS_IMSTABRT (1<<14)
  126. #define STS_ITGTABRT (1<<13)
  127. #define STS_IPARERR (1<<12)
  128. #define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR)
  129. struct grpci2_bd_chan {
  130. unsigned int ctrl; /* 0x00 DMA Control */
  131. unsigned int nchan; /* 0x04 Next DMA Channel Address */
  132. unsigned int nbd; /* 0x08 Next Data Descriptor in chan */
  133. unsigned int res; /* 0x0C Reserved */
  134. };
  135. #define BD_CHAN_EN 0x80000000
  136. #define BD_CHAN_TYPE 0x00300000
  137. #define BD_CHAN_BDCNT 0x0000ffff
  138. #define BD_CHAN_EN_BIT 31
  139. #define BD_CHAN_TYPE_BIT 20
  140. #define BD_CHAN_BDCNT_BIT 0
  141. struct grpci2_bd_data {
  142. unsigned int ctrl; /* 0x00 DMA Data Control */
  143. unsigned int pci_adr; /* 0x04 PCI Start Address */
  144. unsigned int ahb_adr; /* 0x08 AHB Start address */
  145. unsigned int next; /* 0x0C Next Data Descriptor in chan */
  146. };
  147. #define BD_DATA_EN 0x80000000
  148. #define BD_DATA_IE 0x40000000
  149. #define BD_DATA_DR 0x20000000
  150. #define BD_DATA_TYPE 0x00300000
  151. #define BD_DATA_ER 0x00080000
  152. #define BD_DATA_LEN 0x0000ffff
  153. #define BD_DATA_EN_BIT 31
  154. #define BD_DATA_IE_BIT 30
  155. #define BD_DATA_DR_BIT 29
  156. #define BD_DATA_TYPE_BIT 20
  157. #define BD_DATA_ER_BIT 19
  158. #define BD_DATA_LEN_BIT 0
  159. /* GRPCI2 Capability */
  160. struct grpci2_cap_first {
  161. unsigned int ctrl;
  162. unsigned int pci2ahb_map[6];
  163. unsigned int ext2ahb_map;
  164. unsigned int io_map;
  165. unsigned int pcibar_size[6];
  166. };
  167. #define CAP9_CTRL_OFS 0
  168. #define CAP9_BAR_OFS 0x4
  169. #define CAP9_IOMAP_OFS 0x20
  170. #define CAP9_BARSIZE_OFS 0x24
  171. #define TGT 256
  172. struct grpci2_priv {
  173. struct leon_pci_info info; /* must be on top of this structure */
  174. struct grpci2_regs __iomem *regs;
  175. char irq;
  176. char irq_mode; /* IRQ Mode from CAPSTS REG */
  177. char bt_enabled;
  178. char do_reset;
  179. char irq_mask;
  180. u32 pciid; /* PCI ID of Host */
  181. unsigned char irq_map[4];
  182. /* Virtual IRQ numbers */
  183. unsigned int virq_err;
  184. unsigned int virq_dma;
  185. /* AHB PCI Windows */
  186. unsigned long pci_area; /* MEMORY */
  187. unsigned long pci_area_end;
  188. unsigned long pci_io; /* I/O */
  189. unsigned long pci_conf; /* CONFIGURATION */
  190. unsigned long pci_conf_end;
  191. unsigned long pci_io_va;
  192. struct grpci2_barcfg tgtbars[6];
  193. };
  194. static DEFINE_SPINLOCK(grpci2_dev_lock);
  195. static struct grpci2_priv *grpci2priv;
  196. static int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  197. {
  198. struct grpci2_priv *priv = dev->bus->sysdata;
  199. int irq_group;
  200. /* Use default IRQ decoding on PCI BUS0 according slot numbering */
  201. irq_group = slot & 0x3;
  202. pin = ((pin - 1) + irq_group) & 0x3;
  203. return priv->irq_map[pin];
  204. }
  205. static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
  206. unsigned int devfn, int where, u32 *val)
  207. {
  208. unsigned int *pci_conf;
  209. unsigned long flags;
  210. u32 tmp;
  211. if (where & 0x3)
  212. return -EINVAL;
  213. if (bus == 0) {
  214. devfn += (0x8 * 6); /* start at AD16=Device0 */
  215. } else if (bus == TGT) {
  216. bus = 0;
  217. devfn = 0; /* special case: bridge controller itself */
  218. }
  219. /* Select bus */
  220. spin_lock_irqsave(&grpci2_dev_lock, flags);
  221. REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
  222. (bus << 16));
  223. spin_unlock_irqrestore(&grpci2_dev_lock, flags);
  224. /* clear old status */
  225. REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
  226. pci_conf = (unsigned int *) (priv->pci_conf |
  227. (devfn << 8) | (where & 0xfc));
  228. tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
  229. /* Wait until GRPCI2 signals that CFG access is done, it should be
  230. * done instantaneously unless a DMA operation is ongoing...
  231. */
  232. while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
  233. ;
  234. if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) {
  235. *val = 0xffffffff;
  236. } else {
  237. /* Bus always little endian (unaffected by byte-swapping) */
  238. *val = swab32(tmp);
  239. }
  240. return 0;
  241. }
  242. static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus,
  243. unsigned int devfn, int where, u32 *val)
  244. {
  245. u32 v;
  246. int ret;
  247. if (where & 0x1)
  248. return -EINVAL;
  249. ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
  250. *val = 0xffff & (v >> (8 * (where & 0x3)));
  251. return ret;
  252. }
  253. static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus,
  254. unsigned int devfn, int where, u32 *val)
  255. {
  256. u32 v;
  257. int ret;
  258. ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
  259. *val = 0xff & (v >> (8 * (where & 3)));
  260. return ret;
  261. }
  262. static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
  263. unsigned int devfn, int where, u32 val)
  264. {
  265. unsigned int *pci_conf;
  266. unsigned long flags;
  267. if (where & 0x3)
  268. return -EINVAL;
  269. if (bus == 0) {
  270. devfn += (0x8 * 6); /* start at AD16=Device0 */
  271. } else if (bus == TGT) {
  272. bus = 0;
  273. devfn = 0; /* special case: bridge controller itself */
  274. }
  275. /* Select bus */
  276. spin_lock_irqsave(&grpci2_dev_lock, flags);
  277. REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
  278. (bus << 16));
  279. spin_unlock_irqrestore(&grpci2_dev_lock, flags);
  280. /* clear old status */
  281. REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
  282. pci_conf = (unsigned int *) (priv->pci_conf |
  283. (devfn << 8) | (where & 0xfc));
  284. LEON3_BYPASS_STORE_PA(pci_conf, swab32(val));
  285. /* Wait until GRPCI2 signals that CFG access is done, it should be
  286. * done instantaneously unless a DMA operation is ongoing...
  287. */
  288. while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
  289. ;
  290. return 0;
  291. }
  292. static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus,
  293. unsigned int devfn, int where, u32 val)
  294. {
  295. int ret;
  296. u32 v;
  297. if (where & 0x1)
  298. return -EINVAL;
  299. ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v);
  300. if (ret)
  301. return ret;
  302. v = (v & ~(0xffff << (8 * (where & 0x3)))) |
  303. ((0xffff & val) << (8 * (where & 0x3)));
  304. return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
  305. }
  306. static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus,
  307. unsigned int devfn, int where, u32 val)
  308. {
  309. int ret;
  310. u32 v;
  311. ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
  312. if (ret != 0)
  313. return ret;
  314. v = (v & ~(0xff << (8 * (where & 0x3)))) |
  315. ((0xff & val) << (8 * (where & 0x3)));
  316. return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
  317. }
  318. /* Read from Configuration Space. When entering here the PCI layer has taken
  319. * the pci_lock spinlock and IRQ is off.
  320. */
  321. static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
  322. int where, int size, u32 *val)
  323. {
  324. struct grpci2_priv *priv = grpci2priv;
  325. unsigned int busno = bus->number;
  326. int ret;
  327. if (PCI_SLOT(devfn) > 15 || busno > 255) {
  328. *val = ~0;
  329. return 0;
  330. }
  331. switch (size) {
  332. case 1:
  333. ret = grpci2_cfg_r8(priv, busno, devfn, where, val);
  334. break;
  335. case 2:
  336. ret = grpci2_cfg_r16(priv, busno, devfn, where, val);
  337. break;
  338. case 4:
  339. ret = grpci2_cfg_r32(priv, busno, devfn, where, val);
  340. break;
  341. default:
  342. ret = -EINVAL;
  343. break;
  344. }
  345. #ifdef GRPCI2_DEBUG_CFGACCESS
  346. printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x "
  347. "size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where,
  348. *val, size);
  349. #endif
  350. return ret;
  351. }
  352. /* Write to Configuration Space. When entering here the PCI layer has taken
  353. * the pci_lock spinlock and IRQ is off.
  354. */
  355. static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
  356. int where, int size, u32 val)
  357. {
  358. struct grpci2_priv *priv = grpci2priv;
  359. unsigned int busno = bus->number;
  360. if (PCI_SLOT(devfn) > 15 || busno > 255)
  361. return 0;
  362. #ifdef GRPCI2_DEBUG_CFGACCESS
  363. printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d "
  364. "val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn),
  365. where, size, val);
  366. #endif
  367. switch (size) {
  368. default:
  369. return -EINVAL;
  370. case 1:
  371. return grpci2_cfg_w8(priv, busno, devfn, where, val);
  372. case 2:
  373. return grpci2_cfg_w16(priv, busno, devfn, where, val);
  374. case 4:
  375. return grpci2_cfg_w32(priv, busno, devfn, where, val);
  376. }
  377. }
  378. static struct pci_ops grpci2_ops = {
  379. .read = grpci2_read_config,
  380. .write = grpci2_write_config,
  381. };
  382. /* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration
  383. * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
  384. * this is not needed and the standard IRQ controller can be used.
  385. */
  386. static void grpci2_mask_irq(struct irq_data *data)
  387. {
  388. unsigned long flags;
  389. unsigned int irqidx;
  390. struct grpci2_priv *priv = grpci2priv;
  391. irqidx = (unsigned int)data->chip_data - 1;
  392. if (irqidx > 3) /* only mask PCI interrupts here */
  393. return;
  394. spin_lock_irqsave(&grpci2_dev_lock, flags);
  395. REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));
  396. spin_unlock_irqrestore(&grpci2_dev_lock, flags);
  397. }
  398. static void grpci2_unmask_irq(struct irq_data *data)
  399. {
  400. unsigned long flags;
  401. unsigned int irqidx;
  402. struct grpci2_priv *priv = grpci2priv;
  403. irqidx = (unsigned int)data->chip_data - 1;
  404. if (irqidx > 3) /* only unmask PCI interrupts here */
  405. return;
  406. spin_lock_irqsave(&grpci2_dev_lock, flags);
  407. REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));
  408. spin_unlock_irqrestore(&grpci2_dev_lock, flags);
  409. }
  410. static unsigned int grpci2_startup_irq(struct irq_data *data)
  411. {
  412. grpci2_unmask_irq(data);
  413. return 0;
  414. }
  415. static void grpci2_shutdown_irq(struct irq_data *data)
  416. {
  417. grpci2_mask_irq(data);
  418. }
  419. static struct irq_chip grpci2_irq = {
  420. .name = "grpci2",
  421. .irq_startup = grpci2_startup_irq,
  422. .irq_shutdown = grpci2_shutdown_irq,
  423. .irq_mask = grpci2_mask_irq,
  424. .irq_unmask = grpci2_unmask_irq,
  425. };
  426. /* Handle one or multiple IRQs from the PCI core */
  427. static void grpci2_pci_flow_irq(struct irq_desc *desc)
  428. {
  429. struct grpci2_priv *priv = grpci2priv;
  430. int i, ack = 0;
  431. unsigned int ctrl, sts_cap, pci_ints;
  432. ctrl = REGLOAD(priv->regs->ctrl);
  433. sts_cap = REGLOAD(priv->regs->sts_cap);
  434. /* Error Interrupt? */
  435. if (sts_cap & STS_ERR_IRQ) {
  436. generic_handle_irq(priv->virq_err);
  437. ack = 1;
  438. }
  439. /* PCI Interrupt? */
  440. pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT;
  441. if (pci_ints) {
  442. /* Call respective PCI Interrupt handler */
  443. for (i = 0; i < 4; i++) {
  444. if (pci_ints & (1 << i))
  445. generic_handle_irq(priv->irq_map[i]);
  446. }
  447. ack = 1;
  448. }
  449. /*
  450. * Decode DMA Interrupt only when shared with Err and PCI INTX#, when
  451. * the DMA is a unique IRQ the DMA interrupts doesn't end up here, they
  452. * goes directly to DMA ISR.
  453. */
  454. if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) {
  455. generic_handle_irq(priv->virq_dma);
  456. ack = 1;
  457. }
  458. /*
  459. * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
  460. * Controller, this must be done after IRQ sources have been handled to
  461. * avoid double IRQ generation
  462. */
  463. if (ack)
  464. desc->irq_data.chip->irq_eoi(&desc->irq_data);
  465. }
  466. /* Create a virtual IRQ */
  467. static unsigned int grpci2_build_device_irq(unsigned int irq)
  468. {
  469. unsigned int virq = 0, pil;
  470. pil = 1 << 8;
  471. virq = irq_alloc(irq, pil);
  472. if (virq == 0)
  473. goto out;
  474. irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq,
  475. "pcilvl");
  476. irq_set_chip_data(virq, (void *)irq);
  477. out:
  478. return virq;
  479. }
  480. static void grpci2_hw_init(struct grpci2_priv *priv)
  481. {
  482. u32 ahbadr, pciadr, bar_sz, capptr, io_map, data;
  483. struct grpci2_regs __iomem *regs = priv->regs;
  484. int i;
  485. struct grpci2_barcfg *barcfg = priv->tgtbars;
  486. /* Reset any earlier setup */
  487. if (priv->do_reset) {
  488. printk(KERN_INFO "GRPCI2: Resetting PCI bus\n");
  489. REGSTORE(regs->ctrl, CTRL_RESET);
  490. ssleep(1); /* Wait for boards to settle */
  491. }
  492. REGSTORE(regs->ctrl, 0);
  493. REGSTORE(regs->sts_cap, ~0); /* Clear Status */
  494. REGSTORE(regs->dma_ctrl, 0);
  495. REGSTORE(regs->dma_bdbase, 0);
  496. /* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
  497. REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
  498. /* set 1:1 mapping between AHB -> PCI memory space, for all Masters
  499. * Each AHB master has it's own mapping registers. Max 16 AHB masters.
  500. */
  501. for (i = 0; i < 16; i++)
  502. REGSTORE(regs->ahbmst_map[i], priv->pci_area);
  503. /* Get the GRPCI2 Host PCI ID */
  504. grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid);
  505. /* Get address to first (always defined) capability structure */
  506. grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr);
  507. /* Enable/Disable Byte twisting */
  508. grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map);
  509. io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
  510. grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map);
  511. /* Setup the Host's PCI Target BARs for other peripherals to access,
  512. * and do DMA to the host's memory. The target BARs can be sized and
  513. * enabled individually.
  514. *
  515. * User may set custom target BARs, but default is:
  516. * The first BARs is used to map kernel low (DMA is part of normal
  517. * region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the
  518. * PCI bus, the other BARs are disabled. We assume that the first BAR
  519. * is always available.
  520. */
  521. for (i = 0; i < 6; i++) {
  522. if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) {
  523. /* Target BARs must have the proper alignment */
  524. ahbadr = barcfg[i].ahbadr;
  525. pciadr = barcfg[i].pciadr;
  526. bar_sz = ((pciadr - 1) & ~pciadr) + 1;
  527. } else {
  528. if (i == 0) {
  529. /* Map main memory */
  530. bar_sz = 0xf0000008; /* 256MB prefetchable */
  531. ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN(
  532. (unsigned long) &_end));
  533. pciadr = ahbadr;
  534. } else {
  535. bar_sz = 0;
  536. ahbadr = 0;
  537. pciadr = 0;
  538. }
  539. }
  540. grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4,
  541. bar_sz);
  542. grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
  543. grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
  544. printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
  545. i, pciadr, ahbadr);
  546. }
  547. /* set as bus master and enable pci memory responses */
  548. grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
  549. data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  550. grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
  551. /* Enable Error respone (CPU-TRAP) on illegal memory access. */
  552. REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);
  553. }
  554. static irqreturn_t grpci2_jump_interrupt(int irq, void *arg)
  555. {
  556. printk(KERN_ERR "GRPCI2: Jump IRQ happened\n");
  557. return IRQ_NONE;
  558. }
  559. /* Handle GRPCI2 Error Interrupt */
  560. static irqreturn_t grpci2_err_interrupt(int irq, void *arg)
  561. {
  562. struct grpci2_priv *priv = arg;
  563. struct grpci2_regs __iomem *regs = priv->regs;
  564. unsigned int status;
  565. status = REGLOAD(regs->sts_cap);
  566. if ((status & STS_ERR_IRQ) == 0)
  567. return IRQ_NONE;
  568. if (status & STS_IPARERR)
  569. printk(KERN_ERR "GRPCI2: Parity Error\n");
  570. if (status & STS_ITGTABRT)
  571. printk(KERN_ERR "GRPCI2: Target Abort\n");
  572. if (status & STS_IMSTABRT)
  573. printk(KERN_ERR "GRPCI2: Master Abort\n");
  574. if (status & STS_ISYSERR)
  575. printk(KERN_ERR "GRPCI2: System Error\n");
  576. /* Clear handled INT TYPE IRQs */
  577. REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);
  578. return IRQ_HANDLED;
  579. }
  580. static int grpci2_of_probe(struct platform_device *ofdev)
  581. {
  582. struct grpci2_regs __iomem *regs;
  583. struct grpci2_priv *priv;
  584. int err, i, len;
  585. const int *tmp;
  586. unsigned int capability;
  587. if (grpci2priv) {
  588. printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n");
  589. return -ENODEV;
  590. }
  591. if (ofdev->num_resources < 3) {
  592. printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n");
  593. return -EIO;
  594. }
  595. /* Find Device Address */
  596. regs = of_ioremap(&ofdev->resource[0], 0,
  597. resource_size(&ofdev->resource[0]),
  598. "grlib-grpci2 regs");
  599. if (regs == NULL) {
  600. printk(KERN_ERR "GRPCI2: ioremap failed\n");
  601. return -EIO;
  602. }
  603. /*
  604. * Check that we're in Host Slot and that we can act as a Host Bridge
  605. * and not only as target.
  606. */
  607. capability = REGLOAD(regs->sts_cap);
  608. if ((capability & STS_HOST) || !(capability & STS_MST)) {
  609. printk(KERN_INFO "GRPCI2: not in host system slot\n");
  610. err = -EIO;
  611. goto err1;
  612. }
  613. priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL);
  614. if (grpci2priv == NULL) {
  615. err = -ENOMEM;
  616. goto err1;
  617. }
  618. priv->regs = regs;
  619. priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */
  620. priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT;
  621. printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq);
  622. /* Byte twisting should be made configurable from kernel command line */
  623. priv->bt_enabled = 1;
  624. /* Let user do custom Target BAR assignment */
  625. tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len);
  626. if (tmp && (len == 2*4*6))
  627. memcpy(priv->tgtbars, tmp, 2*4*6);
  628. else
  629. memset(priv->tgtbars, -1, 2*4*6);
  630. /* Limit IRQ unmasking in irq_mode 2 and 3 */
  631. tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len);
  632. if (tmp && (len == 4))
  633. priv->do_reset = *tmp;
  634. else
  635. priv->irq_mask = 0xf;
  636. /* Optional PCI reset. Force PCI reset on startup */
  637. tmp = of_get_property(ofdev->dev.of_node, "reset", &len);
  638. if (tmp && (len == 4))
  639. priv->do_reset = *tmp;
  640. else
  641. priv->do_reset = 0;
  642. /* Find PCI Memory, I/O and Configuration Space Windows */
  643. priv->pci_area = ofdev->resource[1].start;
  644. priv->pci_area_end = ofdev->resource[1].end+1;
  645. priv->pci_io = ofdev->resource[2].start;
  646. priv->pci_conf = ofdev->resource[2].start + 0x10000;
  647. priv->pci_conf_end = priv->pci_conf + 0x10000;
  648. priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
  649. if (!priv->pci_io_va) {
  650. err = -EIO;
  651. goto err2;
  652. }
  653. printk(KERN_INFO
  654. "GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
  655. " I/O SPACE [0x%08lx - 0x%08lx]\n"
  656. " CONFIG SPACE [0x%08lx - 0x%08lx]\n",
  657. priv->pci_area, priv->pci_area_end-1,
  658. priv->pci_io, priv->pci_conf-1,
  659. priv->pci_conf, priv->pci_conf_end-1);
  660. /*
  661. * I/O Space resources in I/O Window mapped into Virtual Adr Space
  662. * We never use low 4KB because some devices seem have problems using
  663. * address 0.
  664. */
  665. memset(&priv->info.io_space, 0, sizeof(struct resource));
  666. priv->info.io_space.name = "GRPCI2 PCI I/O Space";
  667. priv->info.io_space.start = priv->pci_io_va + 0x1000;
  668. priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
  669. priv->info.io_space.flags = IORESOURCE_IO;
  670. /*
  671. * GRPCI2 has no prefetchable memory, map everything as
  672. * non-prefetchable memory
  673. */
  674. memset(&priv->info.mem_space, 0, sizeof(struct resource));
  675. priv->info.mem_space.name = "GRPCI2 PCI MEM Space";
  676. priv->info.mem_space.start = priv->pci_area;
  677. priv->info.mem_space.end = priv->pci_area_end - 1;
  678. priv->info.mem_space.flags = IORESOURCE_MEM;
  679. if (request_resource(&iomem_resource, &priv->info.mem_space) < 0)
  680. goto err3;
  681. if (request_resource(&ioport_resource, &priv->info.io_space) < 0)
  682. goto err4;
  683. /* setup maximum supported PCI buses */
  684. priv->info.busn.name = "GRPCI2 busn";
  685. priv->info.busn.start = 0;
  686. priv->info.busn.end = 255;
  687. grpci2_hw_init(priv);
  688. /*
  689. * Get PCI Interrupt to System IRQ mapping and setup IRQ handling
  690. * Error IRQ always on PCI INTA.
  691. */
  692. if (priv->irq_mode < 2) {
  693. /* All PCI interrupts are shared using the same system IRQ */
  694. leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq,
  695. "pcilvl", 0);
  696. priv->irq_map[0] = grpci2_build_device_irq(1);
  697. priv->irq_map[1] = grpci2_build_device_irq(2);
  698. priv->irq_map[2] = grpci2_build_device_irq(3);
  699. priv->irq_map[3] = grpci2_build_device_irq(4);
  700. priv->virq_err = grpci2_build_device_irq(5);
  701. if (priv->irq_mode & 1)
  702. priv->virq_dma = ofdev->archdata.irqs[1];
  703. else
  704. priv->virq_dma = grpci2_build_device_irq(6);
  705. /* Enable IRQs on LEON IRQ controller */
  706. err = request_irq(priv->irq, grpci2_jump_interrupt, 0,
  707. "GRPCI2_JUMP", priv);
  708. if (err)
  709. printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n");
  710. } else {
  711. /* All PCI interrupts have an unique IRQ interrupt */
  712. for (i = 0; i < 4; i++) {
  713. /* Make LEON IRQ layer handle level IRQ by acking */
  714. leon_update_virq_handling(ofdev->archdata.irqs[i],
  715. handle_fasteoi_irq, "pcilvl",
  716. 1);
  717. priv->irq_map[i] = ofdev->archdata.irqs[i];
  718. }
  719. priv->virq_err = priv->irq_map[0];
  720. if (priv->irq_mode & 1)
  721. priv->virq_dma = ofdev->archdata.irqs[4];
  722. else
  723. priv->virq_dma = priv->irq_map[0];
  724. /* Unmask all PCI interrupts, request_irq will not do that */
  725. REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));
  726. }
  727. /* Setup IRQ handler for non-configuration space access errors */
  728. err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED,
  729. "GRPCI2_ERR", priv);
  730. if (err) {
  731. printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err);
  732. goto err5;
  733. }
  734. /*
  735. * Enable Error Interrupts. PCI interrupts are unmasked once request_irq
  736. * is called by the PCI Device drivers
  737. */
  738. REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);
  739. /* Init common layer and scan buses */
  740. priv->info.ops = &grpci2_ops;
  741. priv->info.map_irq = grpci2_map_irq;
  742. leon_pci_init(ofdev, &priv->info);
  743. return 0;
  744. err5:
  745. release_resource(&priv->info.io_space);
  746. err4:
  747. release_resource(&priv->info.mem_space);
  748. err3:
  749. err = -ENOMEM;
  750. iounmap((void __iomem *)priv->pci_io_va);
  751. err2:
  752. kfree(priv);
  753. err1:
  754. of_iounmap(&ofdev->resource[0], regs,
  755. resource_size(&ofdev->resource[0]));
  756. return err;
  757. }
  758. static const struct of_device_id grpci2_of_match[] __initconst = {
  759. {
  760. .name = "GAISLER_GRPCI2",
  761. },
  762. {
  763. .name = "01_07c",
  764. },
  765. {},
  766. };
  767. static struct platform_driver grpci2_of_driver = {
  768. .driver = {
  769. .name = "grpci2",
  770. .of_match_table = grpci2_of_match,
  771. },
  772. .probe = grpci2_of_probe,
  773. };
  774. static int __init grpci2_init(void)
  775. {
  776. return platform_driver_register(&grpci2_of_driver);
  777. }
  778. subsys_initcall(grpci2_init);