irq_64.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* irq.c: UltraSparc IRQ handling/init/registry.
  3. *
  4. * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
  5. * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
  6. * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
  7. */
  8. #include <linux/sched.h>
  9. #include <linux/linkage.h>
  10. #include <linux/ptrace.h>
  11. #include <linux/errno.h>
  12. #include <linux/kernel_stat.h>
  13. #include <linux/signal.h>
  14. #include <linux/mm.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/slab.h>
  17. #include <linux/random.h>
  18. #include <linux/init.h>
  19. #include <linux/delay.h>
  20. #include <linux/proc_fs.h>
  21. #include <linux/seq_file.h>
  22. #include <linux/ftrace.h>
  23. #include <linux/irq.h>
  24. #include <asm/ptrace.h>
  25. #include <asm/processor.h>
  26. #include <linux/atomic.h>
  27. #include <asm/irq.h>
  28. #include <asm/io.h>
  29. #include <asm/iommu.h>
  30. #include <asm/upa.h>
  31. #include <asm/oplib.h>
  32. #include <asm/prom.h>
  33. #include <asm/timer.h>
  34. #include <asm/smp.h>
  35. #include <asm/starfire.h>
  36. #include <linux/uaccess.h>
  37. #include <asm/cache.h>
  38. #include <asm/cpudata.h>
  39. #include <asm/auxio.h>
  40. #include <asm/head.h>
  41. #include <asm/hypervisor.h>
  42. #include <asm/cacheflush.h>
  43. #include "entry.h"
  44. #include "cpumap.h"
  45. #include "kstack.h"
  46. struct ino_bucket *ivector_table;
  47. unsigned long ivector_table_pa;
  48. /* On several sun4u processors, it is illegal to mix bypass and
  49. * non-bypass accesses. Therefore we access all INO buckets
  50. * using bypass accesses only.
  51. */
  52. static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
  53. {
  54. unsigned long ret;
  55. __asm__ __volatile__("ldxa [%1] %2, %0"
  56. : "=&r" (ret)
  57. : "r" (bucket_pa +
  58. offsetof(struct ino_bucket,
  59. __irq_chain_pa)),
  60. "i" (ASI_PHYS_USE_EC));
  61. return ret;
  62. }
  63. static void bucket_clear_chain_pa(unsigned long bucket_pa)
  64. {
  65. __asm__ __volatile__("stxa %%g0, [%0] %1"
  66. : /* no outputs */
  67. : "r" (bucket_pa +
  68. offsetof(struct ino_bucket,
  69. __irq_chain_pa)),
  70. "i" (ASI_PHYS_USE_EC));
  71. }
  72. static unsigned int bucket_get_irq(unsigned long bucket_pa)
  73. {
  74. unsigned int ret;
  75. __asm__ __volatile__("lduwa [%1] %2, %0"
  76. : "=&r" (ret)
  77. : "r" (bucket_pa +
  78. offsetof(struct ino_bucket,
  79. __irq)),
  80. "i" (ASI_PHYS_USE_EC));
  81. return ret;
  82. }
  83. static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq)
  84. {
  85. __asm__ __volatile__("stwa %0, [%1] %2"
  86. : /* no outputs */
  87. : "r" (irq),
  88. "r" (bucket_pa +
  89. offsetof(struct ino_bucket,
  90. __irq)),
  91. "i" (ASI_PHYS_USE_EC));
  92. }
  93. #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa)
  94. static unsigned long hvirq_major __initdata;
  95. static int __init early_hvirq_major(char *p)
  96. {
  97. int rc = kstrtoul(p, 10, &hvirq_major);
  98. return rc;
  99. }
  100. early_param("hvirq", early_hvirq_major);
  101. static int hv_irq_version;
  102. /* Major version 2.0 of HV_GRP_INTR added support for the VIRQ cookie
  103. * based interfaces, but:
  104. *
  105. * 1) Several OSs, Solaris and Linux included, use them even when only
  106. * negotiating version 1.0 (or failing to negotiate at all). So the
  107. * hypervisor has a workaround that provides the VIRQ interfaces even
  108. * when only verion 1.0 of the API is in use.
  109. *
  110. * 2) Second, and more importantly, with major version 2.0 these VIRQ
  111. * interfaces only were actually hooked up for LDC interrupts, even
  112. * though the Hypervisor specification clearly stated:
  113. *
  114. * The new interrupt API functions will be available to a guest
  115. * when it negotiates version 2.0 in the interrupt API group 0x2. When
  116. * a guest negotiates version 2.0, all interrupt sources will only
  117. * support using the cookie interface, and any attempt to use the
  118. * version 1.0 interrupt APIs numbered 0xa0 to 0xa6 will result in the
  119. * ENOTSUPPORTED error being returned.
  120. *
  121. * with an emphasis on "all interrupt sources".
  122. *
  123. * To correct this, major version 3.0 was created which does actually
  124. * support VIRQs for all interrupt sources (not just LDC devices). So
  125. * if we want to move completely over the cookie based VIRQs we must
  126. * negotiate major version 3.0 or later of HV_GRP_INTR.
  127. */
  128. static bool sun4v_cookie_only_virqs(void)
  129. {
  130. if (hv_irq_version >= 3)
  131. return true;
  132. return false;
  133. }
  134. static void __init irq_init_hv(void)
  135. {
  136. unsigned long hv_error, major, minor = 0;
  137. if (tlb_type != hypervisor)
  138. return;
  139. if (hvirq_major)
  140. major = hvirq_major;
  141. else
  142. major = 3;
  143. hv_error = sun4v_hvapi_register(HV_GRP_INTR, major, &minor);
  144. if (!hv_error)
  145. hv_irq_version = major;
  146. else
  147. hv_irq_version = 1;
  148. pr_info("SUN4V: Using IRQ API major %d, cookie only virqs %s\n",
  149. hv_irq_version,
  150. sun4v_cookie_only_virqs() ? "enabled" : "disabled");
  151. }
  152. /* This function is for the timer interrupt.*/
  153. int __init arch_probe_nr_irqs(void)
  154. {
  155. return 1;
  156. }
  157. #define DEFAULT_NUM_IVECS (0xfffU)
  158. static unsigned int nr_ivec = DEFAULT_NUM_IVECS;
  159. #define NUM_IVECS (nr_ivec)
  160. static unsigned int __init size_nr_ivec(void)
  161. {
  162. if (tlb_type == hypervisor) {
  163. switch (sun4v_chip_type) {
  164. /* Athena's devhandle|devino is large.*/
  165. case SUN4V_CHIP_SPARC64X:
  166. nr_ivec = 0xffff;
  167. break;
  168. }
  169. }
  170. return nr_ivec;
  171. }
  172. struct irq_handler_data {
  173. union {
  174. struct {
  175. unsigned int dev_handle;
  176. unsigned int dev_ino;
  177. };
  178. unsigned long sysino;
  179. };
  180. struct ino_bucket bucket;
  181. unsigned long iclr;
  182. unsigned long imap;
  183. };
  184. static inline unsigned int irq_data_to_handle(struct irq_data *data)
  185. {
  186. struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data);
  187. return ihd->dev_handle;
  188. }
  189. static inline unsigned int irq_data_to_ino(struct irq_data *data)
  190. {
  191. struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data);
  192. return ihd->dev_ino;
  193. }
  194. static inline unsigned long irq_data_to_sysino(struct irq_data *data)
  195. {
  196. struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data);
  197. return ihd->sysino;
  198. }
  199. void irq_free(unsigned int irq)
  200. {
  201. void *data = irq_get_handler_data(irq);
  202. kfree(data);
  203. irq_set_handler_data(irq, NULL);
  204. irq_free_descs(irq, 1);
  205. }
  206. unsigned int irq_alloc(unsigned int dev_handle, unsigned int dev_ino)
  207. {
  208. int irq;
  209. irq = __irq_alloc_descs(-1, 1, 1, numa_node_id(), NULL, NULL);
  210. if (irq <= 0)
  211. goto out;
  212. return irq;
  213. out:
  214. return 0;
  215. }
  216. static unsigned int cookie_exists(u32 devhandle, unsigned int devino)
  217. {
  218. unsigned long hv_err, cookie;
  219. struct ino_bucket *bucket;
  220. unsigned int irq = 0U;
  221. hv_err = sun4v_vintr_get_cookie(devhandle, devino, &cookie);
  222. if (hv_err) {
  223. pr_err("HV get cookie failed hv_err = %ld\n", hv_err);
  224. goto out;
  225. }
  226. if (cookie & ((1UL << 63UL))) {
  227. cookie = ~cookie;
  228. bucket = (struct ino_bucket *) __va(cookie);
  229. irq = bucket->__irq;
  230. }
  231. out:
  232. return irq;
  233. }
  234. static unsigned int sysino_exists(u32 devhandle, unsigned int devino)
  235. {
  236. unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
  237. struct ino_bucket *bucket;
  238. unsigned int irq;
  239. bucket = &ivector_table[sysino];
  240. irq = bucket_get_irq(__pa(bucket));
  241. return irq;
  242. }
  243. void ack_bad_irq(unsigned int irq)
  244. {
  245. pr_crit("BAD IRQ ack %d\n", irq);
  246. }
  247. void irq_install_pre_handler(int irq,
  248. void (*func)(unsigned int, void *, void *),
  249. void *arg1, void *arg2)
  250. {
  251. pr_warn("IRQ pre handler NOT supported.\n");
  252. }
  253. /*
  254. * /proc/interrupts printing:
  255. */
  256. int arch_show_interrupts(struct seq_file *p, int prec)
  257. {
  258. int j;
  259. seq_printf(p, "NMI: ");
  260. for_each_online_cpu(j)
  261. seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
  262. seq_printf(p, " Non-maskable interrupts\n");
  263. return 0;
  264. }
  265. static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
  266. {
  267. unsigned int tid;
  268. if (this_is_starfire) {
  269. tid = starfire_translate(imap, cpuid);
  270. tid <<= IMAP_TID_SHIFT;
  271. tid &= IMAP_TID_UPA;
  272. } else {
  273. if (tlb_type == cheetah || tlb_type == cheetah_plus) {
  274. unsigned long ver;
  275. __asm__ ("rdpr %%ver, %0" : "=r" (ver));
  276. if ((ver >> 32UL) == __JALAPENO_ID ||
  277. (ver >> 32UL) == __SERRANO_ID) {
  278. tid = cpuid << IMAP_TID_SHIFT;
  279. tid &= IMAP_TID_JBUS;
  280. } else {
  281. unsigned int a = cpuid & 0x1f;
  282. unsigned int n = (cpuid >> 5) & 0x1f;
  283. tid = ((a << IMAP_AID_SHIFT) |
  284. (n << IMAP_NID_SHIFT));
  285. tid &= (IMAP_AID_SAFARI |
  286. IMAP_NID_SAFARI);
  287. }
  288. } else {
  289. tid = cpuid << IMAP_TID_SHIFT;
  290. tid &= IMAP_TID_UPA;
  291. }
  292. }
  293. return tid;
  294. }
  295. #ifdef CONFIG_SMP
  296. static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity)
  297. {
  298. cpumask_t mask;
  299. int cpuid;
  300. cpumask_copy(&mask, affinity);
  301. if (cpumask_equal(&mask, cpu_online_mask)) {
  302. cpuid = map_to_cpu(irq);
  303. } else {
  304. cpumask_t tmp;
  305. cpumask_and(&tmp, cpu_online_mask, &mask);
  306. cpuid = cpumask_empty(&tmp) ? map_to_cpu(irq) : cpumask_first(&tmp);
  307. }
  308. return cpuid;
  309. }
  310. #else
  311. #define irq_choose_cpu(irq, affinity) \
  312. real_hard_smp_processor_id()
  313. #endif
  314. static void sun4u_irq_enable(struct irq_data *data)
  315. {
  316. struct irq_handler_data *handler_data;
  317. handler_data = irq_data_get_irq_handler_data(data);
  318. if (likely(handler_data)) {
  319. unsigned long cpuid, imap, val;
  320. unsigned int tid;
  321. cpuid = irq_choose_cpu(data->irq,
  322. irq_data_get_affinity_mask(data));
  323. imap = handler_data->imap;
  324. tid = sun4u_compute_tid(imap, cpuid);
  325. val = upa_readq(imap);
  326. val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
  327. IMAP_AID_SAFARI | IMAP_NID_SAFARI);
  328. val |= tid | IMAP_VALID;
  329. upa_writeq(val, imap);
  330. upa_writeq(ICLR_IDLE, handler_data->iclr);
  331. }
  332. }
  333. static int sun4u_set_affinity(struct irq_data *data,
  334. const struct cpumask *mask, bool force)
  335. {
  336. struct irq_handler_data *handler_data;
  337. handler_data = irq_data_get_irq_handler_data(data);
  338. if (likely(handler_data)) {
  339. unsigned long cpuid, imap, val;
  340. unsigned int tid;
  341. cpuid = irq_choose_cpu(data->irq, mask);
  342. imap = handler_data->imap;
  343. tid = sun4u_compute_tid(imap, cpuid);
  344. val = upa_readq(imap);
  345. val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
  346. IMAP_AID_SAFARI | IMAP_NID_SAFARI);
  347. val |= tid | IMAP_VALID;
  348. upa_writeq(val, imap);
  349. upa_writeq(ICLR_IDLE, handler_data->iclr);
  350. }
  351. return 0;
  352. }
  353. /* Don't do anything. The desc->status check for IRQ_DISABLED in
  354. * handler_irq() will skip the handler call and that will leave the
  355. * interrupt in the sent state. The next ->enable() call will hit the
  356. * ICLR register to reset the state machine.
  357. *
  358. * This scheme is necessary, instead of clearing the Valid bit in the
  359. * IMAP register, to handle the case of IMAP registers being shared by
  360. * multiple INOs (and thus ICLR registers). Since we use a different
  361. * virtual IRQ for each shared IMAP instance, the generic code thinks
  362. * there is only one user so it prematurely calls ->disable() on
  363. * free_irq().
  364. *
  365. * We have to provide an explicit ->disable() method instead of using
  366. * NULL to get the default. The reason is that if the generic code
  367. * sees that, it also hooks up a default ->shutdown method which
  368. * invokes ->mask() which we do not want. See irq_chip_set_defaults().
  369. */
  370. static void sun4u_irq_disable(struct irq_data *data)
  371. {
  372. }
  373. static void sun4u_irq_eoi(struct irq_data *data)
  374. {
  375. struct irq_handler_data *handler_data;
  376. handler_data = irq_data_get_irq_handler_data(data);
  377. if (likely(handler_data))
  378. upa_writeq(ICLR_IDLE, handler_data->iclr);
  379. }
  380. static void sun4v_irq_enable(struct irq_data *data)
  381. {
  382. unsigned long cpuid = irq_choose_cpu(data->irq,
  383. irq_data_get_affinity_mask(data));
  384. unsigned int ino = irq_data_to_sysino(data);
  385. int err;
  386. err = sun4v_intr_settarget(ino, cpuid);
  387. if (err != HV_EOK)
  388. printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
  389. "err(%d)\n", ino, cpuid, err);
  390. err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
  391. if (err != HV_EOK)
  392. printk(KERN_ERR "sun4v_intr_setstate(%x): "
  393. "err(%d)\n", ino, err);
  394. err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
  395. if (err != HV_EOK)
  396. printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
  397. ino, err);
  398. }
  399. static int sun4v_set_affinity(struct irq_data *data,
  400. const struct cpumask *mask, bool force)
  401. {
  402. unsigned long cpuid = irq_choose_cpu(data->irq, mask);
  403. unsigned int ino = irq_data_to_sysino(data);
  404. int err;
  405. err = sun4v_intr_settarget(ino, cpuid);
  406. if (err != HV_EOK)
  407. printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
  408. "err(%d)\n", ino, cpuid, err);
  409. return 0;
  410. }
  411. static void sun4v_irq_disable(struct irq_data *data)
  412. {
  413. unsigned int ino = irq_data_to_sysino(data);
  414. int err;
  415. err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
  416. if (err != HV_EOK)
  417. printk(KERN_ERR "sun4v_intr_setenabled(%x): "
  418. "err(%d)\n", ino, err);
  419. }
  420. static void sun4v_irq_eoi(struct irq_data *data)
  421. {
  422. unsigned int ino = irq_data_to_sysino(data);
  423. int err;
  424. err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
  425. if (err != HV_EOK)
  426. printk(KERN_ERR "sun4v_intr_setstate(%x): "
  427. "err(%d)\n", ino, err);
  428. }
  429. static void sun4v_virq_enable(struct irq_data *data)
  430. {
  431. unsigned long dev_handle = irq_data_to_handle(data);
  432. unsigned long dev_ino = irq_data_to_ino(data);
  433. unsigned long cpuid;
  434. int err;
  435. cpuid = irq_choose_cpu(data->irq, irq_data_get_affinity_mask(data));
  436. err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
  437. if (err != HV_EOK)
  438. printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
  439. "err(%d)\n",
  440. dev_handle, dev_ino, cpuid, err);
  441. err = sun4v_vintr_set_state(dev_handle, dev_ino,
  442. HV_INTR_STATE_IDLE);
  443. if (err != HV_EOK)
  444. printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
  445. "HV_INTR_STATE_IDLE): err(%d)\n",
  446. dev_handle, dev_ino, err);
  447. err = sun4v_vintr_set_valid(dev_handle, dev_ino,
  448. HV_INTR_ENABLED);
  449. if (err != HV_EOK)
  450. printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
  451. "HV_INTR_ENABLED): err(%d)\n",
  452. dev_handle, dev_ino, err);
  453. }
  454. static int sun4v_virt_set_affinity(struct irq_data *data,
  455. const struct cpumask *mask, bool force)
  456. {
  457. unsigned long dev_handle = irq_data_to_handle(data);
  458. unsigned long dev_ino = irq_data_to_ino(data);
  459. unsigned long cpuid;
  460. int err;
  461. cpuid = irq_choose_cpu(data->irq, mask);
  462. err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
  463. if (err != HV_EOK)
  464. printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
  465. "err(%d)\n",
  466. dev_handle, dev_ino, cpuid, err);
  467. return 0;
  468. }
  469. static void sun4v_virq_disable(struct irq_data *data)
  470. {
  471. unsigned long dev_handle = irq_data_to_handle(data);
  472. unsigned long dev_ino = irq_data_to_ino(data);
  473. int err;
  474. err = sun4v_vintr_set_valid(dev_handle, dev_ino,
  475. HV_INTR_DISABLED);
  476. if (err != HV_EOK)
  477. printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
  478. "HV_INTR_DISABLED): err(%d)\n",
  479. dev_handle, dev_ino, err);
  480. }
  481. static void sun4v_virq_eoi(struct irq_data *data)
  482. {
  483. unsigned long dev_handle = irq_data_to_handle(data);
  484. unsigned long dev_ino = irq_data_to_ino(data);
  485. int err;
  486. err = sun4v_vintr_set_state(dev_handle, dev_ino,
  487. HV_INTR_STATE_IDLE);
  488. if (err != HV_EOK)
  489. printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
  490. "HV_INTR_STATE_IDLE): err(%d)\n",
  491. dev_handle, dev_ino, err);
  492. }
  493. static struct irq_chip sun4u_irq = {
  494. .name = "sun4u",
  495. .irq_enable = sun4u_irq_enable,
  496. .irq_disable = sun4u_irq_disable,
  497. .irq_eoi = sun4u_irq_eoi,
  498. .irq_set_affinity = sun4u_set_affinity,
  499. .flags = IRQCHIP_EOI_IF_HANDLED,
  500. };
  501. static struct irq_chip sun4v_irq = {
  502. .name = "sun4v",
  503. .irq_enable = sun4v_irq_enable,
  504. .irq_disable = sun4v_irq_disable,
  505. .irq_eoi = sun4v_irq_eoi,
  506. .irq_set_affinity = sun4v_set_affinity,
  507. .flags = IRQCHIP_EOI_IF_HANDLED,
  508. };
  509. static struct irq_chip sun4v_virq = {
  510. .name = "vsun4v",
  511. .irq_enable = sun4v_virq_enable,
  512. .irq_disable = sun4v_virq_disable,
  513. .irq_eoi = sun4v_virq_eoi,
  514. .irq_set_affinity = sun4v_virt_set_affinity,
  515. .flags = IRQCHIP_EOI_IF_HANDLED,
  516. };
  517. unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
  518. {
  519. struct irq_handler_data *handler_data;
  520. struct ino_bucket *bucket;
  521. unsigned int irq;
  522. int ino;
  523. BUG_ON(tlb_type == hypervisor);
  524. ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
  525. bucket = &ivector_table[ino];
  526. irq = bucket_get_irq(__pa(bucket));
  527. if (!irq) {
  528. irq = irq_alloc(0, ino);
  529. bucket_set_irq(__pa(bucket), irq);
  530. irq_set_chip_and_handler_name(irq, &sun4u_irq,
  531. handle_fasteoi_irq, "IVEC");
  532. }
  533. handler_data = irq_get_handler_data(irq);
  534. if (unlikely(handler_data))
  535. goto out;
  536. handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
  537. if (unlikely(!handler_data)) {
  538. prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
  539. prom_halt();
  540. }
  541. irq_set_handler_data(irq, handler_data);
  542. handler_data->imap = imap;
  543. handler_data->iclr = iclr;
  544. out:
  545. return irq;
  546. }
  547. static unsigned int sun4v_build_common(u32 devhandle, unsigned int devino,
  548. void (*handler_data_init)(struct irq_handler_data *data,
  549. u32 devhandle, unsigned int devino),
  550. struct irq_chip *chip)
  551. {
  552. struct irq_handler_data *data;
  553. unsigned int irq;
  554. irq = irq_alloc(devhandle, devino);
  555. if (!irq)
  556. goto out;
  557. data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
  558. if (unlikely(!data)) {
  559. pr_err("IRQ handler data allocation failed.\n");
  560. irq_free(irq);
  561. irq = 0;
  562. goto out;
  563. }
  564. irq_set_handler_data(irq, data);
  565. handler_data_init(data, devhandle, devino);
  566. irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq, "IVEC");
  567. data->imap = ~0UL;
  568. data->iclr = ~0UL;
  569. out:
  570. return irq;
  571. }
  572. static unsigned long cookie_assign(unsigned int irq, u32 devhandle,
  573. unsigned int devino)
  574. {
  575. struct irq_handler_data *ihd = irq_get_handler_data(irq);
  576. unsigned long hv_error, cookie;
  577. /* handler_irq needs to find the irq. cookie is seen signed in
  578. * sun4v_dev_mondo and treated as a non ivector_table delivery.
  579. */
  580. ihd->bucket.__irq = irq;
  581. cookie = ~__pa(&ihd->bucket);
  582. hv_error = sun4v_vintr_set_cookie(devhandle, devino, cookie);
  583. if (hv_error)
  584. pr_err("HV vintr set cookie failed = %ld\n", hv_error);
  585. return hv_error;
  586. }
  587. static void cookie_handler_data(struct irq_handler_data *data,
  588. u32 devhandle, unsigned int devino)
  589. {
  590. data->dev_handle = devhandle;
  591. data->dev_ino = devino;
  592. }
  593. static unsigned int cookie_build_irq(u32 devhandle, unsigned int devino,
  594. struct irq_chip *chip)
  595. {
  596. unsigned long hv_error;
  597. unsigned int irq;
  598. irq = sun4v_build_common(devhandle, devino, cookie_handler_data, chip);
  599. hv_error = cookie_assign(irq, devhandle, devino);
  600. if (hv_error) {
  601. irq_free(irq);
  602. irq = 0;
  603. }
  604. return irq;
  605. }
  606. static unsigned int sun4v_build_cookie(u32 devhandle, unsigned int devino)
  607. {
  608. unsigned int irq;
  609. irq = cookie_exists(devhandle, devino);
  610. if (irq)
  611. goto out;
  612. irq = cookie_build_irq(devhandle, devino, &sun4v_virq);
  613. out:
  614. return irq;
  615. }
  616. static void sysino_set_bucket(unsigned int irq)
  617. {
  618. struct irq_handler_data *ihd = irq_get_handler_data(irq);
  619. struct ino_bucket *bucket;
  620. unsigned long sysino;
  621. sysino = sun4v_devino_to_sysino(ihd->dev_handle, ihd->dev_ino);
  622. BUG_ON(sysino >= nr_ivec);
  623. bucket = &ivector_table[sysino];
  624. bucket_set_irq(__pa(bucket), irq);
  625. }
  626. static void sysino_handler_data(struct irq_handler_data *data,
  627. u32 devhandle, unsigned int devino)
  628. {
  629. unsigned long sysino;
  630. sysino = sun4v_devino_to_sysino(devhandle, devino);
  631. data->sysino = sysino;
  632. }
  633. static unsigned int sysino_build_irq(u32 devhandle, unsigned int devino,
  634. struct irq_chip *chip)
  635. {
  636. unsigned int irq;
  637. irq = sun4v_build_common(devhandle, devino, sysino_handler_data, chip);
  638. if (!irq)
  639. goto out;
  640. sysino_set_bucket(irq);
  641. out:
  642. return irq;
  643. }
  644. static int sun4v_build_sysino(u32 devhandle, unsigned int devino)
  645. {
  646. int irq;
  647. irq = sysino_exists(devhandle, devino);
  648. if (irq)
  649. goto out;
  650. irq = sysino_build_irq(devhandle, devino, &sun4v_irq);
  651. out:
  652. return irq;
  653. }
  654. unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
  655. {
  656. unsigned int irq;
  657. if (sun4v_cookie_only_virqs())
  658. irq = sun4v_build_cookie(devhandle, devino);
  659. else
  660. irq = sun4v_build_sysino(devhandle, devino);
  661. return irq;
  662. }
  663. unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
  664. {
  665. int irq;
  666. irq = cookie_build_irq(devhandle, devino, &sun4v_virq);
  667. if (!irq)
  668. goto out;
  669. /* This is borrowed from the original function.
  670. */
  671. irq_set_status_flags(irq, IRQ_NOAUTOEN);
  672. out:
  673. return irq;
  674. }
  675. void *hardirq_stack[NR_CPUS];
  676. void *softirq_stack[NR_CPUS];
  677. void __irq_entry handler_irq(int pil, struct pt_regs *regs)
  678. {
  679. unsigned long pstate, bucket_pa;
  680. struct pt_regs *old_regs;
  681. void *orig_sp;
  682. clear_softint(1 << pil);
  683. old_regs = set_irq_regs(regs);
  684. irq_enter();
  685. /* Grab an atomic snapshot of the pending IVECs. */
  686. __asm__ __volatile__("rdpr %%pstate, %0\n\t"
  687. "wrpr %0, %3, %%pstate\n\t"
  688. "ldx [%2], %1\n\t"
  689. "stx %%g0, [%2]\n\t"
  690. "wrpr %0, 0x0, %%pstate\n\t"
  691. : "=&r" (pstate), "=&r" (bucket_pa)
  692. : "r" (irq_work_pa(smp_processor_id())),
  693. "i" (PSTATE_IE)
  694. : "memory");
  695. orig_sp = set_hardirq_stack();
  696. while (bucket_pa) {
  697. unsigned long next_pa;
  698. unsigned int irq;
  699. next_pa = bucket_get_chain_pa(bucket_pa);
  700. irq = bucket_get_irq(bucket_pa);
  701. bucket_clear_chain_pa(bucket_pa);
  702. generic_handle_irq(irq);
  703. bucket_pa = next_pa;
  704. }
  705. restore_hardirq_stack(orig_sp);
  706. irq_exit();
  707. set_irq_regs(old_regs);
  708. }
  709. void do_softirq_own_stack(void)
  710. {
  711. void *orig_sp, *sp = softirq_stack[smp_processor_id()];
  712. sp += THREAD_SIZE - 192 - STACK_BIAS;
  713. __asm__ __volatile__("mov %%sp, %0\n\t"
  714. "mov %1, %%sp"
  715. : "=&r" (orig_sp)
  716. : "r" (sp));
  717. __do_softirq();
  718. __asm__ __volatile__("mov %0, %%sp"
  719. : : "r" (orig_sp));
  720. }
  721. #ifdef CONFIG_HOTPLUG_CPU
  722. void fixup_irqs(void)
  723. {
  724. unsigned int irq;
  725. for (irq = 0; irq < NR_IRQS; irq++) {
  726. struct irq_desc *desc = irq_to_desc(irq);
  727. struct irq_data *data;
  728. unsigned long flags;
  729. if (!desc)
  730. continue;
  731. data = irq_desc_get_irq_data(desc);
  732. raw_spin_lock_irqsave(&desc->lock, flags);
  733. if (desc->action && !irqd_is_per_cpu(data)) {
  734. if (data->chip->irq_set_affinity)
  735. data->chip->irq_set_affinity(data,
  736. irq_data_get_affinity_mask(data),
  737. false);
  738. }
  739. raw_spin_unlock_irqrestore(&desc->lock, flags);
  740. }
  741. tick_ops->disable_irq();
  742. }
  743. #endif
  744. struct sun5_timer {
  745. u64 count0;
  746. u64 limit0;
  747. u64 count1;
  748. u64 limit1;
  749. };
  750. static struct sun5_timer *prom_timers;
  751. static u64 prom_limit0, prom_limit1;
  752. static void map_prom_timers(void)
  753. {
  754. struct device_node *dp;
  755. const unsigned int *addr;
  756. /* PROM timer node hangs out in the top level of device siblings... */
  757. dp = of_find_node_by_path("/");
  758. dp = dp->child;
  759. while (dp) {
  760. if (of_node_name_eq(dp, "counter-timer"))
  761. break;
  762. dp = dp->sibling;
  763. }
  764. /* Assume if node is not present, PROM uses different tick mechanism
  765. * which we should not care about.
  766. */
  767. if (!dp) {
  768. prom_timers = (struct sun5_timer *) 0;
  769. return;
  770. }
  771. /* If PROM is really using this, it must be mapped by him. */
  772. addr = of_get_property(dp, "address", NULL);
  773. if (!addr) {
  774. prom_printf("PROM does not have timer mapped, trying to continue.\n");
  775. prom_timers = (struct sun5_timer *) 0;
  776. return;
  777. }
  778. prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
  779. }
  780. static void kill_prom_timer(void)
  781. {
  782. if (!prom_timers)
  783. return;
  784. /* Save them away for later. */
  785. prom_limit0 = prom_timers->limit0;
  786. prom_limit1 = prom_timers->limit1;
  787. /* Just as in sun4c PROM uses timer which ticks at IRQ 14.
  788. * We turn both off here just to be paranoid.
  789. */
  790. prom_timers->limit0 = 0;
  791. prom_timers->limit1 = 0;
  792. /* Wheee, eat the interrupt packet too... */
  793. __asm__ __volatile__(
  794. " mov 0x40, %%g2\n"
  795. " ldxa [%%g0] %0, %%g1\n"
  796. " ldxa [%%g2] %1, %%g1\n"
  797. " stxa %%g0, [%%g0] %0\n"
  798. " membar #Sync\n"
  799. : /* no outputs */
  800. : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
  801. : "g1", "g2");
  802. }
  803. void notrace init_irqwork_curcpu(void)
  804. {
  805. int cpu = hard_smp_processor_id();
  806. trap_block[cpu].irq_worklist_pa = 0UL;
  807. }
  808. /* Please be very careful with register_one_mondo() and
  809. * sun4v_register_mondo_queues().
  810. *
  811. * On SMP this gets invoked from the CPU trampoline before
  812. * the cpu has fully taken over the trap table from OBP,
  813. * and it's kernel stack + %g6 thread register state is
  814. * not fully cooked yet.
  815. *
  816. * Therefore you cannot make any OBP calls, not even prom_printf,
  817. * from these two routines.
  818. */
  819. static void notrace register_one_mondo(unsigned long paddr, unsigned long type,
  820. unsigned long qmask)
  821. {
  822. unsigned long num_entries = (qmask + 1) / 64;
  823. unsigned long status;
  824. status = sun4v_cpu_qconf(type, paddr, num_entries);
  825. if (status != HV_EOK) {
  826. prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
  827. "err %lu\n", type, paddr, num_entries, status);
  828. prom_halt();
  829. }
  830. }
  831. void notrace sun4v_register_mondo_queues(int this_cpu)
  832. {
  833. struct trap_per_cpu *tb = &trap_block[this_cpu];
  834. register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
  835. tb->cpu_mondo_qmask);
  836. register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
  837. tb->dev_mondo_qmask);
  838. register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
  839. tb->resum_qmask);
  840. register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
  841. tb->nonresum_qmask);
  842. }
  843. /* Each queue region must be a power of 2 multiple of 64 bytes in
  844. * size. The base real address must be aligned to the size of the
  845. * region. Thus, an 8KB queue must be 8KB aligned, for example.
  846. */
  847. static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask)
  848. {
  849. unsigned long size = PAGE_ALIGN(qmask + 1);
  850. unsigned long order = get_order(size);
  851. unsigned long p;
  852. p = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
  853. if (!p) {
  854. prom_printf("SUN4V: Error, cannot allocate queue.\n");
  855. prom_halt();
  856. }
  857. *pa_ptr = __pa(p);
  858. }
  859. static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
  860. {
  861. #ifdef CONFIG_SMP
  862. unsigned long page;
  863. void *mondo, *p;
  864. BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > PAGE_SIZE);
  865. /* Make sure mondo block is 64byte aligned */
  866. p = kzalloc(127, GFP_KERNEL);
  867. if (!p) {
  868. prom_printf("SUN4V: Error, cannot allocate mondo block.\n");
  869. prom_halt();
  870. }
  871. mondo = (void *)(((unsigned long)p + 63) & ~0x3f);
  872. tb->cpu_mondo_block_pa = __pa(mondo);
  873. page = get_zeroed_page(GFP_KERNEL);
  874. if (!page) {
  875. prom_printf("SUN4V: Error, cannot allocate cpu list page.\n");
  876. prom_halt();
  877. }
  878. tb->cpu_list_pa = __pa(page);
  879. #endif
  880. }
  881. /* Allocate mondo and error queues for all possible cpus. */
  882. static void __init sun4v_init_mondo_queues(void)
  883. {
  884. int cpu;
  885. for_each_possible_cpu(cpu) {
  886. struct trap_per_cpu *tb = &trap_block[cpu];
  887. alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
  888. alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
  889. alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask);
  890. alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask);
  891. alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
  892. alloc_one_queue(&tb->nonresum_kernel_buf_pa,
  893. tb->nonresum_qmask);
  894. }
  895. }
  896. static void __init init_send_mondo_info(void)
  897. {
  898. int cpu;
  899. for_each_possible_cpu(cpu) {
  900. struct trap_per_cpu *tb = &trap_block[cpu];
  901. init_cpu_send_mondo_info(tb);
  902. }
  903. }
  904. static struct irqaction timer_irq_action = {
  905. .name = "timer",
  906. };
  907. static void __init irq_ivector_init(void)
  908. {
  909. unsigned long size, order;
  910. unsigned int ivecs;
  911. /* If we are doing cookie only VIRQs then we do not need the ivector
  912. * table to process interrupts.
  913. */
  914. if (sun4v_cookie_only_virqs())
  915. return;
  916. ivecs = size_nr_ivec();
  917. size = sizeof(struct ino_bucket) * ivecs;
  918. order = get_order(size);
  919. ivector_table = (struct ino_bucket *)
  920. __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
  921. if (!ivector_table) {
  922. prom_printf("Fatal error, cannot allocate ivector_table\n");
  923. prom_halt();
  924. }
  925. __flush_dcache_range((unsigned long) ivector_table,
  926. ((unsigned long) ivector_table) + size);
  927. ivector_table_pa = __pa(ivector_table);
  928. }
  929. /* Only invoked on boot processor.*/
  930. void __init init_IRQ(void)
  931. {
  932. irq_init_hv();
  933. irq_ivector_init();
  934. map_prom_timers();
  935. kill_prom_timer();
  936. if (tlb_type == hypervisor)
  937. sun4v_init_mondo_queues();
  938. init_send_mondo_info();
  939. if (tlb_type == hypervisor) {
  940. /* Load up the boot cpu's entries. */
  941. sun4v_register_mondo_queues(hard_smp_processor_id());
  942. }
  943. /* We need to clear any IRQ's pending in the soft interrupt
  944. * registers, a spurious one could be left around from the
  945. * PROM timer which we just disabled.
  946. */
  947. clear_softint(get_softint());
  948. /* Now that ivector table is initialized, it is safe
  949. * to receive IRQ vector traps. We will normally take
  950. * one or two right now, in case some device PROM used
  951. * to boot us wants to speak to us. We just ignore them.
  952. */
  953. __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
  954. "or %%g1, %0, %%g1\n\t"
  955. "wrpr %%g1, 0x0, %%pstate"
  956. : /* No outputs */
  957. : "i" (PSTATE_IE)
  958. : "g1");
  959. irq_to_desc(0)->action = &timer_irq_action;
  960. }