iommu.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* iommu.c: Generic sparc64 IOMMU support.
  3. *
  4. * Copyright (C) 1999, 2007, 2008 David S. Miller (davem@davemloft.net)
  5. * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/export.h>
  9. #include <linux/slab.h>
  10. #include <linux/delay.h>
  11. #include <linux/device.h>
  12. #include <linux/dma-map-ops.h>
  13. #include <linux/errno.h>
  14. #include <linux/iommu-helper.h>
  15. #include <linux/bitmap.h>
  16. #include <asm/iommu-common.h>
  17. #ifdef CONFIG_PCI
  18. #include <linux/pci.h>
  19. #endif
  20. #include <asm/iommu.h>
  21. #include "iommu_common.h"
  22. #include "kernel.h"
  23. #define STC_CTXMATCH_ADDR(STC, CTX) \
  24. ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
  25. #define STC_FLUSHFLAG_INIT(STC) \
  26. (*((STC)->strbuf_flushflag) = 0UL)
  27. #define STC_FLUSHFLAG_SET(STC) \
  28. (*((STC)->strbuf_flushflag) != 0UL)
  29. #define iommu_read(__reg) \
  30. ({ u64 __ret; \
  31. __asm__ __volatile__("ldxa [%1] %2, %0" \
  32. : "=r" (__ret) \
  33. : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  34. : "memory"); \
  35. __ret; \
  36. })
  37. #define iommu_write(__reg, __val) \
  38. __asm__ __volatile__("stxa %0, [%1] %2" \
  39. : /* no outputs */ \
  40. : "r" (__val), "r" (__reg), \
  41. "i" (ASI_PHYS_BYPASS_EC_E))
  42. /* Must be invoked under the IOMMU lock. */
  43. static void iommu_flushall(struct iommu_map_table *iommu_map_table)
  44. {
  45. struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl);
  46. if (iommu->iommu_flushinv) {
  47. iommu_write(iommu->iommu_flushinv, ~(u64)0);
  48. } else {
  49. unsigned long tag;
  50. int entry;
  51. tag = iommu->iommu_tags;
  52. for (entry = 0; entry < 16; entry++) {
  53. iommu_write(tag, 0);
  54. tag += 8;
  55. }
  56. /* Ensure completion of previous PIO writes. */
  57. (void) iommu_read(iommu->write_complete_reg);
  58. }
  59. }
  60. #define IOPTE_CONSISTENT(CTX) \
  61. (IOPTE_VALID | IOPTE_CACHE | \
  62. (((CTX) << 47) & IOPTE_CONTEXT))
  63. #define IOPTE_STREAMING(CTX) \
  64. (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
  65. /* Existing mappings are never marked invalid, instead they
  66. * are pointed to a dummy page.
  67. */
  68. #define IOPTE_IS_DUMMY(iommu, iopte) \
  69. ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
  70. static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
  71. {
  72. unsigned long val = iopte_val(*iopte);
  73. val &= ~IOPTE_PAGE;
  74. val |= iommu->dummy_page_pa;
  75. iopte_val(*iopte) = val;
  76. }
  77. int iommu_table_init(struct iommu *iommu, int tsbsize,
  78. u32 dma_offset, u32 dma_addr_mask,
  79. int numa_node)
  80. {
  81. unsigned long i, order, sz, num_tsb_entries;
  82. struct page *page;
  83. num_tsb_entries = tsbsize / sizeof(iopte_t);
  84. /* Setup initial software IOMMU state. */
  85. spin_lock_init(&iommu->lock);
  86. iommu->ctx_lowest_free = 1;
  87. iommu->tbl.table_map_base = dma_offset;
  88. iommu->dma_addr_mask = dma_addr_mask;
  89. /* Allocate and initialize the free area map. */
  90. sz = num_tsb_entries / 8;
  91. sz = (sz + 7UL) & ~7UL;
  92. iommu->tbl.map = kzalloc_node(sz, GFP_KERNEL, numa_node);
  93. if (!iommu->tbl.map)
  94. return -ENOMEM;
  95. iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
  96. (tlb_type != hypervisor ? iommu_flushall : NULL),
  97. false, 1, false);
  98. /* Allocate and initialize the dummy page which we
  99. * set inactive IO PTEs to point to.
  100. */
  101. page = alloc_pages_node(numa_node, GFP_KERNEL, 0);
  102. if (!page) {
  103. printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
  104. goto out_free_map;
  105. }
  106. iommu->dummy_page = (unsigned long) page_address(page);
  107. memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
  108. iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
  109. /* Now allocate and setup the IOMMU page table itself. */
  110. order = get_order(tsbsize);
  111. page = alloc_pages_node(numa_node, GFP_KERNEL, order);
  112. if (!page) {
  113. printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
  114. goto out_free_dummy_page;
  115. }
  116. iommu->page_table = (iopte_t *)page_address(page);
  117. for (i = 0; i < num_tsb_entries; i++)
  118. iopte_make_dummy(iommu, &iommu->page_table[i]);
  119. return 0;
  120. out_free_dummy_page:
  121. free_page(iommu->dummy_page);
  122. iommu->dummy_page = 0UL;
  123. out_free_map:
  124. kfree(iommu->tbl.map);
  125. iommu->tbl.map = NULL;
  126. return -ENOMEM;
  127. }
  128. static inline iopte_t *alloc_npages(struct device *dev,
  129. struct iommu *iommu,
  130. unsigned long npages)
  131. {
  132. unsigned long entry;
  133. entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
  134. (unsigned long)(-1), 0);
  135. if (unlikely(entry == IOMMU_ERROR_CODE))
  136. return NULL;
  137. return iommu->page_table + entry;
  138. }
  139. static int iommu_alloc_ctx(struct iommu *iommu)
  140. {
  141. int lowest = iommu->ctx_lowest_free;
  142. int n = find_next_zero_bit(iommu->ctx_bitmap, IOMMU_NUM_CTXS, lowest);
  143. if (unlikely(n == IOMMU_NUM_CTXS)) {
  144. n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
  145. if (unlikely(n == lowest)) {
  146. printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
  147. n = 0;
  148. }
  149. }
  150. if (n)
  151. __set_bit(n, iommu->ctx_bitmap);
  152. return n;
  153. }
  154. static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
  155. {
  156. if (likely(ctx)) {
  157. __clear_bit(ctx, iommu->ctx_bitmap);
  158. if (ctx < iommu->ctx_lowest_free)
  159. iommu->ctx_lowest_free = ctx;
  160. }
  161. }
  162. static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
  163. dma_addr_t *dma_addrp, gfp_t gfp,
  164. unsigned long attrs)
  165. {
  166. unsigned long order, first_page;
  167. struct iommu *iommu;
  168. struct page *page;
  169. int npages, nid;
  170. iopte_t *iopte;
  171. void *ret;
  172. size = IO_PAGE_ALIGN(size);
  173. order = get_order(size);
  174. if (order >= 10)
  175. return NULL;
  176. nid = dev->archdata.numa_node;
  177. page = alloc_pages_node(nid, gfp, order);
  178. if (unlikely(!page))
  179. return NULL;
  180. first_page = (unsigned long) page_address(page);
  181. memset((char *)first_page, 0, PAGE_SIZE << order);
  182. iommu = dev->archdata.iommu;
  183. iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT);
  184. if (unlikely(iopte == NULL)) {
  185. free_pages(first_page, order);
  186. return NULL;
  187. }
  188. *dma_addrp = (iommu->tbl.table_map_base +
  189. ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
  190. ret = (void *) first_page;
  191. npages = size >> IO_PAGE_SHIFT;
  192. first_page = __pa(first_page);
  193. while (npages--) {
  194. iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
  195. IOPTE_WRITE |
  196. (first_page & IOPTE_PAGE));
  197. iopte++;
  198. first_page += IO_PAGE_SIZE;
  199. }
  200. return ret;
  201. }
  202. static void dma_4u_free_coherent(struct device *dev, size_t size,
  203. void *cpu, dma_addr_t dvma,
  204. unsigned long attrs)
  205. {
  206. struct iommu *iommu;
  207. unsigned long order, npages;
  208. npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
  209. iommu = dev->archdata.iommu;
  210. iommu_tbl_range_free(&iommu->tbl, dvma, npages, IOMMU_ERROR_CODE);
  211. order = get_order(size);
  212. if (order < 10)
  213. free_pages((unsigned long)cpu, order);
  214. }
  215. static dma_addr_t dma_4u_map_page(struct device *dev, struct page *page,
  216. unsigned long offset, size_t sz,
  217. enum dma_data_direction direction,
  218. unsigned long attrs)
  219. {
  220. struct iommu *iommu;
  221. struct strbuf *strbuf;
  222. iopte_t *base;
  223. unsigned long flags, npages, oaddr;
  224. unsigned long i, base_paddr, ctx;
  225. u32 bus_addr, ret;
  226. unsigned long iopte_protection;
  227. iommu = dev->archdata.iommu;
  228. strbuf = dev->archdata.stc;
  229. if (unlikely(direction == DMA_NONE))
  230. goto bad_no_ctx;
  231. oaddr = (unsigned long)(page_address(page) + offset);
  232. npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
  233. npages >>= IO_PAGE_SHIFT;
  234. base = alloc_npages(dev, iommu, npages);
  235. spin_lock_irqsave(&iommu->lock, flags);
  236. ctx = 0;
  237. if (iommu->iommu_ctxflush)
  238. ctx = iommu_alloc_ctx(iommu);
  239. spin_unlock_irqrestore(&iommu->lock, flags);
  240. if (unlikely(!base))
  241. goto bad;
  242. bus_addr = (iommu->tbl.table_map_base +
  243. ((base - iommu->page_table) << IO_PAGE_SHIFT));
  244. ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
  245. base_paddr = __pa(oaddr & IO_PAGE_MASK);
  246. if (strbuf->strbuf_enabled)
  247. iopte_protection = IOPTE_STREAMING(ctx);
  248. else
  249. iopte_protection = IOPTE_CONSISTENT(ctx);
  250. if (direction != DMA_TO_DEVICE)
  251. iopte_protection |= IOPTE_WRITE;
  252. for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
  253. iopte_val(*base) = iopte_protection | base_paddr;
  254. return ret;
  255. bad:
  256. iommu_free_ctx(iommu, ctx);
  257. bad_no_ctx:
  258. if (printk_ratelimit())
  259. WARN_ON(1);
  260. return DMA_MAPPING_ERROR;
  261. }
  262. static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu,
  263. u32 vaddr, unsigned long ctx, unsigned long npages,
  264. enum dma_data_direction direction)
  265. {
  266. int limit;
  267. if (strbuf->strbuf_ctxflush &&
  268. iommu->iommu_ctxflush) {
  269. unsigned long matchreg, flushreg;
  270. u64 val;
  271. flushreg = strbuf->strbuf_ctxflush;
  272. matchreg = STC_CTXMATCH_ADDR(strbuf, ctx);
  273. iommu_write(flushreg, ctx);
  274. val = iommu_read(matchreg);
  275. val &= 0xffff;
  276. if (!val)
  277. goto do_flush_sync;
  278. while (val) {
  279. if (val & 0x1)
  280. iommu_write(flushreg, ctx);
  281. val >>= 1;
  282. }
  283. val = iommu_read(matchreg);
  284. if (unlikely(val)) {
  285. printk(KERN_WARNING "strbuf_flush: ctx flush "
  286. "timeout matchreg[%llx] ctx[%lx]\n",
  287. val, ctx);
  288. goto do_page_flush;
  289. }
  290. } else {
  291. unsigned long i;
  292. do_page_flush:
  293. for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
  294. iommu_write(strbuf->strbuf_pflush, vaddr);
  295. }
  296. do_flush_sync:
  297. /* If the device could not have possibly put dirty data into
  298. * the streaming cache, no flush-flag synchronization needs
  299. * to be performed.
  300. */
  301. if (direction == DMA_TO_DEVICE)
  302. return;
  303. STC_FLUSHFLAG_INIT(strbuf);
  304. iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
  305. (void) iommu_read(iommu->write_complete_reg);
  306. limit = 100000;
  307. while (!STC_FLUSHFLAG_SET(strbuf)) {
  308. limit--;
  309. if (!limit)
  310. break;
  311. udelay(1);
  312. rmb();
  313. }
  314. if (!limit)
  315. printk(KERN_WARNING "strbuf_flush: flushflag timeout "
  316. "vaddr[%08x] ctx[%lx] npages[%ld]\n",
  317. vaddr, ctx, npages);
  318. }
  319. static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
  320. size_t sz, enum dma_data_direction direction,
  321. unsigned long attrs)
  322. {
  323. struct iommu *iommu;
  324. struct strbuf *strbuf;
  325. iopte_t *base;
  326. unsigned long flags, npages, ctx, i;
  327. if (unlikely(direction == DMA_NONE)) {
  328. if (printk_ratelimit())
  329. WARN_ON(1);
  330. return;
  331. }
  332. iommu = dev->archdata.iommu;
  333. strbuf = dev->archdata.stc;
  334. npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
  335. npages >>= IO_PAGE_SHIFT;
  336. base = iommu->page_table +
  337. ((bus_addr - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT);
  338. bus_addr &= IO_PAGE_MASK;
  339. spin_lock_irqsave(&iommu->lock, flags);
  340. /* Record the context, if any. */
  341. ctx = 0;
  342. if (iommu->iommu_ctxflush)
  343. ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
  344. /* Step 1: Kick data out of streaming buffers if necessary. */
  345. if (strbuf->strbuf_enabled && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
  346. strbuf_flush(strbuf, iommu, bus_addr, ctx,
  347. npages, direction);
  348. /* Step 2: Clear out TSB entries. */
  349. for (i = 0; i < npages; i++)
  350. iopte_make_dummy(iommu, base + i);
  351. iommu_free_ctx(iommu, ctx);
  352. spin_unlock_irqrestore(&iommu->lock, flags);
  353. iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE);
  354. }
  355. static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
  356. int nelems, enum dma_data_direction direction,
  357. unsigned long attrs)
  358. {
  359. struct scatterlist *s, *outs, *segstart;
  360. unsigned long flags, handle, prot, ctx;
  361. dma_addr_t dma_next = 0, dma_addr;
  362. unsigned int max_seg_size;
  363. unsigned long seg_boundary_size;
  364. int outcount, incount, i;
  365. struct strbuf *strbuf;
  366. struct iommu *iommu;
  367. unsigned long base_shift;
  368. BUG_ON(direction == DMA_NONE);
  369. iommu = dev->archdata.iommu;
  370. strbuf = dev->archdata.stc;
  371. if (nelems == 0 || !iommu)
  372. return 0;
  373. spin_lock_irqsave(&iommu->lock, flags);
  374. ctx = 0;
  375. if (iommu->iommu_ctxflush)
  376. ctx = iommu_alloc_ctx(iommu);
  377. if (strbuf->strbuf_enabled)
  378. prot = IOPTE_STREAMING(ctx);
  379. else
  380. prot = IOPTE_CONSISTENT(ctx);
  381. if (direction != DMA_TO_DEVICE)
  382. prot |= IOPTE_WRITE;
  383. outs = s = segstart = &sglist[0];
  384. outcount = 1;
  385. incount = nelems;
  386. handle = 0;
  387. /* Init first segment length for backout at failure */
  388. outs->dma_length = 0;
  389. max_seg_size = dma_get_max_seg_size(dev);
  390. seg_boundary_size = dma_get_seg_boundary_nr_pages(dev, IO_PAGE_SHIFT);
  391. base_shift = iommu->tbl.table_map_base >> IO_PAGE_SHIFT;
  392. for_each_sg(sglist, s, nelems, i) {
  393. unsigned long paddr, npages, entry, out_entry = 0, slen;
  394. iopte_t *base;
  395. slen = s->length;
  396. /* Sanity check */
  397. if (slen == 0) {
  398. dma_next = 0;
  399. continue;
  400. }
  401. /* Allocate iommu entries for that segment */
  402. paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
  403. npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
  404. entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages,
  405. &handle, (unsigned long)(-1), 0);
  406. /* Handle failure */
  407. if (unlikely(entry == IOMMU_ERROR_CODE)) {
  408. if (printk_ratelimit())
  409. printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
  410. " npages %lx\n", iommu, paddr, npages);
  411. goto iommu_map_failed;
  412. }
  413. base = iommu->page_table + entry;
  414. /* Convert entry to a dma_addr_t */
  415. dma_addr = iommu->tbl.table_map_base +
  416. (entry << IO_PAGE_SHIFT);
  417. dma_addr |= (s->offset & ~IO_PAGE_MASK);
  418. /* Insert into HW table */
  419. paddr &= IO_PAGE_MASK;
  420. while (npages--) {
  421. iopte_val(*base) = prot | paddr;
  422. base++;
  423. paddr += IO_PAGE_SIZE;
  424. }
  425. /* If we are in an open segment, try merging */
  426. if (segstart != s) {
  427. /* We cannot merge if:
  428. * - allocated dma_addr isn't contiguous to previous allocation
  429. */
  430. if ((dma_addr != dma_next) ||
  431. (outs->dma_length + s->length > max_seg_size) ||
  432. (is_span_boundary(out_entry, base_shift,
  433. seg_boundary_size, outs, s))) {
  434. /* Can't merge: create a new segment */
  435. segstart = s;
  436. outcount++;
  437. outs = sg_next(outs);
  438. } else {
  439. outs->dma_length += s->length;
  440. }
  441. }
  442. if (segstart == s) {
  443. /* This is a new segment, fill entries */
  444. outs->dma_address = dma_addr;
  445. outs->dma_length = slen;
  446. out_entry = entry;
  447. }
  448. /* Calculate next page pointer for contiguous check */
  449. dma_next = dma_addr + slen;
  450. }
  451. spin_unlock_irqrestore(&iommu->lock, flags);
  452. if (outcount < incount) {
  453. outs = sg_next(outs);
  454. outs->dma_address = DMA_MAPPING_ERROR;
  455. outs->dma_length = 0;
  456. }
  457. return outcount;
  458. iommu_map_failed:
  459. for_each_sg(sglist, s, nelems, i) {
  460. if (s->dma_length != 0) {
  461. unsigned long vaddr, npages, entry, j;
  462. iopte_t *base;
  463. vaddr = s->dma_address & IO_PAGE_MASK;
  464. npages = iommu_num_pages(s->dma_address, s->dma_length,
  465. IO_PAGE_SIZE);
  466. entry = (vaddr - iommu->tbl.table_map_base)
  467. >> IO_PAGE_SHIFT;
  468. base = iommu->page_table + entry;
  469. for (j = 0; j < npages; j++)
  470. iopte_make_dummy(iommu, base + j);
  471. iommu_tbl_range_free(&iommu->tbl, vaddr, npages,
  472. IOMMU_ERROR_CODE);
  473. s->dma_address = DMA_MAPPING_ERROR;
  474. s->dma_length = 0;
  475. }
  476. if (s == outs)
  477. break;
  478. }
  479. spin_unlock_irqrestore(&iommu->lock, flags);
  480. return 0;
  481. }
  482. /* If contexts are being used, they are the same in all of the mappings
  483. * we make for a particular SG.
  484. */
  485. static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg)
  486. {
  487. unsigned long ctx = 0;
  488. if (iommu->iommu_ctxflush) {
  489. iopte_t *base;
  490. u32 bus_addr;
  491. struct iommu_map_table *tbl = &iommu->tbl;
  492. bus_addr = sg->dma_address & IO_PAGE_MASK;
  493. base = iommu->page_table +
  494. ((bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT);
  495. ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
  496. }
  497. return ctx;
  498. }
  499. static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
  500. int nelems, enum dma_data_direction direction,
  501. unsigned long attrs)
  502. {
  503. unsigned long flags, ctx;
  504. struct scatterlist *sg;
  505. struct strbuf *strbuf;
  506. struct iommu *iommu;
  507. BUG_ON(direction == DMA_NONE);
  508. iommu = dev->archdata.iommu;
  509. strbuf = dev->archdata.stc;
  510. ctx = fetch_sg_ctx(iommu, sglist);
  511. spin_lock_irqsave(&iommu->lock, flags);
  512. sg = sglist;
  513. while (nelems--) {
  514. dma_addr_t dma_handle = sg->dma_address;
  515. unsigned int len = sg->dma_length;
  516. unsigned long npages, entry;
  517. iopte_t *base;
  518. int i;
  519. if (!len)
  520. break;
  521. npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
  522. entry = ((dma_handle - iommu->tbl.table_map_base)
  523. >> IO_PAGE_SHIFT);
  524. base = iommu->page_table + entry;
  525. dma_handle &= IO_PAGE_MASK;
  526. if (strbuf->strbuf_enabled && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
  527. strbuf_flush(strbuf, iommu, dma_handle, ctx,
  528. npages, direction);
  529. for (i = 0; i < npages; i++)
  530. iopte_make_dummy(iommu, base + i);
  531. iommu_tbl_range_free(&iommu->tbl, dma_handle, npages,
  532. IOMMU_ERROR_CODE);
  533. sg = sg_next(sg);
  534. }
  535. iommu_free_ctx(iommu, ctx);
  536. spin_unlock_irqrestore(&iommu->lock, flags);
  537. }
  538. static void dma_4u_sync_single_for_cpu(struct device *dev,
  539. dma_addr_t bus_addr, size_t sz,
  540. enum dma_data_direction direction)
  541. {
  542. struct iommu *iommu;
  543. struct strbuf *strbuf;
  544. unsigned long flags, ctx, npages;
  545. iommu = dev->archdata.iommu;
  546. strbuf = dev->archdata.stc;
  547. if (!strbuf->strbuf_enabled)
  548. return;
  549. spin_lock_irqsave(&iommu->lock, flags);
  550. npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
  551. npages >>= IO_PAGE_SHIFT;
  552. bus_addr &= IO_PAGE_MASK;
  553. /* Step 1: Record the context, if any. */
  554. ctx = 0;
  555. if (iommu->iommu_ctxflush &&
  556. strbuf->strbuf_ctxflush) {
  557. iopte_t *iopte;
  558. struct iommu_map_table *tbl = &iommu->tbl;
  559. iopte = iommu->page_table +
  560. ((bus_addr - tbl->table_map_base)>>IO_PAGE_SHIFT);
  561. ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
  562. }
  563. /* Step 2: Kick data out of streaming buffers. */
  564. strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
  565. spin_unlock_irqrestore(&iommu->lock, flags);
  566. }
  567. static void dma_4u_sync_sg_for_cpu(struct device *dev,
  568. struct scatterlist *sglist, int nelems,
  569. enum dma_data_direction direction)
  570. {
  571. struct iommu *iommu;
  572. struct strbuf *strbuf;
  573. unsigned long flags, ctx, npages, i;
  574. struct scatterlist *sg, *sgprv;
  575. u32 bus_addr;
  576. iommu = dev->archdata.iommu;
  577. strbuf = dev->archdata.stc;
  578. if (!strbuf->strbuf_enabled)
  579. return;
  580. spin_lock_irqsave(&iommu->lock, flags);
  581. /* Step 1: Record the context, if any. */
  582. ctx = 0;
  583. if (iommu->iommu_ctxflush &&
  584. strbuf->strbuf_ctxflush) {
  585. iopte_t *iopte;
  586. struct iommu_map_table *tbl = &iommu->tbl;
  587. iopte = iommu->page_table + ((sglist[0].dma_address -
  588. tbl->table_map_base) >> IO_PAGE_SHIFT);
  589. ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
  590. }
  591. /* Step 2: Kick data out of streaming buffers. */
  592. bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
  593. sgprv = NULL;
  594. for_each_sg(sglist, sg, nelems, i) {
  595. if (sg->dma_length == 0)
  596. break;
  597. sgprv = sg;
  598. }
  599. npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length)
  600. - bus_addr) >> IO_PAGE_SHIFT;
  601. strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
  602. spin_unlock_irqrestore(&iommu->lock, flags);
  603. }
  604. static int dma_4u_supported(struct device *dev, u64 device_mask)
  605. {
  606. struct iommu *iommu = dev->archdata.iommu;
  607. if (ali_sound_dma_hack(dev, device_mask))
  608. return 1;
  609. if (device_mask < iommu->dma_addr_mask)
  610. return 0;
  611. return 1;
  612. }
  613. static const struct dma_map_ops sun4u_dma_ops = {
  614. .alloc = dma_4u_alloc_coherent,
  615. .free = dma_4u_free_coherent,
  616. .map_page = dma_4u_map_page,
  617. .unmap_page = dma_4u_unmap_page,
  618. .map_sg = dma_4u_map_sg,
  619. .unmap_sg = dma_4u_unmap_sg,
  620. .sync_single_for_cpu = dma_4u_sync_single_for_cpu,
  621. .sync_sg_for_cpu = dma_4u_sync_sg_for_cpu,
  622. .dma_supported = dma_4u_supported,
  623. };
  624. const struct dma_map_ops *dma_ops = &sun4u_dma_ops;
  625. EXPORT_SYMBOL(dma_ops);