iommu-common.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * IOMMU mmap management and range allocation functions.
  4. * Based almost entirely upon the powerpc iommu allocator.
  5. */
  6. #include <linux/export.h>
  7. #include <linux/bitmap.h>
  8. #include <linux/bug.h>
  9. #include <linux/iommu-helper.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/hash.h>
  12. #include <asm/iommu-common.h>
  13. static unsigned long iommu_large_alloc = 15;
  14. static DEFINE_PER_CPU(unsigned int, iommu_hash_common);
  15. static inline bool need_flush(struct iommu_map_table *iommu)
  16. {
  17. return ((iommu->flags & IOMMU_NEED_FLUSH) != 0);
  18. }
  19. static inline void set_flush(struct iommu_map_table *iommu)
  20. {
  21. iommu->flags |= IOMMU_NEED_FLUSH;
  22. }
  23. static inline void clear_flush(struct iommu_map_table *iommu)
  24. {
  25. iommu->flags &= ~IOMMU_NEED_FLUSH;
  26. }
  27. static void setup_iommu_pool_hash(void)
  28. {
  29. unsigned int i;
  30. static bool do_once;
  31. if (do_once)
  32. return;
  33. do_once = true;
  34. for_each_possible_cpu(i)
  35. per_cpu(iommu_hash_common, i) = hash_32(i, IOMMU_POOL_HASHBITS);
  36. }
  37. /*
  38. * Initialize iommu_pool entries for the iommu_map_table. `num_entries'
  39. * is the number of table entries. If `large_pool' is set to true,
  40. * the top 1/4 of the table will be set aside for pool allocations
  41. * of more than iommu_large_alloc pages.
  42. */
  43. void iommu_tbl_pool_init(struct iommu_map_table *iommu,
  44. unsigned long num_entries,
  45. u32 table_shift,
  46. void (*lazy_flush)(struct iommu_map_table *),
  47. bool large_pool, u32 npools,
  48. bool skip_span_boundary_check)
  49. {
  50. unsigned int start, i;
  51. struct iommu_pool *p = &(iommu->large_pool);
  52. setup_iommu_pool_hash();
  53. if (npools == 0)
  54. iommu->nr_pools = IOMMU_NR_POOLS;
  55. else
  56. iommu->nr_pools = npools;
  57. BUG_ON(npools > IOMMU_NR_POOLS);
  58. iommu->table_shift = table_shift;
  59. iommu->lazy_flush = lazy_flush;
  60. start = 0;
  61. if (skip_span_boundary_check)
  62. iommu->flags |= IOMMU_NO_SPAN_BOUND;
  63. if (large_pool)
  64. iommu->flags |= IOMMU_HAS_LARGE_POOL;
  65. if (!large_pool)
  66. iommu->poolsize = num_entries/iommu->nr_pools;
  67. else
  68. iommu->poolsize = (num_entries * 3 / 4)/iommu->nr_pools;
  69. for (i = 0; i < iommu->nr_pools; i++) {
  70. spin_lock_init(&(iommu->pools[i].lock));
  71. iommu->pools[i].start = start;
  72. iommu->pools[i].hint = start;
  73. start += iommu->poolsize; /* start for next pool */
  74. iommu->pools[i].end = start - 1;
  75. }
  76. if (!large_pool)
  77. return;
  78. /* initialize large_pool */
  79. spin_lock_init(&(p->lock));
  80. p->start = start;
  81. p->hint = p->start;
  82. p->end = num_entries;
  83. }
  84. unsigned long iommu_tbl_range_alloc(struct device *dev,
  85. struct iommu_map_table *iommu,
  86. unsigned long npages,
  87. unsigned long *handle,
  88. unsigned long mask,
  89. unsigned int align_order)
  90. {
  91. unsigned int pool_hash = __this_cpu_read(iommu_hash_common);
  92. unsigned long n, end, start, limit, boundary_size;
  93. struct iommu_pool *pool;
  94. int pass = 0;
  95. unsigned int pool_nr;
  96. unsigned int npools = iommu->nr_pools;
  97. unsigned long flags;
  98. bool large_pool = ((iommu->flags & IOMMU_HAS_LARGE_POOL) != 0);
  99. bool largealloc = (large_pool && npages > iommu_large_alloc);
  100. unsigned long shift;
  101. unsigned long align_mask = 0;
  102. if (align_order > 0)
  103. align_mask = ~0ul >> (BITS_PER_LONG - align_order);
  104. /* Sanity check */
  105. if (unlikely(npages == 0)) {
  106. WARN_ON_ONCE(1);
  107. return IOMMU_ERROR_CODE;
  108. }
  109. if (largealloc) {
  110. pool = &(iommu->large_pool);
  111. pool_nr = 0; /* to keep compiler happy */
  112. } else {
  113. /* pick out pool_nr */
  114. pool_nr = pool_hash & (npools - 1);
  115. pool = &(iommu->pools[pool_nr]);
  116. }
  117. spin_lock_irqsave(&pool->lock, flags);
  118. again:
  119. if (pass == 0 && handle && *handle &&
  120. (*handle >= pool->start) && (*handle < pool->end))
  121. start = *handle;
  122. else
  123. start = pool->hint;
  124. limit = pool->end;
  125. /* The case below can happen if we have a small segment appended
  126. * to a large, or when the previous alloc was at the very end of
  127. * the available space. If so, go back to the beginning. If a
  128. * flush is needed, it will get done based on the return value
  129. * from iommu_area_alloc() below.
  130. */
  131. if (start >= limit)
  132. start = pool->start;
  133. shift = iommu->table_map_base >> iommu->table_shift;
  134. if (limit + shift > mask) {
  135. limit = mask - shift + 1;
  136. /* If we're constrained on address range, first try
  137. * at the masked hint to avoid O(n) search complexity,
  138. * but on second pass, start at 0 in pool 0.
  139. */
  140. if ((start & mask) >= limit || pass > 0) {
  141. spin_unlock(&(pool->lock));
  142. pool = &(iommu->pools[0]);
  143. spin_lock(&(pool->lock));
  144. start = pool->start;
  145. } else {
  146. start &= mask;
  147. }
  148. }
  149. /*
  150. * if the skip_span_boundary_check had been set during init, we set
  151. * things up so that iommu_is_span_boundary() merely checks if the
  152. * (index + npages) < num_tsb_entries
  153. */
  154. if ((iommu->flags & IOMMU_NO_SPAN_BOUND) != 0) {
  155. shift = 0;
  156. boundary_size = iommu->poolsize * iommu->nr_pools;
  157. } else {
  158. boundary_size = dma_get_seg_boundary_nr_pages(dev,
  159. iommu->table_shift);
  160. }
  161. n = iommu_area_alloc(iommu->map, limit, start, npages, shift,
  162. boundary_size, align_mask);
  163. if (n == -1) {
  164. if (likely(pass == 0)) {
  165. /* First failure, rescan from the beginning. */
  166. pool->hint = pool->start;
  167. set_flush(iommu);
  168. pass++;
  169. goto again;
  170. } else if (!largealloc && pass <= iommu->nr_pools) {
  171. spin_unlock(&(pool->lock));
  172. pool_nr = (pool_nr + 1) & (iommu->nr_pools - 1);
  173. pool = &(iommu->pools[pool_nr]);
  174. spin_lock(&(pool->lock));
  175. pool->hint = pool->start;
  176. set_flush(iommu);
  177. pass++;
  178. goto again;
  179. } else {
  180. /* give up */
  181. n = IOMMU_ERROR_CODE;
  182. goto bail;
  183. }
  184. }
  185. if (iommu->lazy_flush &&
  186. (n < pool->hint || need_flush(iommu))) {
  187. clear_flush(iommu);
  188. iommu->lazy_flush(iommu);
  189. }
  190. end = n + npages;
  191. pool->hint = end;
  192. /* Update handle for SG allocations */
  193. if (handle)
  194. *handle = end;
  195. bail:
  196. spin_unlock_irqrestore(&(pool->lock), flags);
  197. return n;
  198. }
  199. static struct iommu_pool *get_pool(struct iommu_map_table *tbl,
  200. unsigned long entry)
  201. {
  202. struct iommu_pool *p;
  203. unsigned long largepool_start = tbl->large_pool.start;
  204. bool large_pool = ((tbl->flags & IOMMU_HAS_LARGE_POOL) != 0);
  205. /* The large pool is the last pool at the top of the table */
  206. if (large_pool && entry >= largepool_start) {
  207. p = &tbl->large_pool;
  208. } else {
  209. unsigned int pool_nr = entry / tbl->poolsize;
  210. BUG_ON(pool_nr >= tbl->nr_pools);
  211. p = &tbl->pools[pool_nr];
  212. }
  213. return p;
  214. }
  215. /* Caller supplies the index of the entry into the iommu map table
  216. * itself when the mapping from dma_addr to the entry is not the
  217. * default addr->entry mapping below.
  218. */
  219. void iommu_tbl_range_free(struct iommu_map_table *iommu, u64 dma_addr,
  220. unsigned long npages, unsigned long entry)
  221. {
  222. struct iommu_pool *pool;
  223. unsigned long flags;
  224. unsigned long shift = iommu->table_shift;
  225. if (entry == IOMMU_ERROR_CODE) /* use default addr->entry mapping */
  226. entry = (dma_addr - iommu->table_map_base) >> shift;
  227. pool = get_pool(iommu, entry);
  228. spin_lock_irqsave(&(pool->lock), flags);
  229. bitmap_clear(iommu->map, entry, npages);
  230. spin_unlock_irqrestore(&(pool->lock), flags);
  231. }