head_64.S 23 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* head.S: Initial boot code for the Sparc64 port of Linux.
  3. *
  4. * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
  5. * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
  6. * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  7. * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
  8. */
  9. #include <linux/version.h>
  10. #include <linux/errno.h>
  11. #include <linux/threads.h>
  12. #include <linux/init.h>
  13. #include <linux/linkage.h>
  14. #include <linux/pgtable.h>
  15. #include <asm/thread_info.h>
  16. #include <asm/asi.h>
  17. #include <asm/pstate.h>
  18. #include <asm/ptrace.h>
  19. #include <asm/spitfire.h>
  20. #include <asm/page.h>
  21. #include <asm/errno.h>
  22. #include <asm/signal.h>
  23. #include <asm/processor.h>
  24. #include <asm/lsu.h>
  25. #include <asm/dcr.h>
  26. #include <asm/dcu.h>
  27. #include <asm/head.h>
  28. #include <asm/ttable.h>
  29. #include <asm/mmu.h>
  30. #include <asm/cpudata.h>
  31. #include <asm/pil.h>
  32. #include <asm/estate.h>
  33. #include <asm/sfafsr.h>
  34. #include <asm/unistd.h>
  35. #include <asm/export.h>
  36. /* This section from from _start to sparc64_boot_end should fit into
  37. * 0x0000000000404000 to 0x0000000000408000.
  38. */
  39. .text
  40. .globl start, _start, stext, _stext
  41. _start:
  42. start:
  43. _stext:
  44. stext:
  45. ! 0x0000000000404000
  46. b sparc64_boot
  47. flushw /* Flush register file. */
  48. /* This stuff has to be in sync with SILO and other potential boot loaders
  49. * Fields should be kept upward compatible and whenever any change is made,
  50. * HdrS version should be incremented.
  51. */
  52. .global root_flags, ram_flags, root_dev
  53. .global sparc_ramdisk_image, sparc_ramdisk_size
  54. .global sparc_ramdisk_image64
  55. .ascii "HdrS"
  56. .word LINUX_VERSION_CODE
  57. /* History:
  58. *
  59. * 0x0300 : Supports being located at other than 0x4000
  60. * 0x0202 : Supports kernel params string
  61. * 0x0201 : Supports reboot_command
  62. */
  63. .half 0x0301 /* HdrS version */
  64. root_flags:
  65. .half 1
  66. root_dev:
  67. .half 0
  68. ram_flags:
  69. .half 0
  70. sparc_ramdisk_image:
  71. .word 0
  72. sparc_ramdisk_size:
  73. .word 0
  74. .xword reboot_command
  75. .xword bootstr_info
  76. sparc_ramdisk_image64:
  77. .xword 0
  78. .word _end
  79. /* PROM cif handler code address is in %o4. */
  80. sparc64_boot:
  81. mov %o4, %l7
  82. /* We need to remap the kernel. Use position independent
  83. * code to remap us to KERNBASE.
  84. *
  85. * SILO can invoke us with 32-bit address masking enabled,
  86. * so make sure that's clear.
  87. */
  88. rdpr %pstate, %g1
  89. andn %g1, PSTATE_AM, %g1
  90. wrpr %g1, 0x0, %pstate
  91. ba,a,pt %xcc, 1f
  92. nop
  93. .globl prom_finddev_name, prom_chosen_path, prom_root_node
  94. .globl prom_getprop_name, prom_mmu_name, prom_peer_name
  95. .globl prom_callmethod_name, prom_translate_name, prom_root_compatible
  96. .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
  97. .globl prom_boot_mapped_pc, prom_boot_mapping_mode
  98. .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
  99. .globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible
  100. .globl is_sun4v, sun4v_chip_type, prom_set_trap_table_name
  101. prom_peer_name:
  102. .asciz "peer"
  103. prom_compatible_name:
  104. .asciz "compatible"
  105. prom_finddev_name:
  106. .asciz "finddevice"
  107. prom_chosen_path:
  108. .asciz "/chosen"
  109. prom_cpu_path:
  110. .asciz "/cpu"
  111. prom_getprop_name:
  112. .asciz "getprop"
  113. prom_mmu_name:
  114. .asciz "mmu"
  115. prom_callmethod_name:
  116. .asciz "call-method"
  117. prom_translate_name:
  118. .asciz "translate"
  119. prom_map_name:
  120. .asciz "map"
  121. prom_unmap_name:
  122. .asciz "unmap"
  123. prom_set_trap_table_name:
  124. .asciz "SUNW,set-trap-table"
  125. prom_sun4v_name:
  126. .asciz "sun4v"
  127. prom_niagara_prefix:
  128. .asciz "SUNW,UltraSPARC-T"
  129. prom_sparc_prefix:
  130. .asciz "SPARC-"
  131. prom_sparc64x_prefix:
  132. .asciz "SPARC64-X"
  133. .align 4
  134. prom_root_compatible:
  135. .skip 64
  136. prom_cpu_compatible:
  137. .skip 64
  138. prom_root_node:
  139. .word 0
  140. EXPORT_SYMBOL(prom_root_node)
  141. prom_mmu_ihandle_cache:
  142. .word 0
  143. prom_boot_mapped_pc:
  144. .word 0
  145. prom_boot_mapping_mode:
  146. .word 0
  147. .align 8
  148. prom_boot_mapping_phys_high:
  149. .xword 0
  150. prom_boot_mapping_phys_low:
  151. .xword 0
  152. is_sun4v:
  153. .word 0
  154. sun4v_chip_type:
  155. .word SUN4V_CHIP_INVALID
  156. EXPORT_SYMBOL(sun4v_chip_type)
  157. 1:
  158. rd %pc, %l0
  159. mov (1b - prom_peer_name), %l1
  160. sub %l0, %l1, %l1
  161. mov 0, %l2
  162. /* prom_root_node = prom_peer(0) */
  163. stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
  164. mov 1, %l3
  165. stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
  166. stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
  167. stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
  168. stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
  169. call %l7
  170. add %sp, (2047 + 128), %o0 ! argument array
  171. ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
  172. mov (1b - prom_root_node), %l1
  173. sub %l0, %l1, %l1
  174. stw %l4, [%l1]
  175. mov (1b - prom_getprop_name), %l1
  176. mov (1b - prom_compatible_name), %l2
  177. mov (1b - prom_root_compatible), %l5
  178. sub %l0, %l1, %l1
  179. sub %l0, %l2, %l2
  180. sub %l0, %l5, %l5
  181. /* prom_getproperty(prom_root_node, "compatible",
  182. * &prom_root_compatible, 64)
  183. */
  184. stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
  185. mov 4, %l3
  186. stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
  187. mov 1, %l3
  188. stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
  189. stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
  190. stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
  191. stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
  192. mov 64, %l3
  193. stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
  194. stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
  195. call %l7
  196. add %sp, (2047 + 128), %o0 ! argument array
  197. mov (1b - prom_finddev_name), %l1
  198. mov (1b - prom_chosen_path), %l2
  199. mov (1b - prom_boot_mapped_pc), %l3
  200. sub %l0, %l1, %l1
  201. sub %l0, %l2, %l2
  202. sub %l0, %l3, %l3
  203. stw %l0, [%l3]
  204. sub %sp, (192 + 128), %sp
  205. /* chosen_node = prom_finddevice("/chosen") */
  206. stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
  207. mov 1, %l3
  208. stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
  209. stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
  210. stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
  211. stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
  212. call %l7
  213. add %sp, (2047 + 128), %o0 ! argument array
  214. ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
  215. mov (1b - prom_getprop_name), %l1
  216. mov (1b - prom_mmu_name), %l2
  217. mov (1b - prom_mmu_ihandle_cache), %l5
  218. sub %l0, %l1, %l1
  219. sub %l0, %l2, %l2
  220. sub %l0, %l5, %l5
  221. /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
  222. stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
  223. mov 4, %l3
  224. stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
  225. mov 1, %l3
  226. stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
  227. stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
  228. stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
  229. stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
  230. mov 4, %l3
  231. stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
  232. stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
  233. call %l7
  234. add %sp, (2047 + 128), %o0 ! argument array
  235. mov (1b - prom_callmethod_name), %l1
  236. mov (1b - prom_translate_name), %l2
  237. sub %l0, %l1, %l1
  238. sub %l0, %l2, %l2
  239. lduw [%l5], %l5 ! prom_mmu_ihandle_cache
  240. stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
  241. mov 3, %l3
  242. stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
  243. mov 5, %l3
  244. stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
  245. stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
  246. stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
  247. /* PAGE align */
  248. srlx %l0, 13, %l3
  249. sllx %l3, 13, %l3
  250. stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
  251. stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
  252. stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
  253. stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
  254. stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
  255. stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
  256. call %l7
  257. add %sp, (2047 + 128), %o0 ! argument array
  258. ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
  259. mov (1b - prom_boot_mapping_mode), %l4
  260. sub %l0, %l4, %l4
  261. stw %l1, [%l4]
  262. mov (1b - prom_boot_mapping_phys_high), %l4
  263. sub %l0, %l4, %l4
  264. ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
  265. stx %l2, [%l4 + 0x0]
  266. ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
  267. /* 4MB align */
  268. srlx %l3, ILOG2_4MB, %l3
  269. sllx %l3, ILOG2_4MB, %l3
  270. stx %l3, [%l4 + 0x8]
  271. /* Leave service as-is, "call-method" */
  272. mov 7, %l3
  273. stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
  274. mov 1, %l3
  275. stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
  276. mov (1b - prom_map_name), %l3
  277. sub %l0, %l3, %l3
  278. stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
  279. /* Leave arg2 as-is, prom_mmu_ihandle_cache */
  280. mov -1, %l3
  281. stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
  282. /* 4MB align the kernel image size. */
  283. set (_end - KERNBASE), %l3
  284. set ((4 * 1024 * 1024) - 1), %l4
  285. add %l3, %l4, %l3
  286. andn %l3, %l4, %l3
  287. stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: roundup(ksize, 4MB)
  288. sethi %hi(KERNBASE), %l3
  289. stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
  290. stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
  291. mov (1b - prom_boot_mapping_phys_low), %l3
  292. sub %l0, %l3, %l3
  293. ldx [%l3], %l3
  294. stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
  295. call %l7
  296. add %sp, (2047 + 128), %o0 ! argument array
  297. add %sp, (192 + 128), %sp
  298. sethi %hi(prom_root_compatible), %g1
  299. or %g1, %lo(prom_root_compatible), %g1
  300. sethi %hi(prom_sun4v_name), %g7
  301. or %g7, %lo(prom_sun4v_name), %g7
  302. mov 5, %g3
  303. 90: ldub [%g7], %g2
  304. ldub [%g1], %g4
  305. cmp %g2, %g4
  306. bne,pn %icc, 80f
  307. add %g7, 1, %g7
  308. subcc %g3, 1, %g3
  309. bne,pt %xcc, 90b
  310. add %g1, 1, %g1
  311. sethi %hi(is_sun4v), %g1
  312. or %g1, %lo(is_sun4v), %g1
  313. mov 1, %g7
  314. stw %g7, [%g1]
  315. /* cpu_node = prom_finddevice("/cpu") */
  316. mov (1b - prom_finddev_name), %l1
  317. mov (1b - prom_cpu_path), %l2
  318. sub %l0, %l1, %l1
  319. sub %l0, %l2, %l2
  320. sub %sp, (192 + 128), %sp
  321. stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
  322. mov 1, %l3
  323. stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
  324. stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
  325. stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu"
  326. stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
  327. call %l7
  328. add %sp, (2047 + 128), %o0 ! argument array
  329. ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node
  330. mov (1b - prom_getprop_name), %l1
  331. mov (1b - prom_compatible_name), %l2
  332. mov (1b - prom_cpu_compatible), %l5
  333. sub %l0, %l1, %l1
  334. sub %l0, %l2, %l2
  335. sub %l0, %l5, %l5
  336. /* prom_getproperty(cpu_node, "compatible",
  337. * &prom_cpu_compatible, 64)
  338. */
  339. stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
  340. mov 4, %l3
  341. stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
  342. mov 1, %l3
  343. stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
  344. stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node
  345. stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
  346. stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible
  347. mov 64, %l3
  348. stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
  349. stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
  350. call %l7
  351. add %sp, (2047 + 128), %o0 ! argument array
  352. add %sp, (192 + 128), %sp
  353. sethi %hi(prom_cpu_compatible), %g1
  354. or %g1, %lo(prom_cpu_compatible), %g1
  355. sethi %hi(prom_niagara_prefix), %g7
  356. or %g7, %lo(prom_niagara_prefix), %g7
  357. mov 17, %g3
  358. 90: ldub [%g7], %g2
  359. ldub [%g1], %g4
  360. cmp %g2, %g4
  361. bne,pn %icc, 89f
  362. add %g7, 1, %g7
  363. subcc %g3, 1, %g3
  364. bne,pt %xcc, 90b
  365. add %g1, 1, %g1
  366. ba,pt %xcc, 91f
  367. nop
  368. 89: sethi %hi(prom_cpu_compatible), %g1
  369. or %g1, %lo(prom_cpu_compatible), %g1
  370. sethi %hi(prom_sparc_prefix), %g7
  371. or %g7, %lo(prom_sparc_prefix), %g7
  372. mov 6, %g3
  373. 90: ldub [%g7], %g2
  374. ldub [%g1], %g4
  375. cmp %g2, %g4
  376. bne,pn %icc, 4f
  377. add %g7, 1, %g7
  378. subcc %g3, 1, %g3
  379. bne,pt %xcc, 90b
  380. add %g1, 1, %g1
  381. sethi %hi(prom_cpu_compatible), %g1
  382. or %g1, %lo(prom_cpu_compatible), %g1
  383. ldub [%g1 + 6], %g2
  384. cmp %g2, 'T'
  385. be,pt %xcc, 70f
  386. cmp %g2, 'M'
  387. be,pt %xcc, 70f
  388. cmp %g2, 'S'
  389. bne,pn %xcc, 49f
  390. nop
  391. 70: ldub [%g1 + 7], %g2
  392. cmp %g2, CPU_ID_NIAGARA3
  393. be,pt %xcc, 5f
  394. mov SUN4V_CHIP_NIAGARA3, %g4
  395. cmp %g2, CPU_ID_NIAGARA4
  396. be,pt %xcc, 5f
  397. mov SUN4V_CHIP_NIAGARA4, %g4
  398. cmp %g2, CPU_ID_NIAGARA5
  399. be,pt %xcc, 5f
  400. mov SUN4V_CHIP_NIAGARA5, %g4
  401. cmp %g2, CPU_ID_M6
  402. be,pt %xcc, 5f
  403. mov SUN4V_CHIP_SPARC_M6, %g4
  404. cmp %g2, CPU_ID_M7
  405. be,pt %xcc, 5f
  406. mov SUN4V_CHIP_SPARC_M7, %g4
  407. cmp %g2, CPU_ID_M8
  408. be,pt %xcc, 5f
  409. mov SUN4V_CHIP_SPARC_M8, %g4
  410. cmp %g2, CPU_ID_SONOMA1
  411. be,pt %xcc, 5f
  412. mov SUN4V_CHIP_SPARC_SN, %g4
  413. ba,pt %xcc, 49f
  414. nop
  415. 91: sethi %hi(prom_cpu_compatible), %g1
  416. or %g1, %lo(prom_cpu_compatible), %g1
  417. ldub [%g1 + 17], %g2
  418. cmp %g2, CPU_ID_NIAGARA1
  419. be,pt %xcc, 5f
  420. mov SUN4V_CHIP_NIAGARA1, %g4
  421. cmp %g2, CPU_ID_NIAGARA2
  422. be,pt %xcc, 5f
  423. mov SUN4V_CHIP_NIAGARA2, %g4
  424. 4:
  425. /* Athena */
  426. sethi %hi(prom_cpu_compatible), %g1
  427. or %g1, %lo(prom_cpu_compatible), %g1
  428. sethi %hi(prom_sparc64x_prefix), %g7
  429. or %g7, %lo(prom_sparc64x_prefix), %g7
  430. mov 9, %g3
  431. 41: ldub [%g7], %g2
  432. ldub [%g1], %g4
  433. cmp %g2, %g4
  434. bne,pn %icc, 49f
  435. add %g7, 1, %g7
  436. subcc %g3, 1, %g3
  437. bne,pt %xcc, 41b
  438. add %g1, 1, %g1
  439. ba,pt %xcc, 5f
  440. mov SUN4V_CHIP_SPARC64X, %g4
  441. 49:
  442. mov SUN4V_CHIP_UNKNOWN, %g4
  443. 5: sethi %hi(sun4v_chip_type), %g2
  444. or %g2, %lo(sun4v_chip_type), %g2
  445. stw %g4, [%g2]
  446. 80:
  447. BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
  448. BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
  449. BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
  450. ba,pt %xcc, spitfire_boot
  451. nop
  452. cheetah_plus_boot:
  453. /* Preserve OBP chosen DCU and DCR register settings. */
  454. ba,pt %xcc, cheetah_generic_boot
  455. nop
  456. cheetah_boot:
  457. mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
  458. wr %g1, %asr18
  459. sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
  460. or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
  461. sllx %g7, 32, %g7
  462. or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
  463. stxa %g7, [%g0] ASI_DCU_CONTROL_REG
  464. membar #Sync
  465. cheetah_generic_boot:
  466. mov TSB_EXTENSION_P, %g3
  467. stxa %g0, [%g3] ASI_DMMU
  468. stxa %g0, [%g3] ASI_IMMU
  469. membar #Sync
  470. mov TSB_EXTENSION_S, %g3
  471. stxa %g0, [%g3] ASI_DMMU
  472. membar #Sync
  473. mov TSB_EXTENSION_N, %g3
  474. stxa %g0, [%g3] ASI_DMMU
  475. stxa %g0, [%g3] ASI_IMMU
  476. membar #Sync
  477. ba,a,pt %xcc, jump_to_sun4u_init
  478. spitfire_boot:
  479. /* Typically PROM has already enabled both MMU's and both on-chip
  480. * caches, but we do it here anyway just to be paranoid.
  481. */
  482. mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
  483. stxa %g1, [%g0] ASI_LSU_CONTROL
  484. membar #Sync
  485. jump_to_sun4u_init:
  486. /*
  487. * Make sure we are in privileged mode, have address masking,
  488. * using the ordinary globals and have enabled floating
  489. * point.
  490. *
  491. * Again, typically PROM has left %pil at 13 or similar, and
  492. * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
  493. */
  494. wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
  495. wr %g0, 0, %fprs
  496. set sun4u_init, %g2
  497. jmpl %g2 + %g0, %g0
  498. nop
  499. __REF
  500. sun4u_init:
  501. BRANCH_IF_SUN4V(g1, sun4v_init)
  502. /* Set ctx 0 */
  503. mov PRIMARY_CONTEXT, %g7
  504. stxa %g0, [%g7] ASI_DMMU
  505. membar #Sync
  506. mov SECONDARY_CONTEXT, %g7
  507. stxa %g0, [%g7] ASI_DMMU
  508. membar #Sync
  509. ba,a,pt %xcc, sun4u_continue
  510. sun4v_init:
  511. /* Set ctx 0 */
  512. mov PRIMARY_CONTEXT, %g7
  513. stxa %g0, [%g7] ASI_MMU
  514. membar #Sync
  515. mov SECONDARY_CONTEXT, %g7
  516. stxa %g0, [%g7] ASI_MMU
  517. membar #Sync
  518. ba,a,pt %xcc, niagara_tlb_fixup
  519. sun4u_continue:
  520. BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
  521. ba,a,pt %xcc, spitfire_tlb_fixup
  522. niagara_tlb_fixup:
  523. mov 3, %g2 /* Set TLB type to hypervisor. */
  524. sethi %hi(tlb_type), %g1
  525. stw %g2, [%g1 + %lo(tlb_type)]
  526. /* Patch copy/clear ops. */
  527. sethi %hi(sun4v_chip_type), %g1
  528. lduw [%g1 + %lo(sun4v_chip_type)], %g1
  529. cmp %g1, SUN4V_CHIP_NIAGARA1
  530. be,pt %xcc, niagara_patch
  531. cmp %g1, SUN4V_CHIP_NIAGARA2
  532. be,pt %xcc, niagara2_patch
  533. nop
  534. cmp %g1, SUN4V_CHIP_NIAGARA3
  535. be,pt %xcc, niagara2_patch
  536. nop
  537. cmp %g1, SUN4V_CHIP_NIAGARA4
  538. be,pt %xcc, niagara4_patch
  539. nop
  540. cmp %g1, SUN4V_CHIP_NIAGARA5
  541. be,pt %xcc, niagara4_patch
  542. nop
  543. cmp %g1, SUN4V_CHIP_SPARC_M6
  544. be,pt %xcc, niagara4_patch
  545. nop
  546. cmp %g1, SUN4V_CHIP_SPARC_M7
  547. be,pt %xcc, sparc_m7_patch
  548. nop
  549. cmp %g1, SUN4V_CHIP_SPARC_M8
  550. be,pt %xcc, sparc_m7_patch
  551. nop
  552. cmp %g1, SUN4V_CHIP_SPARC_SN
  553. be,pt %xcc, niagara4_patch
  554. nop
  555. call generic_patch_copyops
  556. nop
  557. call generic_patch_bzero
  558. nop
  559. call generic_patch_pageops
  560. nop
  561. ba,a,pt %xcc, 80f
  562. nop
  563. sparc_m7_patch:
  564. call m7_patch_copyops
  565. nop
  566. call m7_patch_bzero
  567. nop
  568. call m7_patch_pageops
  569. nop
  570. ba,a,pt %xcc, 80f
  571. nop
  572. niagara4_patch:
  573. call niagara4_patch_copyops
  574. nop
  575. call niagara4_patch_bzero
  576. nop
  577. call niagara4_patch_pageops
  578. nop
  579. call niagara4_patch_fls
  580. nop
  581. ba,a,pt %xcc, 80f
  582. nop
  583. niagara2_patch:
  584. call niagara2_patch_copyops
  585. nop
  586. call niagara_patch_bzero
  587. nop
  588. call niagara_patch_pageops
  589. nop
  590. ba,a,pt %xcc, 80f
  591. nop
  592. niagara_patch:
  593. call niagara_patch_copyops
  594. nop
  595. call niagara_patch_bzero
  596. nop
  597. call niagara_patch_pageops
  598. nop
  599. 80:
  600. /* Patch TLB/cache ops. */
  601. call hypervisor_patch_cachetlbops
  602. nop
  603. ba,a,pt %xcc, tlb_fixup_done
  604. cheetah_tlb_fixup:
  605. mov 2, %g2 /* Set TLB type to cheetah+. */
  606. BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
  607. mov 1, %g2 /* Set TLB type to cheetah. */
  608. 1: sethi %hi(tlb_type), %g1
  609. stw %g2, [%g1 + %lo(tlb_type)]
  610. /* Patch copy/page operations to cheetah optimized versions. */
  611. call cheetah_patch_copyops
  612. nop
  613. call cheetah_patch_copy_page
  614. nop
  615. call cheetah_patch_cachetlbops
  616. nop
  617. ba,a,pt %xcc, tlb_fixup_done
  618. spitfire_tlb_fixup:
  619. /* Set TLB type to spitfire. */
  620. mov 0, %g2
  621. sethi %hi(tlb_type), %g1
  622. stw %g2, [%g1 + %lo(tlb_type)]
  623. tlb_fixup_done:
  624. sethi %hi(init_thread_union), %g6
  625. or %g6, %lo(init_thread_union), %g6
  626. ldx [%g6 + TI_TASK], %g4
  627. wr %g0, ASI_P, %asi
  628. mov 1, %g1
  629. sllx %g1, THREAD_SHIFT, %g1
  630. sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
  631. add %g6, %g1, %sp
  632. /* Set per-cpu pointer initially to zero, this makes
  633. * the boot-cpu use the in-kernel-image per-cpu areas
  634. * before setup_per_cpu_area() is invoked.
  635. */
  636. clr %g5
  637. wrpr %g0, 0, %wstate
  638. wrpr %g0, 0x0, %tl
  639. /* Clear the bss */
  640. sethi %hi(__bss_start), %o0
  641. or %o0, %lo(__bss_start), %o0
  642. sethi %hi(_end), %o1
  643. or %o1, %lo(_end), %o1
  644. call __bzero
  645. sub %o1, %o0, %o1
  646. call prom_init
  647. mov %l7, %o0 ! OpenPROM cif handler
  648. /* To create a one-register-window buffer between the kernel's
  649. * initial stack and the last stack frame we use from the firmware,
  650. * do the rest of the boot from a C helper function.
  651. */
  652. call start_early_boot
  653. nop
  654. /* Not reached... */
  655. .previous
  656. /* This is meant to allow the sharing of this code between
  657. * boot processor invocation (via setup_tba() below) and
  658. * secondary processor startup (via trampoline.S). The
  659. * former does use this code, the latter does not yet due
  660. * to some complexities. That should be fixed up at some
  661. * point.
  662. *
  663. * There used to be enormous complexity wrt. transferring
  664. * over from the firmware's trap table to the Linux kernel's.
  665. * For example, there was a chicken & egg problem wrt. building
  666. * the OBP page tables, yet needing to be on the Linux kernel
  667. * trap table (to translate PAGE_OFFSET addresses) in order to
  668. * do that.
  669. *
  670. * We now handle OBP tlb misses differently, via linear lookups
  671. * into the prom_trans[] array. So that specific problem no
  672. * longer exists. Yet, unfortunately there are still some issues
  673. * preventing trampoline.S from using this code... ho hum.
  674. */
  675. .globl setup_trap_table
  676. setup_trap_table:
  677. save %sp, -192, %sp
  678. /* Force interrupts to be disabled. */
  679. rdpr %pstate, %l0
  680. andn %l0, PSTATE_IE, %o1
  681. wrpr %o1, 0x0, %pstate
  682. rdpr %pil, %l1
  683. wrpr %g0, PIL_NORMAL_MAX, %pil
  684. /* Make the firmware call to jump over to the Linux trap table. */
  685. sethi %hi(is_sun4v), %o0
  686. lduw [%o0 + %lo(is_sun4v)], %o0
  687. brz,pt %o0, 1f
  688. nop
  689. TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
  690. add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
  691. stxa %g2, [%g0] ASI_SCRATCHPAD
  692. /* Compute physical address:
  693. *
  694. * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
  695. */
  696. sethi %hi(KERNBASE), %g3
  697. sub %g2, %g3, %g2
  698. sethi %hi(kern_base), %g3
  699. ldx [%g3 + %lo(kern_base)], %g3
  700. add %g2, %g3, %o1
  701. sethi %hi(sparc64_ttable_tl0), %o0
  702. set prom_set_trap_table_name, %g2
  703. stx %g2, [%sp + 2047 + 128 + 0x00]
  704. mov 2, %g2
  705. stx %g2, [%sp + 2047 + 128 + 0x08]
  706. mov 0, %g2
  707. stx %g2, [%sp + 2047 + 128 + 0x10]
  708. stx %o0, [%sp + 2047 + 128 + 0x18]
  709. stx %o1, [%sp + 2047 + 128 + 0x20]
  710. sethi %hi(p1275buf), %g2
  711. or %g2, %lo(p1275buf), %g2
  712. ldx [%g2 + 0x08], %o1
  713. call %o1
  714. add %sp, (2047 + 128), %o0
  715. ba,a,pt %xcc, 2f
  716. 1: sethi %hi(sparc64_ttable_tl0), %o0
  717. set prom_set_trap_table_name, %g2
  718. stx %g2, [%sp + 2047 + 128 + 0x00]
  719. mov 1, %g2
  720. stx %g2, [%sp + 2047 + 128 + 0x08]
  721. mov 0, %g2
  722. stx %g2, [%sp + 2047 + 128 + 0x10]
  723. stx %o0, [%sp + 2047 + 128 + 0x18]
  724. sethi %hi(p1275buf), %g2
  725. or %g2, %lo(p1275buf), %g2
  726. ldx [%g2 + 0x08], %o1
  727. call %o1
  728. add %sp, (2047 + 128), %o0
  729. /* Start using proper page size encodings in ctx register. */
  730. 2: sethi %hi(sparc64_kern_pri_context), %g3
  731. ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
  732. mov PRIMARY_CONTEXT, %g1
  733. 661: stxa %g2, [%g1] ASI_DMMU
  734. .section .sun4v_1insn_patch, "ax"
  735. .word 661b
  736. stxa %g2, [%g1] ASI_MMU
  737. .previous
  738. membar #Sync
  739. BRANCH_IF_SUN4V(o2, 1f)
  740. /* Kill PROM timer */
  741. sethi %hi(0x80000000), %o2
  742. sllx %o2, 32, %o2
  743. wr %o2, 0, %tick_cmpr
  744. BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
  745. ba,a,pt %xcc, 2f
  746. /* Disable STICK_INT interrupts. */
  747. 1:
  748. sethi %hi(0x80000000), %o2
  749. sllx %o2, 32, %o2
  750. wr %o2, %asr25
  751. 2:
  752. wrpr %g0, %g0, %wstate
  753. call init_irqwork_curcpu
  754. nop
  755. /* Now we can restore interrupt state. */
  756. wrpr %l0, 0, %pstate
  757. wrpr %l1, 0x0, %pil
  758. ret
  759. restore
  760. .globl setup_tba
  761. setup_tba:
  762. save %sp, -192, %sp
  763. /* The boot processor is the only cpu which invokes this
  764. * routine, the other cpus set things up via trampoline.S.
  765. * So save the OBP trap table address here.
  766. */
  767. rdpr %tba, %g7
  768. sethi %hi(prom_tba), %o1
  769. or %o1, %lo(prom_tba), %o1
  770. stx %g7, [%o1]
  771. call setup_trap_table
  772. nop
  773. ret
  774. restore
  775. sparc64_boot_end:
  776. #include "etrap_64.S"
  777. #include "rtrap_64.S"
  778. #include "winfixup.S"
  779. #include "fpu_traps.S"
  780. #include "ivec.S"
  781. #include "getsetcc.S"
  782. #include "utrap.S"
  783. #include "spiterrs.S"
  784. #include "cherrs.S"
  785. #include "misctrap.S"
  786. #include "syscalls.S"
  787. #include "helpers.S"
  788. #include "sun4v_tlb_miss.S"
  789. #include "sun4v_mcd.S"
  790. #include "sun4v_ivec.S"
  791. #include "ktlb.S"
  792. #include "tsb.S"
  793. /*
  794. * The following skip makes sure the trap table in ttable.S is aligned
  795. * on a 32K boundary as required by the v9 specs for TBA register.
  796. *
  797. * We align to a 32K boundary, then we have the 32K kernel TSB,
  798. * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
  799. */
  800. 1:
  801. .skip 0x4000 + _start - 1b
  802. ! 0x0000000000408000
  803. .globl swapper_tsb
  804. swapper_tsb:
  805. .skip (32 * 1024)
  806. .globl swapper_4m_tsb
  807. swapper_4m_tsb:
  808. .skip (64 * 1024)
  809. ! 0x0000000000420000
  810. /* Some care needs to be exercised if you try to move the
  811. * location of the trap table relative to other things. For
  812. * one thing there are br* instructions in some of the
  813. * trap table entires which branch back to code in ktlb.S
  814. * Those instructions can only handle a signed 16-bit
  815. * displacement.
  816. *
  817. * There is a binutils bug (bugzilla #4558) which causes
  818. * the relocation overflow checks for such instructions to
  819. * not be done correctly. So bintuils will not notice the
  820. * error and will instead write junk into the relocation and
  821. * you'll have an unbootable kernel.
  822. */
  823. #include "ttable_64.S"
  824. ! 0x0000000000428000
  825. #include "hvcalls.S"
  826. #include "systbls_64.S"
  827. .data
  828. .align 8
  829. .globl prom_tba, tlb_type
  830. prom_tba: .xword 0
  831. tlb_type: .word 0 /* Must NOT end up in BSS */
  832. EXPORT_SYMBOL(tlb_type)
  833. .section ".fixup",#alloc,#execinstr
  834. ENTRY(__retl_efault)
  835. retl
  836. mov -EFAULT, %o0
  837. ENDPROC(__retl_efault)
  838. ENTRY(__retl_o1)
  839. retl
  840. mov %o1, %o0
  841. ENDPROC(__retl_o1)
  842. ENTRY(__retl_o1_asi)
  843. wr %o5, 0x0, %asi
  844. retl
  845. mov %o1, %o0
  846. ENDPROC(__retl_o1_asi)