head_32.S 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * head.S: The initial boot code for the Sparc port of Linux.
  4. *
  5. * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
  6. * Copyright (C) 1995,1999 Pete Zaitcev (zaitcev@yahoo.com)
  7. * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
  8. * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  9. * Copyright (C) 1997 Michael A. Griffith (grif@acm.org)
  10. *
  11. * CompactPCI platform by Eric Brower, 1999.
  12. */
  13. #include <linux/version.h>
  14. #include <linux/init.h>
  15. #include <asm/head.h>
  16. #include <asm/asi.h>
  17. #include <asm/contregs.h>
  18. #include <asm/ptrace.h>
  19. #include <asm/psr.h>
  20. #include <asm/page.h>
  21. #include <asm/kdebug.h>
  22. #include <asm/winmacro.h>
  23. #include <asm/thread_info.h> /* TI_UWINMASK */
  24. #include <asm/errno.h>
  25. #include <asm/pgtable.h> /* PGDIR_SHIFT */
  26. #include <asm/export.h>
  27. .data
  28. /* The following are used with the prom_vector node-ops to figure out
  29. * the cpu-type
  30. */
  31. .align 4
  32. .globl cputypval
  33. cputypval:
  34. .asciz "sun4m"
  35. .ascii " "
  36. /* Tested on SS-5, SS-10 */
  37. .align 4
  38. cputypvar:
  39. .asciz "compatible"
  40. .align 4
  41. notsup:
  42. .asciz "Sparc-Linux sun4/sun4c or MMU-less not supported\n\n"
  43. .align 4
  44. sun4e_notsup:
  45. .asciz "Sparc-Linux sun4e support does not exist\n\n"
  46. .align 4
  47. /* The trap-table - located in the __HEAD section */
  48. #include "ttable_32.S"
  49. .align PAGE_SIZE
  50. /* This was the only reasonable way I could think of to properly align
  51. * these page-table data structures.
  52. */
  53. .globl empty_zero_page
  54. empty_zero_page: .skip PAGE_SIZE
  55. EXPORT_SYMBOL(empty_zero_page)
  56. .global root_flags
  57. .global ram_flags
  58. .global root_dev
  59. .global sparc_ramdisk_image
  60. .global sparc_ramdisk_size
  61. /* This stuff has to be in sync with SILO and other potential boot loaders
  62. * Fields should be kept upward compatible and whenever any change is made,
  63. * HdrS version should be incremented.
  64. */
  65. .ascii "HdrS"
  66. .word LINUX_VERSION_CODE
  67. .half 0x0203 /* HdrS version */
  68. root_flags:
  69. .half 1
  70. root_dev:
  71. .half 0
  72. ram_flags:
  73. .half 0
  74. sparc_ramdisk_image:
  75. .word 0
  76. sparc_ramdisk_size:
  77. .word 0
  78. .word reboot_command
  79. .word 0, 0, 0
  80. .word _end
  81. /* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in
  82. * %g7 and at prom_vector_p. And also quickly check whether we are on
  83. * a v0, v2, or v3 prom.
  84. */
  85. gokernel:
  86. /* Ok, it's nice to know, as early as possible, if we
  87. * are already mapped where we expect to be in virtual
  88. * memory. The Solaris /boot elf format bootloader
  89. * will peek into our elf header and load us where
  90. * we want to be, otherwise we have to re-map.
  91. *
  92. * Some boot loaders don't place the jmp'rs address
  93. * in %o7, so we do a pc-relative call to a local
  94. * label, then see what %o7 has.
  95. */
  96. mov %o7, %g4 ! Save %o7
  97. /* Jump to it, and pray... */
  98. current_pc:
  99. call 1f
  100. nop
  101. 1:
  102. mov %o7, %g3
  103. tst %o0
  104. be no_sun4u_here
  105. mov %g4, %o7 /* Previous %o7. */
  106. mov %o0, %l0 ! stash away romvec
  107. mov %o0, %g7 ! put it here too
  108. mov %o1, %l1 ! stash away debug_vec too
  109. /* Ok, let's check out our run time program counter. */
  110. set current_pc, %g5
  111. cmp %g3, %g5
  112. be already_mapped
  113. nop
  114. /* %l6 will hold the offset we have to subtract
  115. * from absolute symbols in order to access areas
  116. * in our own image. If already mapped this is
  117. * just plain zero, else it is KERNBASE.
  118. */
  119. set KERNBASE, %l6
  120. b copy_prom_lvl14
  121. nop
  122. already_mapped:
  123. mov 0, %l6
  124. /* Copy over the Prom's level 14 clock handler. */
  125. copy_prom_lvl14:
  126. #if 1
  127. /* DJHR
  128. * preserve our linked/calculated instructions
  129. */
  130. set lvl14_save, %g1
  131. set t_irq14, %g3
  132. sub %g1, %l6, %g1 ! translate to physical
  133. sub %g3, %l6, %g3 ! translate to physical
  134. ldd [%g3], %g4
  135. std %g4, [%g1]
  136. ldd [%g3+8], %g4
  137. std %g4, [%g1+8]
  138. #endif
  139. rd %tbr, %g1
  140. andn %g1, 0xfff, %g1 ! proms trap table base
  141. or %g0, (0x1e<<4), %g2 ! offset to lvl14 intr
  142. or %g1, %g2, %g2
  143. set t_irq14, %g3
  144. sub %g3, %l6, %g3
  145. ldd [%g2], %g4
  146. std %g4, [%g3]
  147. ldd [%g2 + 0x8], %g4
  148. std %g4, [%g3 + 0x8] ! Copy proms handler
  149. /* DON'T TOUCH %l0 thru %l5 in these remapping routines,
  150. * we need their values afterwards!
  151. */
  152. /* Now check whether we are already mapped, if we
  153. * are we can skip all this garbage coming up.
  154. */
  155. copy_prom_done:
  156. cmp %l6, 0
  157. be go_to_highmem ! this will be a nop then
  158. nop
  159. /* Validate that we are in fact running on an
  160. * SRMMU based cpu.
  161. */
  162. set 0x4000, %g6
  163. cmp %g7, %g6
  164. bne not_a_sun4
  165. nop
  166. halt_notsup:
  167. ld [%g7 + 0x68], %o1
  168. set notsup, %o0
  169. sub %o0, %l6, %o0
  170. call %o1
  171. nop
  172. ba halt_me
  173. nop
  174. not_a_sun4:
  175. /* It looks like this is a machine we support.
  176. * Now find out what MMU we are dealing with
  177. * LEON - identified by the psr.impl field
  178. * Viking - identified by the psr.impl field
  179. * In all other cases a sun4m srmmu.
  180. * We check that the MMU is enabled in all cases.
  181. */
  182. /* Check if this is a LEON CPU */
  183. rd %psr, %g3
  184. srl %g3, PSR_IMPL_SHIFT, %g3
  185. and %g3, PSR_IMPL_SHIFTED_MASK, %g3
  186. cmp %g3, PSR_IMPL_LEON
  187. be leon_remap /* It is a LEON - jump */
  188. nop
  189. /* Sanity-check, is MMU enabled */
  190. lda [%g0] ASI_M_MMUREGS, %g1
  191. andcc %g1, 1, %g0
  192. be halt_notsup
  193. nop
  194. /* Check for a viking (TI) module. */
  195. cmp %g3, PSR_IMPL_TI
  196. bne srmmu_not_viking
  197. nop
  198. /* Figure out what kind of viking we are on.
  199. * We need to know if we have to play with the
  200. * AC bit and disable traps or not.
  201. */
  202. /* I've only seen MicroSparc's on SparcClassics with this
  203. * bit set.
  204. */
  205. set 0x800, %g2
  206. lda [%g0] ASI_M_MMUREGS, %g3 ! peek in the control reg
  207. and %g2, %g3, %g3
  208. subcc %g3, 0x0, %g0
  209. bnz srmmu_not_viking ! is in mbus mode
  210. nop
  211. rd %psr, %g3 ! DO NOT TOUCH %g3
  212. andn %g3, PSR_ET, %g2
  213. wr %g2, 0x0, %psr
  214. WRITE_PAUSE
  215. /* Get context table pointer, then convert to
  216. * a physical address, which is 36 bits.
  217. */
  218. set AC_M_CTPR, %g4
  219. lda [%g4] ASI_M_MMUREGS, %g4
  220. sll %g4, 0x4, %g4 ! We use this below
  221. ! DO NOT TOUCH %g4
  222. /* Set the AC bit in the Viking's MMU control reg. */
  223. lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5
  224. set 0x8000, %g6 ! AC bit mask
  225. or %g5, %g6, %g6 ! Or it in...
  226. sta %g6, [%g0] ASI_M_MMUREGS ! Close your eyes...
  227. /* Grrr, why does it seem like every other load/store
  228. * on the sun4m is in some ASI space...
  229. * Fine with me, let's get the pointer to the level 1
  230. * page table directory and fetch its entry.
  231. */
  232. lda [%g4] ASI_M_BYPASS, %o1 ! This is a level 1 ptr
  233. srl %o1, 0x4, %o1 ! Clear low 4 bits
  234. sll %o1, 0x8, %o1 ! Make physical
  235. /* Ok, pull in the PTD. */
  236. lda [%o1] ASI_M_BYPASS, %o2 ! This is the 0x0 16MB pgd
  237. /* Calculate to KERNBASE entry. */
  238. add %o1, KERNBASE >> (PGDIR_SHIFT - 2), %o3
  239. /* Poke the entry into the calculated address. */
  240. sta %o2, [%o3] ASI_M_BYPASS
  241. /* I don't get it Sun, if you engineered all these
  242. * boot loaders and the PROM (thank you for the debugging
  243. * features btw) why did you not have them load kernel
  244. * images up in high address space, since this is necessary
  245. * for ABI compliance anyways? Does this low-mapping provide
  246. * enhanced interoperability?
  247. *
  248. * "The PROM is the computer."
  249. */
  250. /* Ok, restore the MMU control register we saved in %g5 */
  251. sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch
  252. /* Turn traps back on. We saved it in %g3 earlier. */
  253. wr %g3, 0x0, %psr ! tick tock, tick tock
  254. /* Now we burn precious CPU cycles due to bad engineering. */
  255. WRITE_PAUSE
  256. /* Wow, all that just to move a 32-bit value from one
  257. * place to another... Jump to high memory.
  258. */
  259. b go_to_highmem
  260. nop
  261. srmmu_not_viking:
  262. /* This works on viking's in Mbus mode and all
  263. * other MBUS modules. It is virtually the same as
  264. * the above madness sans turning traps off and flipping
  265. * the AC bit.
  266. */
  267. set AC_M_CTPR, %g1
  268. lda [%g1] ASI_M_MMUREGS, %g1 ! get ctx table ptr
  269. sll %g1, 0x4, %g1 ! make physical addr
  270. lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table
  271. srl %g1, 0x4, %g1
  272. sll %g1, 0x8, %g1 ! make phys addr for l1 tbl
  273. lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
  274. add %g1, KERNBASE >> (PGDIR_SHIFT - 2), %g3
  275. sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
  276. b go_to_highmem
  277. nop ! wheee....
  278. leon_remap:
  279. /* Sanity-check, is MMU enabled */
  280. lda [%g0] ASI_LEON_MMUREGS, %g1
  281. andcc %g1, 1, %g0
  282. be halt_notsup
  283. nop
  284. /* Same code as in the srmmu_not_viking case,
  285. * with the LEON ASI for mmuregs
  286. */
  287. set AC_M_CTPR, %g1
  288. lda [%g1] ASI_LEON_MMUREGS, %g1 ! get ctx table ptr
  289. sll %g1, 0x4, %g1 ! make physical addr
  290. lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table
  291. srl %g1, 0x4, %g1
  292. sll %g1, 0x8, %g1 ! make phys addr for l1 tbl
  293. lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
  294. add %g1, KERNBASE >> (PGDIR_SHIFT - 2), %g3
  295. sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
  296. b go_to_highmem
  297. nop ! wheee....
  298. /* Now do a non-relative jump so that PC is in high-memory */
  299. go_to_highmem:
  300. set execute_in_high_mem, %g1
  301. jmpl %g1, %g0
  302. nop
  303. /* The code above should be at beginning and we have to take care about
  304. * short jumps, as branching to .init.text section from .text is usually
  305. * impossible */
  306. __INIT
  307. /* Acquire boot time privileged register values, this will help debugging.
  308. * I figure out and store nwindows and nwindowsm1 later on.
  309. */
  310. execute_in_high_mem:
  311. mov %l0, %o0 ! put back romvec
  312. mov %l1, %o1 ! and debug_vec
  313. sethi %hi(prom_vector_p), %g1
  314. st %o0, [%g1 + %lo(prom_vector_p)]
  315. sethi %hi(linux_dbvec), %g1
  316. st %o1, [%g1 + %lo(linux_dbvec)]
  317. /* Get the machine type via the romvec
  318. * getprops node operation
  319. */
  320. add %g7, 0x1c, %l1
  321. ld [%l1], %l0
  322. ld [%l0], %l0
  323. call %l0
  324. or %g0, %g0, %o0 ! next_node(0) = first_node
  325. or %o0, %g0, %g6
  326. sethi %hi(cputypvar), %o1 ! First node has cpu-arch
  327. or %o1, %lo(cputypvar), %o1
  328. sethi %hi(cputypval), %o2 ! information, the string
  329. or %o2, %lo(cputypval), %o2
  330. ld [%l1], %l0 ! 'compatible' tells
  331. ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where
  332. call %l0 ! x is one of 'm', 'd' or 'e'.
  333. nop ! %o2 holds pointer
  334. ! to a buf where above string
  335. ! will get stored by the prom.
  336. /* Check value of "compatible" property.
  337. * "value" => "model"
  338. * leon => sparc_leon
  339. * sun4m => sun4m
  340. * sun4s => sun4m
  341. * sun4d => sun4d
  342. * sun4e => "no_sun4e_here"
  343. * '*' => "no_sun4u_here"
  344. * Check single letters only
  345. */
  346. set cputypval, %o2
  347. /* If cputypval[0] == 'l' (lower case letter L) this is leon */
  348. ldub [%o2], %l1
  349. cmp %l1, 'l'
  350. be leon_init
  351. nop
  352. /* Check cputypval[4] to find the sun model */
  353. ldub [%o2 + 0x4], %l1
  354. cmp %l1, 'm'
  355. be sun4m_init
  356. cmp %l1, 's'
  357. be sun4m_init
  358. cmp %l1, 'd'
  359. be sun4d_init
  360. cmp %l1, 'e'
  361. be no_sun4e_here ! Could be a sun4e.
  362. nop
  363. b no_sun4u_here ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
  364. nop
  365. leon_init:
  366. /* LEON CPU - set boot_cpu_id */
  367. sethi %hi(boot_cpu_id), %g2 ! boot-cpu index
  368. #ifdef CONFIG_SMP
  369. ldub [%g2 + %lo(boot_cpu_id)], %g1
  370. cmp %g1, 0xff ! unset means first CPU
  371. bne leon_smp_cpu_startup ! continue only with master
  372. nop
  373. #endif
  374. /* Get CPU-ID from most significant 4-bit of ASR17 */
  375. rd %asr17, %g1
  376. srl %g1, 28, %g1
  377. /* Update boot_cpu_id only on boot cpu */
  378. stub %g1, [%g2 + %lo(boot_cpu_id)]
  379. ba continue_boot
  380. nop
  381. /* CPUID in bootbus can be found at PA 0xff0140000 */
  382. #define SUN4D_BOOTBUS_CPUID 0xf0140000
  383. sun4d_init:
  384. /* Need to patch call to handler_irq */
  385. set patch_handler_irq, %g4
  386. set sun4d_handler_irq, %g5
  387. sethi %hi(0x40000000), %g3 ! call
  388. sub %g5, %g4, %g5
  389. srl %g5, 2, %g5
  390. or %g5, %g3, %g5
  391. st %g5, [%g4]
  392. #ifdef CONFIG_SMP
  393. /* Get our CPU id out of bootbus */
  394. set SUN4D_BOOTBUS_CPUID, %g3
  395. lduba [%g3] ASI_M_CTL, %g3
  396. and %g3, 0xf8, %g3
  397. srl %g3, 3, %g4
  398. sta %g4, [%g0] ASI_M_VIKING_TMP1
  399. sethi %hi(boot_cpu_id), %g5
  400. stb %g4, [%g5 + %lo(boot_cpu_id)]
  401. #endif
  402. /* Fall through to sun4m_init */
  403. sun4m_init:
  404. /* Ok, the PROM could have done funny things and apple cider could still
  405. * be sitting in the fault status/address registers. Read them all to
  406. * clear them so we don't get magic faults later on.
  407. */
  408. /* This sucks, apparently this makes Vikings call prom panic, will fix later */
  409. 2:
  410. rd %psr, %o1
  411. srl %o1, PSR_IMPL_SHIFT, %o1 ! Get a type of the CPU
  412. subcc %o1, PSR_IMPL_TI, %g0 ! TI: Viking or MicroSPARC
  413. be continue_boot
  414. nop
  415. set AC_M_SFSR, %o0
  416. lda [%o0] ASI_M_MMUREGS, %g0
  417. set AC_M_SFAR, %o0
  418. lda [%o0] ASI_M_MMUREGS, %g0
  419. /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
  420. subcc %o1, 0, %g0
  421. be continue_boot
  422. nop
  423. set AC_M_AFSR, %o0
  424. lda [%o0] ASI_M_MMUREGS, %g0
  425. set AC_M_AFAR, %o0
  426. lda [%o0] ASI_M_MMUREGS, %g0
  427. nop
  428. continue_boot:
  429. /* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
  430. * show-time!
  431. */
  432. /* Turn on Supervisor, EnableFloating, and all the PIL bits.
  433. * Also puts us in register window zero with traps off.
  434. */
  435. set (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
  436. wr %g2, 0x0, %psr
  437. WRITE_PAUSE
  438. /* I want a kernel stack NOW! */
  439. set init_thread_union, %g1
  440. set (THREAD_SIZE - STACKFRAME_SZ), %g2
  441. add %g1, %g2, %sp
  442. mov 0, %fp /* And for good luck */
  443. /* Zero out our BSS section. */
  444. set __bss_start , %o0 ! First address of BSS
  445. set _end , %o1 ! Last address of BSS
  446. add %o0, 0x1, %o0
  447. 1:
  448. stb %g0, [%o0]
  449. subcc %o0, %o1, %g0
  450. bl 1b
  451. add %o0, 0x1, %o0
  452. /* If boot_cpu_id has not been setup by machine specific
  453. * init-code above we default it to zero.
  454. */
  455. sethi %hi(boot_cpu_id), %g2
  456. ldub [%g2 + %lo(boot_cpu_id)], %g3
  457. cmp %g3, 0xff
  458. bne 1f
  459. nop
  460. mov %g0, %g3
  461. stub %g3, [%g2 + %lo(boot_cpu_id)]
  462. 1: sll %g3, 2, %g3
  463. /* Initialize the uwinmask value for init task just in case.
  464. * But first make current_set[boot_cpu_id] point to something useful.
  465. */
  466. set init_thread_union, %g6
  467. set current_set, %g2
  468. #ifdef CONFIG_SMP
  469. st %g6, [%g2]
  470. add %g2, %g3, %g2
  471. #endif
  472. st %g6, [%g2]
  473. st %g0, [%g6 + TI_UWINMASK]
  474. /* Compute NWINDOWS and stash it away. Now uses %wim trick explained
  475. * in the V8 manual. Ok, this method seems to work, Sparc is cool...
  476. * No, it doesn't work, have to play the save/readCWP/restore trick.
  477. */
  478. wr %g0, 0x0, %wim ! so we do not get a trap
  479. WRITE_PAUSE
  480. save
  481. rd %psr, %g3
  482. restore
  483. and %g3, 0x1f, %g3
  484. add %g3, 0x1, %g3
  485. mov 2, %g1
  486. wr %g1, 0x0, %wim ! make window 1 invalid
  487. WRITE_PAUSE
  488. cmp %g3, 0x7
  489. bne 2f
  490. nop
  491. /* Adjust our window handling routines to
  492. * do things correctly on 7 window Sparcs.
  493. */
  494. #define PATCH_INSN(src, dest) \
  495. set src, %g5; \
  496. set dest, %g2; \
  497. ld [%g5], %g4; \
  498. st %g4, [%g2];
  499. /* Patch for window spills... */
  500. PATCH_INSN(spnwin_patch1_7win, spnwin_patch1)
  501. PATCH_INSN(spnwin_patch2_7win, spnwin_patch2)
  502. PATCH_INSN(spnwin_patch3_7win, spnwin_patch3)
  503. /* Patch for window fills... */
  504. PATCH_INSN(fnwin_patch1_7win, fnwin_patch1)
  505. PATCH_INSN(fnwin_patch2_7win, fnwin_patch2)
  506. /* Patch for trap entry setup... */
  507. PATCH_INSN(tsetup_7win_patch1, tsetup_patch1)
  508. PATCH_INSN(tsetup_7win_patch2, tsetup_patch2)
  509. PATCH_INSN(tsetup_7win_patch3, tsetup_patch3)
  510. PATCH_INSN(tsetup_7win_patch4, tsetup_patch4)
  511. PATCH_INSN(tsetup_7win_patch5, tsetup_patch5)
  512. PATCH_INSN(tsetup_7win_patch6, tsetup_patch6)
  513. /* Patch for returning from traps... */
  514. PATCH_INSN(rtrap_7win_patch1, rtrap_patch1)
  515. PATCH_INSN(rtrap_7win_patch2, rtrap_patch2)
  516. PATCH_INSN(rtrap_7win_patch3, rtrap_patch3)
  517. PATCH_INSN(rtrap_7win_patch4, rtrap_patch4)
  518. PATCH_INSN(rtrap_7win_patch5, rtrap_patch5)
  519. /* Patch for killing user windows from the register file. */
  520. PATCH_INSN(kuw_patch1_7win, kuw_patch1)
  521. /* Now patch the kernel window flush sequences.
  522. * This saves 2 traps on every switch and fork.
  523. */
  524. set 0x01000000, %g4
  525. set flush_patch_one, %g5
  526. st %g4, [%g5 + 0x18]
  527. st %g4, [%g5 + 0x1c]
  528. set flush_patch_two, %g5
  529. st %g4, [%g5 + 0x18]
  530. st %g4, [%g5 + 0x1c]
  531. set flush_patch_three, %g5
  532. st %g4, [%g5 + 0x18]
  533. st %g4, [%g5 + 0x1c]
  534. set flush_patch_four, %g5
  535. st %g4, [%g5 + 0x18]
  536. st %g4, [%g5 + 0x1c]
  537. set flush_patch_exception, %g5
  538. st %g4, [%g5 + 0x18]
  539. st %g4, [%g5 + 0x1c]
  540. set flush_patch_switch, %g5
  541. st %g4, [%g5 + 0x18]
  542. st %g4, [%g5 + 0x1c]
  543. 2:
  544. sethi %hi(nwindows), %g4
  545. st %g3, [%g4 + %lo(nwindows)] ! store final value
  546. sub %g3, 0x1, %g3
  547. sethi %hi(nwindowsm1), %g4
  548. st %g3, [%g4 + %lo(nwindowsm1)]
  549. /* Here we go, start using Linux's trap table... */
  550. set trapbase, %g3
  551. wr %g3, 0x0, %tbr
  552. WRITE_PAUSE
  553. /* Finally, turn on traps so that we can call c-code. */
  554. rd %psr, %g3
  555. wr %g3, 0x0, %psr
  556. WRITE_PAUSE
  557. wr %g3, PSR_ET, %psr
  558. WRITE_PAUSE
  559. /* Call sparc32_start_kernel(struct linux_romvec *rp) */
  560. sethi %hi(prom_vector_p), %g5
  561. ld [%g5 + %lo(prom_vector_p)], %o0
  562. call sparc32_start_kernel
  563. nop
  564. /* We should not get here. */
  565. call halt_me
  566. nop
  567. no_sun4e_here:
  568. ld [%g7 + 0x68], %o1
  569. set sun4e_notsup, %o0
  570. call %o1
  571. nop
  572. b halt_me
  573. nop
  574. __INITDATA
  575. sun4u_1:
  576. .asciz "finddevice"
  577. .align 4
  578. sun4u_2:
  579. .asciz "/chosen"
  580. .align 4
  581. sun4u_3:
  582. .asciz "getprop"
  583. .align 4
  584. sun4u_4:
  585. .asciz "stdout"
  586. .align 4
  587. sun4u_5:
  588. .asciz "write"
  589. .align 4
  590. sun4u_6:
  591. .asciz "\n\rOn sun4u you have to use sparc64 kernel\n\rand not a sparc32 version\n\r\n\r"
  592. sun4u_6e:
  593. .align 4
  594. sun4u_7:
  595. .asciz "exit"
  596. .align 8
  597. sun4u_a1:
  598. .word 0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0
  599. sun4u_r1:
  600. .word 0
  601. sun4u_a2:
  602. .word 0, sun4u_3, 0, 4, 0, 1, 0
  603. sun4u_i2:
  604. .word 0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0
  605. sun4u_r2:
  606. .word 0
  607. sun4u_a3:
  608. .word 0, sun4u_5, 0, 3, 0, 1, 0
  609. sun4u_i3:
  610. .word 0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0
  611. sun4u_r3:
  612. .word 0
  613. sun4u_a4:
  614. .word 0, sun4u_7, 0, 0, 0, 0
  615. sun4u_r4:
  616. __INIT
  617. no_sun4u_here:
  618. set sun4u_a1, %o0
  619. set current_pc, %l2
  620. cmp %l2, %g3
  621. be 1f
  622. mov %o4, %l0
  623. sub %g3, %l2, %l6
  624. add %o0, %l6, %o0
  625. mov %o0, %l4
  626. mov sun4u_r4 - sun4u_a1, %l3
  627. ld [%l4], %l5
  628. 2:
  629. add %l4, 4, %l4
  630. cmp %l5, %l2
  631. add %l5, %l6, %l5
  632. bgeu,a 3f
  633. st %l5, [%l4 - 4]
  634. 3:
  635. subcc %l3, 4, %l3
  636. bne 2b
  637. ld [%l4], %l5
  638. 1:
  639. call %l0
  640. mov %o0, %l1
  641. ld [%l1 + (sun4u_r1 - sun4u_a1)], %o1
  642. add %l1, (sun4u_a2 - sun4u_a1), %o0
  643. call %l0
  644. st %o1, [%o0 + (sun4u_i2 - sun4u_a2)]
  645. ld [%l1 + (sun4u_1 - sun4u_a1)], %o1
  646. add %l1, (sun4u_a3 - sun4u_a1), %o0
  647. call %l0
  648. st %o1, [%o0 + (sun4u_i3 - sun4u_a3)]
  649. call %l0
  650. add %l1, (sun4u_a4 - sun4u_a1), %o0
  651. /* Not reached */
  652. halt_me:
  653. ld [%g7 + 0x74], %o0
  654. call %o0 ! Get us out of here...
  655. nop ! Apparently Solaris is better.
  656. /* Ok, now we continue in the .data/.text sections */
  657. .data
  658. .align 4
  659. /*
  660. * Fill up the prom vector, note in particular the kind first element,
  661. * no joke. I don't need all of them in here as the entire prom vector
  662. * gets initialized in c-code so all routines can use it.
  663. */
  664. prom_vector_p:
  665. .word 0
  666. /* We calculate the following at boot time, window fills/spills and trap entry
  667. * code uses these to keep track of the register windows.
  668. */
  669. .align 4
  670. .globl nwindows
  671. .globl nwindowsm1
  672. nwindows:
  673. .word 8
  674. nwindowsm1:
  675. .word 7
  676. /* Boot time debugger vector value. We need this later on. */
  677. .align 4
  678. .globl linux_dbvec
  679. linux_dbvec:
  680. .word 0
  681. .word 0
  682. .align 8
  683. .globl lvl14_save
  684. lvl14_save:
  685. .word 0
  686. .word 0
  687. .word 0
  688. .word 0
  689. .word t_irq14