ebus.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* ebus.c: EBUS DMA library code.
  3. *
  4. * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
  5. * Copyright (C) 1999 David S. Miller (davem@redhat.com)
  6. */
  7. #include <linux/export.h>
  8. #include <linux/kernel.h>
  9. #include <linux/types.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/delay.h>
  12. #include <asm/ebus_dma.h>
  13. #include <asm/io.h>
  14. #define EBDMA_CSR 0x00UL /* Control/Status */
  15. #define EBDMA_ADDR 0x04UL /* DMA Address */
  16. #define EBDMA_COUNT 0x08UL /* DMA Count */
  17. #define EBDMA_CSR_INT_PEND 0x00000001
  18. #define EBDMA_CSR_ERR_PEND 0x00000002
  19. #define EBDMA_CSR_DRAIN 0x00000004
  20. #define EBDMA_CSR_INT_EN 0x00000010
  21. #define EBDMA_CSR_RESET 0x00000080
  22. #define EBDMA_CSR_WRITE 0x00000100
  23. #define EBDMA_CSR_EN_DMA 0x00000200
  24. #define EBDMA_CSR_CYC_PEND 0x00000400
  25. #define EBDMA_CSR_DIAG_RD_DONE 0x00000800
  26. #define EBDMA_CSR_DIAG_WR_DONE 0x00001000
  27. #define EBDMA_CSR_EN_CNT 0x00002000
  28. #define EBDMA_CSR_TC 0x00004000
  29. #define EBDMA_CSR_DIS_CSR_DRN 0x00010000
  30. #define EBDMA_CSR_BURST_SZ_MASK 0x000c0000
  31. #define EBDMA_CSR_BURST_SZ_1 0x00080000
  32. #define EBDMA_CSR_BURST_SZ_4 0x00000000
  33. #define EBDMA_CSR_BURST_SZ_8 0x00040000
  34. #define EBDMA_CSR_BURST_SZ_16 0x000c0000
  35. #define EBDMA_CSR_DIAG_EN 0x00100000
  36. #define EBDMA_CSR_DIS_ERR_PEND 0x00400000
  37. #define EBDMA_CSR_TCI_DIS 0x00800000
  38. #define EBDMA_CSR_EN_NEXT 0x01000000
  39. #define EBDMA_CSR_DMA_ON 0x02000000
  40. #define EBDMA_CSR_A_LOADED 0x04000000
  41. #define EBDMA_CSR_NA_LOADED 0x08000000
  42. #define EBDMA_CSR_DEV_ID_MASK 0xf0000000
  43. #define EBUS_DMA_RESET_TIMEOUT 10000
  44. static void __ebus_dma_reset(struct ebus_dma_info *p, int no_drain)
  45. {
  46. int i;
  47. u32 val = 0;
  48. writel(EBDMA_CSR_RESET, p->regs + EBDMA_CSR);
  49. udelay(1);
  50. if (no_drain)
  51. return;
  52. for (i = EBUS_DMA_RESET_TIMEOUT; i > 0; i--) {
  53. val = readl(p->regs + EBDMA_CSR);
  54. if (!(val & (EBDMA_CSR_DRAIN | EBDMA_CSR_CYC_PEND)))
  55. break;
  56. udelay(10);
  57. }
  58. }
  59. static irqreturn_t ebus_dma_irq(int irq, void *dev_id)
  60. {
  61. struct ebus_dma_info *p = dev_id;
  62. unsigned long flags;
  63. u32 csr = 0;
  64. spin_lock_irqsave(&p->lock, flags);
  65. csr = readl(p->regs + EBDMA_CSR);
  66. writel(csr, p->regs + EBDMA_CSR);
  67. spin_unlock_irqrestore(&p->lock, flags);
  68. if (csr & EBDMA_CSR_ERR_PEND) {
  69. printk(KERN_CRIT "ebus_dma(%s): DMA error!\n", p->name);
  70. p->callback(p, EBUS_DMA_EVENT_ERROR, p->client_cookie);
  71. return IRQ_HANDLED;
  72. } else if (csr & EBDMA_CSR_INT_PEND) {
  73. p->callback(p,
  74. (csr & EBDMA_CSR_TC) ?
  75. EBUS_DMA_EVENT_DMA : EBUS_DMA_EVENT_DEVICE,
  76. p->client_cookie);
  77. return IRQ_HANDLED;
  78. }
  79. return IRQ_NONE;
  80. }
  81. int ebus_dma_register(struct ebus_dma_info *p)
  82. {
  83. u32 csr;
  84. if (!p->regs)
  85. return -EINVAL;
  86. if (p->flags & ~(EBUS_DMA_FLAG_USE_EBDMA_HANDLER |
  87. EBUS_DMA_FLAG_TCI_DISABLE))
  88. return -EINVAL;
  89. if ((p->flags & EBUS_DMA_FLAG_USE_EBDMA_HANDLER) && !p->callback)
  90. return -EINVAL;
  91. if (!strlen(p->name))
  92. return -EINVAL;
  93. __ebus_dma_reset(p, 1);
  94. csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT;
  95. if (p->flags & EBUS_DMA_FLAG_TCI_DISABLE)
  96. csr |= EBDMA_CSR_TCI_DIS;
  97. writel(csr, p->regs + EBDMA_CSR);
  98. return 0;
  99. }
  100. EXPORT_SYMBOL(ebus_dma_register);
  101. int ebus_dma_irq_enable(struct ebus_dma_info *p, int on)
  102. {
  103. unsigned long flags;
  104. u32 csr;
  105. if (on) {
  106. if (p->flags & EBUS_DMA_FLAG_USE_EBDMA_HANDLER) {
  107. if (request_irq(p->irq, ebus_dma_irq, IRQF_SHARED, p->name, p))
  108. return -EBUSY;
  109. }
  110. spin_lock_irqsave(&p->lock, flags);
  111. csr = readl(p->regs + EBDMA_CSR);
  112. csr |= EBDMA_CSR_INT_EN;
  113. writel(csr, p->regs + EBDMA_CSR);
  114. spin_unlock_irqrestore(&p->lock, flags);
  115. } else {
  116. spin_lock_irqsave(&p->lock, flags);
  117. csr = readl(p->regs + EBDMA_CSR);
  118. csr &= ~EBDMA_CSR_INT_EN;
  119. writel(csr, p->regs + EBDMA_CSR);
  120. spin_unlock_irqrestore(&p->lock, flags);
  121. if (p->flags & EBUS_DMA_FLAG_USE_EBDMA_HANDLER) {
  122. free_irq(p->irq, p);
  123. }
  124. }
  125. return 0;
  126. }
  127. EXPORT_SYMBOL(ebus_dma_irq_enable);
  128. void ebus_dma_unregister(struct ebus_dma_info *p)
  129. {
  130. unsigned long flags;
  131. u32 csr;
  132. int irq_on = 0;
  133. spin_lock_irqsave(&p->lock, flags);
  134. csr = readl(p->regs + EBDMA_CSR);
  135. if (csr & EBDMA_CSR_INT_EN) {
  136. csr &= ~EBDMA_CSR_INT_EN;
  137. writel(csr, p->regs + EBDMA_CSR);
  138. irq_on = 1;
  139. }
  140. spin_unlock_irqrestore(&p->lock, flags);
  141. if (irq_on)
  142. free_irq(p->irq, p);
  143. }
  144. EXPORT_SYMBOL(ebus_dma_unregister);
  145. int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr, size_t len)
  146. {
  147. unsigned long flags;
  148. u32 csr;
  149. int err;
  150. if (len >= (1 << 24))
  151. return -EINVAL;
  152. spin_lock_irqsave(&p->lock, flags);
  153. csr = readl(p->regs + EBDMA_CSR);
  154. err = -EINVAL;
  155. if (!(csr & EBDMA_CSR_EN_DMA))
  156. goto out;
  157. err = -EBUSY;
  158. if (csr & EBDMA_CSR_NA_LOADED)
  159. goto out;
  160. writel(len, p->regs + EBDMA_COUNT);
  161. writel(bus_addr, p->regs + EBDMA_ADDR);
  162. err = 0;
  163. out:
  164. spin_unlock_irqrestore(&p->lock, flags);
  165. return err;
  166. }
  167. EXPORT_SYMBOL(ebus_dma_request);
  168. void ebus_dma_prepare(struct ebus_dma_info *p, int write)
  169. {
  170. unsigned long flags;
  171. u32 csr;
  172. spin_lock_irqsave(&p->lock, flags);
  173. __ebus_dma_reset(p, 0);
  174. csr = (EBDMA_CSR_INT_EN |
  175. EBDMA_CSR_EN_CNT |
  176. EBDMA_CSR_BURST_SZ_16 |
  177. EBDMA_CSR_EN_NEXT);
  178. if (write)
  179. csr |= EBDMA_CSR_WRITE;
  180. if (p->flags & EBUS_DMA_FLAG_TCI_DISABLE)
  181. csr |= EBDMA_CSR_TCI_DIS;
  182. writel(csr, p->regs + EBDMA_CSR);
  183. spin_unlock_irqrestore(&p->lock, flags);
  184. }
  185. EXPORT_SYMBOL(ebus_dma_prepare);
  186. unsigned int ebus_dma_residue(struct ebus_dma_info *p)
  187. {
  188. return readl(p->regs + EBDMA_COUNT);
  189. }
  190. EXPORT_SYMBOL(ebus_dma_residue);
  191. unsigned int ebus_dma_addr(struct ebus_dma_info *p)
  192. {
  193. return readl(p->regs + EBDMA_ADDR);
  194. }
  195. EXPORT_SYMBOL(ebus_dma_addr);
  196. void ebus_dma_enable(struct ebus_dma_info *p, int on)
  197. {
  198. unsigned long flags;
  199. u32 orig_csr, csr;
  200. spin_lock_irqsave(&p->lock, flags);
  201. orig_csr = csr = readl(p->regs + EBDMA_CSR);
  202. if (on)
  203. csr |= EBDMA_CSR_EN_DMA;
  204. else
  205. csr &= ~EBDMA_CSR_EN_DMA;
  206. if ((orig_csr & EBDMA_CSR_EN_DMA) !=
  207. (csr & EBDMA_CSR_EN_DMA))
  208. writel(csr, p->regs + EBDMA_CSR);
  209. spin_unlock_irqrestore(&p->lock, flags);
  210. }
  211. EXPORT_SYMBOL(ebus_dma_enable);