chmc.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* chmc.c: Driver for UltraSPARC-III memory controller.
  3. *
  4. * Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net)
  5. */
  6. #include <linux/module.h>
  7. #include <linux/kernel.h>
  8. #include <linux/types.h>
  9. #include <linux/slab.h>
  10. #include <linux/list.h>
  11. #include <linux/string.h>
  12. #include <linux/sched.h>
  13. #include <linux/smp.h>
  14. #include <linux/errno.h>
  15. #include <linux/init.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <asm/spitfire.h>
  19. #include <asm/chmctrl.h>
  20. #include <asm/cpudata.h>
  21. #include <asm/oplib.h>
  22. #include <asm/prom.h>
  23. #include <asm/head.h>
  24. #include <asm/io.h>
  25. #include <asm/memctrl.h>
  26. #define DRV_MODULE_NAME "chmc"
  27. #define PFX DRV_MODULE_NAME ": "
  28. #define DRV_MODULE_VERSION "0.2"
  29. MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  30. MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
  31. MODULE_LICENSE("GPL");
  32. MODULE_VERSION(DRV_MODULE_VERSION);
  33. static int mc_type;
  34. #define MC_TYPE_SAFARI 1
  35. #define MC_TYPE_JBUS 2
  36. static dimm_printer_t us3mc_dimm_printer;
  37. #define CHMCTRL_NDGRPS 2
  38. #define CHMCTRL_NDIMMS 4
  39. #define CHMC_DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
  40. /* OBP memory-layout property format. */
  41. struct chmc_obp_map {
  42. unsigned char dimm_map[144];
  43. unsigned char pin_map[576];
  44. };
  45. #define DIMM_LABEL_SZ 8
  46. struct chmc_obp_mem_layout {
  47. /* One max 8-byte string label per DIMM. Usually
  48. * this matches the label on the motherboard where
  49. * that DIMM resides.
  50. */
  51. char dimm_labels[CHMC_DIMMS_PER_MC][DIMM_LABEL_SZ];
  52. /* If symmetric use map[0], else it is
  53. * asymmetric and map[1] should be used.
  54. */
  55. char symmetric;
  56. struct chmc_obp_map map[2];
  57. };
  58. #define CHMCTRL_NBANKS 4
  59. struct chmc_bank_info {
  60. struct chmc *p;
  61. int bank_id;
  62. u64 raw_reg;
  63. int valid;
  64. int uk;
  65. int um;
  66. int lk;
  67. int lm;
  68. int interleave;
  69. unsigned long base;
  70. unsigned long size;
  71. };
  72. struct chmc {
  73. struct list_head list;
  74. int portid;
  75. struct chmc_obp_mem_layout layout_prop;
  76. int layout_size;
  77. void __iomem *regs;
  78. u64 timing_control1;
  79. u64 timing_control2;
  80. u64 timing_control3;
  81. u64 timing_control4;
  82. u64 memaddr_control;
  83. struct chmc_bank_info logical_banks[CHMCTRL_NBANKS];
  84. };
  85. #define JBUSMC_REGS_SIZE 8
  86. #define JB_MC_REG1_DIMM2_BANK3 0x8000000000000000UL
  87. #define JB_MC_REG1_DIMM1_BANK1 0x4000000000000000UL
  88. #define JB_MC_REG1_DIMM2_BANK2 0x2000000000000000UL
  89. #define JB_MC_REG1_DIMM1_BANK0 0x1000000000000000UL
  90. #define JB_MC_REG1_XOR 0x0000010000000000UL
  91. #define JB_MC_REG1_ADDR_GEN_2 0x000000e000000000UL
  92. #define JB_MC_REG1_ADDR_GEN_2_SHIFT 37
  93. #define JB_MC_REG1_ADDR_GEN_1 0x0000001c00000000UL
  94. #define JB_MC_REG1_ADDR_GEN_1_SHIFT 34
  95. #define JB_MC_REG1_INTERLEAVE 0x0000000001800000UL
  96. #define JB_MC_REG1_INTERLEAVE_SHIFT 23
  97. #define JB_MC_REG1_DIMM2_PTYPE 0x0000000000200000UL
  98. #define JB_MC_REG1_DIMM2_PTYPE_SHIFT 21
  99. #define JB_MC_REG1_DIMM1_PTYPE 0x0000000000100000UL
  100. #define JB_MC_REG1_DIMM1_PTYPE_SHIFT 20
  101. #define PART_TYPE_X8 0
  102. #define PART_TYPE_X4 1
  103. #define INTERLEAVE_NONE 0
  104. #define INTERLEAVE_SAME 1
  105. #define INTERLEAVE_INTERNAL 2
  106. #define INTERLEAVE_BOTH 3
  107. #define ADDR_GEN_128MB 0
  108. #define ADDR_GEN_256MB 1
  109. #define ADDR_GEN_512MB 2
  110. #define ADDR_GEN_1GB 3
  111. #define JB_NUM_DIMM_GROUPS 2
  112. #define JB_NUM_DIMMS_PER_GROUP 2
  113. #define JB_NUM_DIMMS (JB_NUM_DIMM_GROUPS * JB_NUM_DIMMS_PER_GROUP)
  114. struct jbusmc_obp_map {
  115. unsigned char dimm_map[18];
  116. unsigned char pin_map[144];
  117. };
  118. struct jbusmc_obp_mem_layout {
  119. /* One max 8-byte string label per DIMM. Usually
  120. * this matches the label on the motherboard where
  121. * that DIMM resides.
  122. */
  123. char dimm_labels[JB_NUM_DIMMS][DIMM_LABEL_SZ];
  124. /* If symmetric use map[0], else it is
  125. * asymmetric and map[1] should be used.
  126. */
  127. char symmetric;
  128. struct jbusmc_obp_map map;
  129. char _pad;
  130. };
  131. struct jbusmc_dimm_group {
  132. struct jbusmc *controller;
  133. int index;
  134. u64 base_addr;
  135. u64 size;
  136. };
  137. struct jbusmc {
  138. void __iomem *regs;
  139. u64 mc_reg_1;
  140. u32 portid;
  141. struct jbusmc_obp_mem_layout layout;
  142. int layout_len;
  143. int num_dimm_groups;
  144. struct jbusmc_dimm_group dimm_groups[JB_NUM_DIMM_GROUPS];
  145. struct list_head list;
  146. };
  147. static DEFINE_SPINLOCK(mctrl_list_lock);
  148. static LIST_HEAD(mctrl_list);
  149. static void mc_list_add(struct list_head *list)
  150. {
  151. spin_lock(&mctrl_list_lock);
  152. list_add(list, &mctrl_list);
  153. spin_unlock(&mctrl_list_lock);
  154. }
  155. static void mc_list_del(struct list_head *list)
  156. {
  157. spin_lock(&mctrl_list_lock);
  158. list_del_init(list);
  159. spin_unlock(&mctrl_list_lock);
  160. }
  161. #define SYNDROME_MIN -1
  162. #define SYNDROME_MAX 144
  163. /* Covert syndrome code into the way the bits are positioned
  164. * on the bus.
  165. */
  166. static int syndrome_to_qword_code(int syndrome_code)
  167. {
  168. if (syndrome_code < 128)
  169. syndrome_code += 16;
  170. else if (syndrome_code < 128 + 9)
  171. syndrome_code -= (128 - 7);
  172. else if (syndrome_code < (128 + 9 + 3))
  173. syndrome_code -= (128 + 9 - 4);
  174. else
  175. syndrome_code -= (128 + 9 + 3);
  176. return syndrome_code;
  177. }
  178. /* All this magic has to do with how a cache line comes over the wire
  179. * on Safari and JBUS. A 64-bit line comes over in 1 or more quadword
  180. * cycles, each of which transmit ECC/MTAG info as well as the actual
  181. * data.
  182. */
  183. #define L2_LINE_SIZE 64
  184. #define L2_LINE_ADDR_MSK (L2_LINE_SIZE - 1)
  185. #define QW_PER_LINE 4
  186. #define QW_BYTES (L2_LINE_SIZE / QW_PER_LINE)
  187. #define QW_BITS 144
  188. #define SAFARI_LAST_BIT (576 - 1)
  189. #define JBUS_LAST_BIT (144 - 1)
  190. static void get_pin_and_dimm_str(int syndrome_code, unsigned long paddr,
  191. int *pin_p, char **dimm_str_p, void *_prop,
  192. int base_dimm_offset)
  193. {
  194. int qword_code = syndrome_to_qword_code(syndrome_code);
  195. int cache_line_offset;
  196. int offset_inverse;
  197. int dimm_map_index;
  198. int map_val;
  199. if (mc_type == MC_TYPE_JBUS) {
  200. struct jbusmc_obp_mem_layout *p = _prop;
  201. /* JBUS */
  202. cache_line_offset = qword_code;
  203. offset_inverse = (JBUS_LAST_BIT - cache_line_offset);
  204. dimm_map_index = offset_inverse / 8;
  205. map_val = p->map.dimm_map[dimm_map_index];
  206. map_val = ((map_val >> ((7 - (offset_inverse & 7)))) & 1);
  207. *dimm_str_p = p->dimm_labels[base_dimm_offset + map_val];
  208. *pin_p = p->map.pin_map[cache_line_offset];
  209. } else {
  210. struct chmc_obp_mem_layout *p = _prop;
  211. struct chmc_obp_map *mp;
  212. int qword;
  213. /* Safari */
  214. if (p->symmetric)
  215. mp = &p->map[0];
  216. else
  217. mp = &p->map[1];
  218. qword = (paddr & L2_LINE_ADDR_MSK) / QW_BYTES;
  219. cache_line_offset = ((3 - qword) * QW_BITS) + qword_code;
  220. offset_inverse = (SAFARI_LAST_BIT - cache_line_offset);
  221. dimm_map_index = offset_inverse >> 2;
  222. map_val = mp->dimm_map[dimm_map_index];
  223. map_val = ((map_val >> ((3 - (offset_inverse & 3)) << 1)) & 0x3);
  224. *dimm_str_p = p->dimm_labels[base_dimm_offset + map_val];
  225. *pin_p = mp->pin_map[cache_line_offset];
  226. }
  227. }
  228. static struct jbusmc_dimm_group *jbusmc_find_dimm_group(unsigned long phys_addr)
  229. {
  230. struct jbusmc *p;
  231. list_for_each_entry(p, &mctrl_list, list) {
  232. int i;
  233. for (i = 0; i < p->num_dimm_groups; i++) {
  234. struct jbusmc_dimm_group *dp = &p->dimm_groups[i];
  235. if (phys_addr < dp->base_addr ||
  236. (dp->base_addr + dp->size) <= phys_addr)
  237. continue;
  238. return dp;
  239. }
  240. }
  241. return NULL;
  242. }
  243. static int jbusmc_print_dimm(int syndrome_code,
  244. unsigned long phys_addr,
  245. char *buf, int buflen)
  246. {
  247. struct jbusmc_obp_mem_layout *prop;
  248. struct jbusmc_dimm_group *dp;
  249. struct jbusmc *p;
  250. int first_dimm;
  251. dp = jbusmc_find_dimm_group(phys_addr);
  252. if (dp == NULL ||
  253. syndrome_code < SYNDROME_MIN ||
  254. syndrome_code > SYNDROME_MAX) {
  255. buf[0] = '?';
  256. buf[1] = '?';
  257. buf[2] = '?';
  258. buf[3] = '\0';
  259. return 0;
  260. }
  261. p = dp->controller;
  262. prop = &p->layout;
  263. first_dimm = dp->index * JB_NUM_DIMMS_PER_GROUP;
  264. if (syndrome_code != SYNDROME_MIN) {
  265. char *dimm_str;
  266. int pin;
  267. get_pin_and_dimm_str(syndrome_code, phys_addr, &pin,
  268. &dimm_str, prop, first_dimm);
  269. sprintf(buf, "%s, pin %3d", dimm_str, pin);
  270. } else {
  271. int dimm;
  272. /* Multi-bit error, we just dump out all the
  273. * dimm labels associated with this dimm group.
  274. */
  275. for (dimm = 0; dimm < JB_NUM_DIMMS_PER_GROUP; dimm++) {
  276. sprintf(buf, "%s ",
  277. prop->dimm_labels[first_dimm + dimm]);
  278. buf += strlen(buf);
  279. }
  280. }
  281. return 0;
  282. }
  283. static u64 jbusmc_dimm_group_size(u64 base,
  284. const struct linux_prom64_registers *mem_regs,
  285. int num_mem_regs)
  286. {
  287. u64 max = base + (8UL * 1024 * 1024 * 1024);
  288. u64 max_seen = base;
  289. int i;
  290. for (i = 0; i < num_mem_regs; i++) {
  291. const struct linux_prom64_registers *ent;
  292. u64 this_base;
  293. u64 this_end;
  294. ent = &mem_regs[i];
  295. this_base = ent->phys_addr;
  296. this_end = this_base + ent->reg_size;
  297. if (base < this_base || base >= this_end)
  298. continue;
  299. if (this_end > max)
  300. this_end = max;
  301. if (this_end > max_seen)
  302. max_seen = this_end;
  303. }
  304. return max_seen - base;
  305. }
  306. static void jbusmc_construct_one_dimm_group(struct jbusmc *p,
  307. unsigned long index,
  308. const struct linux_prom64_registers *mem_regs,
  309. int num_mem_regs)
  310. {
  311. struct jbusmc_dimm_group *dp = &p->dimm_groups[index];
  312. dp->controller = p;
  313. dp->index = index;
  314. dp->base_addr = (p->portid * (64UL * 1024 * 1024 * 1024));
  315. dp->base_addr += (index * (8UL * 1024 * 1024 * 1024));
  316. dp->size = jbusmc_dimm_group_size(dp->base_addr, mem_regs, num_mem_regs);
  317. }
  318. static void jbusmc_construct_dimm_groups(struct jbusmc *p,
  319. const struct linux_prom64_registers *mem_regs,
  320. int num_mem_regs)
  321. {
  322. if (p->mc_reg_1 & JB_MC_REG1_DIMM1_BANK0) {
  323. jbusmc_construct_one_dimm_group(p, 0, mem_regs, num_mem_regs);
  324. p->num_dimm_groups++;
  325. }
  326. if (p->mc_reg_1 & JB_MC_REG1_DIMM2_BANK2) {
  327. jbusmc_construct_one_dimm_group(p, 1, mem_regs, num_mem_regs);
  328. p->num_dimm_groups++;
  329. }
  330. }
  331. static int jbusmc_probe(struct platform_device *op)
  332. {
  333. const struct linux_prom64_registers *mem_regs;
  334. struct device_node *mem_node;
  335. int err, len, num_mem_regs;
  336. struct jbusmc *p;
  337. const u32 *prop;
  338. const void *ml;
  339. err = -ENODEV;
  340. mem_node = of_find_node_by_path("/memory");
  341. if (!mem_node) {
  342. printk(KERN_ERR PFX "Cannot find /memory node.\n");
  343. goto out;
  344. }
  345. mem_regs = of_get_property(mem_node, "reg", &len);
  346. if (!mem_regs) {
  347. printk(KERN_ERR PFX "Cannot get reg property of /memory node.\n");
  348. goto out;
  349. }
  350. num_mem_regs = len / sizeof(*mem_regs);
  351. err = -ENOMEM;
  352. p = kzalloc(sizeof(*p), GFP_KERNEL);
  353. if (!p) {
  354. printk(KERN_ERR PFX "Cannot allocate struct jbusmc.\n");
  355. goto out;
  356. }
  357. INIT_LIST_HEAD(&p->list);
  358. err = -ENODEV;
  359. prop = of_get_property(op->dev.of_node, "portid", &len);
  360. if (!prop || len != 4) {
  361. printk(KERN_ERR PFX "Cannot find portid.\n");
  362. goto out_free;
  363. }
  364. p->portid = *prop;
  365. prop = of_get_property(op->dev.of_node, "memory-control-register-1", &len);
  366. if (!prop || len != 8) {
  367. printk(KERN_ERR PFX "Cannot get memory control register 1.\n");
  368. goto out_free;
  369. }
  370. p->mc_reg_1 = ((u64)prop[0] << 32) | (u64) prop[1];
  371. err = -ENOMEM;
  372. p->regs = of_ioremap(&op->resource[0], 0, JBUSMC_REGS_SIZE, "jbusmc");
  373. if (!p->regs) {
  374. printk(KERN_ERR PFX "Cannot map jbusmc regs.\n");
  375. goto out_free;
  376. }
  377. err = -ENODEV;
  378. ml = of_get_property(op->dev.of_node, "memory-layout", &p->layout_len);
  379. if (!ml) {
  380. printk(KERN_ERR PFX "Cannot get memory layout property.\n");
  381. goto out_iounmap;
  382. }
  383. if (p->layout_len > sizeof(p->layout)) {
  384. printk(KERN_ERR PFX "Unexpected memory-layout size %d\n",
  385. p->layout_len);
  386. goto out_iounmap;
  387. }
  388. memcpy(&p->layout, ml, p->layout_len);
  389. jbusmc_construct_dimm_groups(p, mem_regs, num_mem_regs);
  390. mc_list_add(&p->list);
  391. printk(KERN_INFO PFX "UltraSPARC-IIIi memory controller at %pOF\n",
  392. op->dev.of_node);
  393. dev_set_drvdata(&op->dev, p);
  394. err = 0;
  395. out:
  396. return err;
  397. out_iounmap:
  398. of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);
  399. out_free:
  400. kfree(p);
  401. goto out;
  402. }
  403. /* Does BANK decode PHYS_ADDR? */
  404. static int chmc_bank_match(struct chmc_bank_info *bp, unsigned long phys_addr)
  405. {
  406. unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT;
  407. unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT;
  408. /* Bank must be enabled to match. */
  409. if (bp->valid == 0)
  410. return 0;
  411. /* Would BANK match upper bits? */
  412. upper_bits ^= bp->um; /* What bits are different? */
  413. upper_bits = ~upper_bits; /* Invert. */
  414. upper_bits |= bp->uk; /* What bits don't matter for matching? */
  415. upper_bits = ~upper_bits; /* Invert. */
  416. if (upper_bits)
  417. return 0;
  418. /* Would BANK match lower bits? */
  419. lower_bits ^= bp->lm; /* What bits are different? */
  420. lower_bits = ~lower_bits; /* Invert. */
  421. lower_bits |= bp->lk; /* What bits don't matter for matching? */
  422. lower_bits = ~lower_bits; /* Invert. */
  423. if (lower_bits)
  424. return 0;
  425. /* I always knew you'd be the one. */
  426. return 1;
  427. }
  428. /* Given PHYS_ADDR, search memory controller banks for a match. */
  429. static struct chmc_bank_info *chmc_find_bank(unsigned long phys_addr)
  430. {
  431. struct chmc *p;
  432. list_for_each_entry(p, &mctrl_list, list) {
  433. int bank_no;
  434. for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) {
  435. struct chmc_bank_info *bp;
  436. bp = &p->logical_banks[bank_no];
  437. if (chmc_bank_match(bp, phys_addr))
  438. return bp;
  439. }
  440. }
  441. return NULL;
  442. }
  443. /* This is the main purpose of this driver. */
  444. static int chmc_print_dimm(int syndrome_code,
  445. unsigned long phys_addr,
  446. char *buf, int buflen)
  447. {
  448. struct chmc_bank_info *bp;
  449. struct chmc_obp_mem_layout *prop;
  450. int bank_in_controller, first_dimm;
  451. bp = chmc_find_bank(phys_addr);
  452. if (bp == NULL ||
  453. syndrome_code < SYNDROME_MIN ||
  454. syndrome_code > SYNDROME_MAX) {
  455. buf[0] = '?';
  456. buf[1] = '?';
  457. buf[2] = '?';
  458. buf[3] = '\0';
  459. return 0;
  460. }
  461. prop = &bp->p->layout_prop;
  462. bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);
  463. first_dimm = (bank_in_controller & (CHMCTRL_NDGRPS - 1));
  464. first_dimm *= CHMCTRL_NDIMMS;
  465. if (syndrome_code != SYNDROME_MIN) {
  466. char *dimm_str;
  467. int pin;
  468. get_pin_and_dimm_str(syndrome_code, phys_addr, &pin,
  469. &dimm_str, prop, first_dimm);
  470. sprintf(buf, "%s, pin %3d", dimm_str, pin);
  471. } else {
  472. int dimm;
  473. /* Multi-bit error, we just dump out all the
  474. * dimm labels associated with this bank.
  475. */
  476. for (dimm = 0; dimm < CHMCTRL_NDIMMS; dimm++) {
  477. sprintf(buf, "%s ",
  478. prop->dimm_labels[first_dimm + dimm]);
  479. buf += strlen(buf);
  480. }
  481. }
  482. return 0;
  483. }
  484. /* Accessing the registers is slightly complicated. If you want
  485. * to get at the memory controller which is on the same processor
  486. * the code is executing, you must use special ASI load/store else
  487. * you go through the global mapping.
  488. */
  489. static u64 chmc_read_mcreg(struct chmc *p, unsigned long offset)
  490. {
  491. unsigned long ret, this_cpu;
  492. preempt_disable();
  493. this_cpu = real_hard_smp_processor_id();
  494. if (p->portid == this_cpu) {
  495. __asm__ __volatile__("ldxa [%1] %2, %0"
  496. : "=r" (ret)
  497. : "r" (offset), "i" (ASI_MCU_CTRL_REG));
  498. } else {
  499. __asm__ __volatile__("ldxa [%1] %2, %0"
  500. : "=r" (ret)
  501. : "r" (p->regs + offset),
  502. "i" (ASI_PHYS_BYPASS_EC_E));
  503. }
  504. preempt_enable();
  505. return ret;
  506. }
  507. #if 0 /* currently unused */
  508. static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val)
  509. {
  510. if (p->portid == smp_processor_id()) {
  511. __asm__ __volatile__("stxa %0, [%1] %2"
  512. : : "r" (val),
  513. "r" (offset), "i" (ASI_MCU_CTRL_REG));
  514. } else {
  515. __asm__ __volatile__("ldxa %0, [%1] %2"
  516. : : "r" (val),
  517. "r" (p->regs + offset),
  518. "i" (ASI_PHYS_BYPASS_EC_E));
  519. }
  520. }
  521. #endif
  522. static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val)
  523. {
  524. struct chmc_bank_info *bp = &p->logical_banks[which_bank];
  525. bp->p = p;
  526. bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank;
  527. bp->raw_reg = val;
  528. bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
  529. bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
  530. bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
  531. bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
  532. bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;
  533. bp->base = (bp->um);
  534. bp->base &= ~(bp->uk);
  535. bp->base <<= PA_UPPER_BITS_SHIFT;
  536. switch(bp->lk) {
  537. case 0xf:
  538. default:
  539. bp->interleave = 1;
  540. break;
  541. case 0xe:
  542. bp->interleave = 2;
  543. break;
  544. case 0xc:
  545. bp->interleave = 4;
  546. break;
  547. case 0x8:
  548. bp->interleave = 8;
  549. break;
  550. case 0x0:
  551. bp->interleave = 16;
  552. break;
  553. }
  554. /* UK[10] is reserved, and UK[11] is not set for the SDRAM
  555. * bank size definition.
  556. */
  557. bp->size = (((unsigned long)bp->uk &
  558. ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
  559. bp->size /= bp->interleave;
  560. }
  561. static void chmc_fetch_decode_regs(struct chmc *p)
  562. {
  563. if (p->layout_size == 0)
  564. return;
  565. chmc_interpret_one_decode_reg(p, 0,
  566. chmc_read_mcreg(p, CHMCTRL_DECODE1));
  567. chmc_interpret_one_decode_reg(p, 1,
  568. chmc_read_mcreg(p, CHMCTRL_DECODE2));
  569. chmc_interpret_one_decode_reg(p, 2,
  570. chmc_read_mcreg(p, CHMCTRL_DECODE3));
  571. chmc_interpret_one_decode_reg(p, 3,
  572. chmc_read_mcreg(p, CHMCTRL_DECODE4));
  573. }
  574. static int chmc_probe(struct platform_device *op)
  575. {
  576. struct device_node *dp = op->dev.of_node;
  577. unsigned long ver;
  578. const void *pval;
  579. int len, portid;
  580. struct chmc *p;
  581. int err;
  582. err = -ENODEV;
  583. __asm__ ("rdpr %%ver, %0" : "=r" (ver));
  584. if ((ver >> 32UL) == __JALAPENO_ID ||
  585. (ver >> 32UL) == __SERRANO_ID)
  586. goto out;
  587. portid = of_getintprop_default(dp, "portid", -1);
  588. if (portid == -1)
  589. goto out;
  590. pval = of_get_property(dp, "memory-layout", &len);
  591. if (pval && len > sizeof(p->layout_prop)) {
  592. printk(KERN_ERR PFX "Unexpected memory-layout property "
  593. "size %d.\n", len);
  594. goto out;
  595. }
  596. err = -ENOMEM;
  597. p = kzalloc(sizeof(*p), GFP_KERNEL);
  598. if (!p) {
  599. printk(KERN_ERR PFX "Could not allocate struct chmc.\n");
  600. goto out;
  601. }
  602. p->portid = portid;
  603. p->layout_size = len;
  604. if (!pval)
  605. p->layout_size = 0;
  606. else
  607. memcpy(&p->layout_prop, pval, len);
  608. p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");
  609. if (!p->regs) {
  610. printk(KERN_ERR PFX "Could not map registers.\n");
  611. goto out_free;
  612. }
  613. if (p->layout_size != 0UL) {
  614. p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1);
  615. p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2);
  616. p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3);
  617. p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4);
  618. p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL);
  619. }
  620. chmc_fetch_decode_regs(p);
  621. mc_list_add(&p->list);
  622. printk(KERN_INFO PFX "UltraSPARC-III memory controller at %pOF [%s]\n",
  623. dp,
  624. (p->layout_size ? "ACTIVE" : "INACTIVE"));
  625. dev_set_drvdata(&op->dev, p);
  626. err = 0;
  627. out:
  628. return err;
  629. out_free:
  630. kfree(p);
  631. goto out;
  632. }
  633. static int us3mc_probe(struct platform_device *op)
  634. {
  635. if (mc_type == MC_TYPE_SAFARI)
  636. return chmc_probe(op);
  637. else if (mc_type == MC_TYPE_JBUS)
  638. return jbusmc_probe(op);
  639. return -ENODEV;
  640. }
  641. static void chmc_destroy(struct platform_device *op, struct chmc *p)
  642. {
  643. list_del(&p->list);
  644. of_iounmap(&op->resource[0], p->regs, 0x48);
  645. kfree(p);
  646. }
  647. static void jbusmc_destroy(struct platform_device *op, struct jbusmc *p)
  648. {
  649. mc_list_del(&p->list);
  650. of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);
  651. kfree(p);
  652. }
  653. static int us3mc_remove(struct platform_device *op)
  654. {
  655. void *p = dev_get_drvdata(&op->dev);
  656. if (p) {
  657. if (mc_type == MC_TYPE_SAFARI)
  658. chmc_destroy(op, p);
  659. else if (mc_type == MC_TYPE_JBUS)
  660. jbusmc_destroy(op, p);
  661. }
  662. return 0;
  663. }
  664. static const struct of_device_id us3mc_match[] = {
  665. {
  666. .name = "memory-controller",
  667. },
  668. {},
  669. };
  670. MODULE_DEVICE_TABLE(of, us3mc_match);
  671. static struct platform_driver us3mc_driver = {
  672. .driver = {
  673. .name = "us3mc",
  674. .of_match_table = us3mc_match,
  675. },
  676. .probe = us3mc_probe,
  677. .remove = us3mc_remove,
  678. };
  679. static inline bool us3mc_platform(void)
  680. {
  681. if (tlb_type == cheetah || tlb_type == cheetah_plus)
  682. return true;
  683. return false;
  684. }
  685. static int __init us3mc_init(void)
  686. {
  687. unsigned long ver;
  688. int ret;
  689. if (!us3mc_platform())
  690. return -ENODEV;
  691. __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
  692. if ((ver >> 32UL) == __JALAPENO_ID ||
  693. (ver >> 32UL) == __SERRANO_ID) {
  694. mc_type = MC_TYPE_JBUS;
  695. us3mc_dimm_printer = jbusmc_print_dimm;
  696. } else {
  697. mc_type = MC_TYPE_SAFARI;
  698. us3mc_dimm_printer = chmc_print_dimm;
  699. }
  700. ret = register_dimm_printer(us3mc_dimm_printer);
  701. if (!ret) {
  702. ret = platform_driver_register(&us3mc_driver);
  703. if (ret)
  704. unregister_dimm_printer(us3mc_dimm_printer);
  705. }
  706. return ret;
  707. }
  708. static void __exit us3mc_cleanup(void)
  709. {
  710. if (us3mc_platform()) {
  711. unregister_dimm_printer(us3mc_dimm_printer);
  712. platform_driver_unregister(&us3mc_driver);
  713. }
  714. }
  715. module_init(us3mc_init);
  716. module_exit(us3mc_cleanup);