tlb-sh3.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/sh/mm/tlb-sh3.c
  4. *
  5. * SH-3 specific TLB operations
  6. *
  7. * Copyright (C) 1999 Niibe Yutaka
  8. * Copyright (C) 2002 Paul Mundt
  9. */
  10. #include <linux/signal.h>
  11. #include <linux/sched.h>
  12. #include <linux/kernel.h>
  13. #include <linux/errno.h>
  14. #include <linux/string.h>
  15. #include <linux/types.h>
  16. #include <linux/ptrace.h>
  17. #include <linux/mman.h>
  18. #include <linux/mm.h>
  19. #include <linux/smp.h>
  20. #include <linux/interrupt.h>
  21. #include <asm/io.h>
  22. #include <linux/uaccess.h>
  23. #include <asm/mmu_context.h>
  24. #include <asm/cacheflush.h>
  25. void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
  26. {
  27. unsigned long flags, pteval, vpn;
  28. /*
  29. * Handle debugger faulting in for debugee.
  30. */
  31. if (vma && current->active_mm != vma->vm_mm)
  32. return;
  33. local_irq_save(flags);
  34. /* Set PTEH register */
  35. vpn = (address & MMU_VPN_MASK) | get_asid();
  36. __raw_writel(vpn, MMU_PTEH);
  37. pteval = pte_val(pte);
  38. /* Set PTEL register */
  39. pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
  40. /* conveniently, we want all the software flags to be 0 anyway */
  41. __raw_writel(pteval, MMU_PTEL);
  42. /* Load the TLB */
  43. asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
  44. local_irq_restore(flags);
  45. }
  46. void local_flush_tlb_one(unsigned long asid, unsigned long page)
  47. {
  48. unsigned long addr, data;
  49. int i, ways = MMU_NTLB_WAYS;
  50. /*
  51. * NOTE: PTEH.ASID should be set to this MM
  52. * _AND_ we need to write ASID to the array.
  53. *
  54. * It would be simple if we didn't need to set PTEH.ASID...
  55. */
  56. addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
  57. data = (page & 0xfffe0000) | asid; /* VALID bit is off */
  58. if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
  59. addr |= MMU_PAGE_ASSOC_BIT;
  60. ways = 1; /* we already know the way .. */
  61. }
  62. for (i = 0; i < ways; i++)
  63. __raw_writel(data, addr + (i << 8));
  64. }
  65. void local_flush_tlb_all(void)
  66. {
  67. unsigned long flags, status;
  68. /*
  69. * Flush all the TLB.
  70. *
  71. * Write to the MMU control register's bit:
  72. * TF-bit for SH-3, TI-bit for SH-4.
  73. * It's same position, bit #2.
  74. */
  75. local_irq_save(flags);
  76. status = __raw_readl(MMUCR);
  77. status |= 0x04;
  78. __raw_writel(status, MMUCR);
  79. ctrl_barrier();
  80. local_irq_restore(flags);
  81. }