perf_event.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Performance event support framework for SuperH hardware counters.
  4. *
  5. * Copyright (C) 2009 Paul Mundt
  6. *
  7. * Heavily based on the x86 and PowerPC implementations.
  8. *
  9. * x86:
  10. * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
  11. * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
  12. * Copyright (C) 2009 Jaswinder Singh Rajput
  13. * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
  14. * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
  15. * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  16. *
  17. * ppc:
  18. * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/io.h>
  23. #include <linux/irq.h>
  24. #include <linux/perf_event.h>
  25. #include <linux/export.h>
  26. #include <asm/processor.h>
  27. struct cpu_hw_events {
  28. struct perf_event *events[MAX_HWEVENTS];
  29. unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
  30. unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
  31. };
  32. DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
  33. static struct sh_pmu *sh_pmu __read_mostly;
  34. /* Number of perf_events counting hardware events */
  35. static atomic_t num_events;
  36. /* Used to avoid races in calling reserve/release_pmc_hardware */
  37. static DEFINE_MUTEX(pmc_reserve_mutex);
  38. /*
  39. * Stub these out for now, do something more profound later.
  40. */
  41. int reserve_pmc_hardware(void)
  42. {
  43. return 0;
  44. }
  45. void release_pmc_hardware(void)
  46. {
  47. }
  48. static inline int sh_pmu_initialized(void)
  49. {
  50. return !!sh_pmu;
  51. }
  52. const char *perf_pmu_name(void)
  53. {
  54. if (!sh_pmu)
  55. return NULL;
  56. return sh_pmu->name;
  57. }
  58. EXPORT_SYMBOL_GPL(perf_pmu_name);
  59. int perf_num_counters(void)
  60. {
  61. if (!sh_pmu)
  62. return 0;
  63. return sh_pmu->num_events;
  64. }
  65. EXPORT_SYMBOL_GPL(perf_num_counters);
  66. /*
  67. * Release the PMU if this is the last perf_event.
  68. */
  69. static void hw_perf_event_destroy(struct perf_event *event)
  70. {
  71. if (!atomic_add_unless(&num_events, -1, 1)) {
  72. mutex_lock(&pmc_reserve_mutex);
  73. if (atomic_dec_return(&num_events) == 0)
  74. release_pmc_hardware();
  75. mutex_unlock(&pmc_reserve_mutex);
  76. }
  77. }
  78. static int hw_perf_cache_event(int config, int *evp)
  79. {
  80. unsigned long type, op, result;
  81. int ev;
  82. if (!sh_pmu->cache_events)
  83. return -EINVAL;
  84. /* unpack config */
  85. type = config & 0xff;
  86. op = (config >> 8) & 0xff;
  87. result = (config >> 16) & 0xff;
  88. if (type >= PERF_COUNT_HW_CACHE_MAX ||
  89. op >= PERF_COUNT_HW_CACHE_OP_MAX ||
  90. result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  91. return -EINVAL;
  92. ev = (*sh_pmu->cache_events)[type][op][result];
  93. if (ev == 0)
  94. return -EOPNOTSUPP;
  95. if (ev == -1)
  96. return -EINVAL;
  97. *evp = ev;
  98. return 0;
  99. }
  100. static int __hw_perf_event_init(struct perf_event *event)
  101. {
  102. struct perf_event_attr *attr = &event->attr;
  103. struct hw_perf_event *hwc = &event->hw;
  104. int config = -1;
  105. int err;
  106. if (!sh_pmu_initialized())
  107. return -ENODEV;
  108. /*
  109. * See if we need to reserve the counter.
  110. *
  111. * If no events are currently in use, then we have to take a
  112. * mutex to ensure that we don't race with another task doing
  113. * reserve_pmc_hardware or release_pmc_hardware.
  114. */
  115. err = 0;
  116. if (!atomic_inc_not_zero(&num_events)) {
  117. mutex_lock(&pmc_reserve_mutex);
  118. if (atomic_read(&num_events) == 0 &&
  119. reserve_pmc_hardware())
  120. err = -EBUSY;
  121. else
  122. atomic_inc(&num_events);
  123. mutex_unlock(&pmc_reserve_mutex);
  124. }
  125. if (err)
  126. return err;
  127. event->destroy = hw_perf_event_destroy;
  128. switch (attr->type) {
  129. case PERF_TYPE_RAW:
  130. config = attr->config & sh_pmu->raw_event_mask;
  131. break;
  132. case PERF_TYPE_HW_CACHE:
  133. err = hw_perf_cache_event(attr->config, &config);
  134. if (err)
  135. return err;
  136. break;
  137. case PERF_TYPE_HARDWARE:
  138. if (attr->config >= sh_pmu->max_events)
  139. return -EINVAL;
  140. config = sh_pmu->event_map(attr->config);
  141. break;
  142. }
  143. if (config == -1)
  144. return -EINVAL;
  145. hwc->config |= config;
  146. return 0;
  147. }
  148. static void sh_perf_event_update(struct perf_event *event,
  149. struct hw_perf_event *hwc, int idx)
  150. {
  151. u64 prev_raw_count, new_raw_count;
  152. s64 delta;
  153. int shift = 0;
  154. /*
  155. * Depending on the counter configuration, they may or may not
  156. * be chained, in which case the previous counter value can be
  157. * updated underneath us if the lower-half overflows.
  158. *
  159. * Our tactic to handle this is to first atomically read and
  160. * exchange a new raw count - then add that new-prev delta
  161. * count to the generic counter atomically.
  162. *
  163. * As there is no interrupt associated with the overflow events,
  164. * this is the simplest approach for maintaining consistency.
  165. */
  166. again:
  167. prev_raw_count = local64_read(&hwc->prev_count);
  168. new_raw_count = sh_pmu->read(idx);
  169. if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  170. new_raw_count) != prev_raw_count)
  171. goto again;
  172. /*
  173. * Now we have the new raw value and have updated the prev
  174. * timestamp already. We can now calculate the elapsed delta
  175. * (counter-)time and add that to the generic counter.
  176. *
  177. * Careful, not all hw sign-extends above the physical width
  178. * of the count.
  179. */
  180. delta = (new_raw_count << shift) - (prev_raw_count << shift);
  181. delta >>= shift;
  182. local64_add(delta, &event->count);
  183. }
  184. static void sh_pmu_stop(struct perf_event *event, int flags)
  185. {
  186. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  187. struct hw_perf_event *hwc = &event->hw;
  188. int idx = hwc->idx;
  189. if (!(event->hw.state & PERF_HES_STOPPED)) {
  190. sh_pmu->disable(hwc, idx);
  191. cpuc->events[idx] = NULL;
  192. event->hw.state |= PERF_HES_STOPPED;
  193. }
  194. if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
  195. sh_perf_event_update(event, &event->hw, idx);
  196. event->hw.state |= PERF_HES_UPTODATE;
  197. }
  198. }
  199. static void sh_pmu_start(struct perf_event *event, int flags)
  200. {
  201. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  202. struct hw_perf_event *hwc = &event->hw;
  203. int idx = hwc->idx;
  204. if (WARN_ON_ONCE(idx == -1))
  205. return;
  206. if (flags & PERF_EF_RELOAD)
  207. WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
  208. cpuc->events[idx] = event;
  209. event->hw.state = 0;
  210. sh_pmu->enable(hwc, idx);
  211. }
  212. static void sh_pmu_del(struct perf_event *event, int flags)
  213. {
  214. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  215. sh_pmu_stop(event, PERF_EF_UPDATE);
  216. __clear_bit(event->hw.idx, cpuc->used_mask);
  217. perf_event_update_userpage(event);
  218. }
  219. static int sh_pmu_add(struct perf_event *event, int flags)
  220. {
  221. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  222. struct hw_perf_event *hwc = &event->hw;
  223. int idx = hwc->idx;
  224. int ret = -EAGAIN;
  225. perf_pmu_disable(event->pmu);
  226. if (__test_and_set_bit(idx, cpuc->used_mask)) {
  227. idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);
  228. if (idx == sh_pmu->num_events)
  229. goto out;
  230. __set_bit(idx, cpuc->used_mask);
  231. hwc->idx = idx;
  232. }
  233. sh_pmu->disable(hwc, idx);
  234. event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
  235. if (flags & PERF_EF_START)
  236. sh_pmu_start(event, PERF_EF_RELOAD);
  237. perf_event_update_userpage(event);
  238. ret = 0;
  239. out:
  240. perf_pmu_enable(event->pmu);
  241. return ret;
  242. }
  243. static void sh_pmu_read(struct perf_event *event)
  244. {
  245. sh_perf_event_update(event, &event->hw, event->hw.idx);
  246. }
  247. static int sh_pmu_event_init(struct perf_event *event)
  248. {
  249. int err;
  250. /* does not support taken branch sampling */
  251. if (has_branch_stack(event))
  252. return -EOPNOTSUPP;
  253. switch (event->attr.type) {
  254. case PERF_TYPE_RAW:
  255. case PERF_TYPE_HW_CACHE:
  256. case PERF_TYPE_HARDWARE:
  257. err = __hw_perf_event_init(event);
  258. break;
  259. default:
  260. return -ENOENT;
  261. }
  262. if (unlikely(err)) {
  263. if (event->destroy)
  264. event->destroy(event);
  265. }
  266. return err;
  267. }
  268. static void sh_pmu_enable(struct pmu *pmu)
  269. {
  270. if (!sh_pmu_initialized())
  271. return;
  272. sh_pmu->enable_all();
  273. }
  274. static void sh_pmu_disable(struct pmu *pmu)
  275. {
  276. if (!sh_pmu_initialized())
  277. return;
  278. sh_pmu->disable_all();
  279. }
  280. static struct pmu pmu = {
  281. .pmu_enable = sh_pmu_enable,
  282. .pmu_disable = sh_pmu_disable,
  283. .event_init = sh_pmu_event_init,
  284. .add = sh_pmu_add,
  285. .del = sh_pmu_del,
  286. .start = sh_pmu_start,
  287. .stop = sh_pmu_stop,
  288. .read = sh_pmu_read,
  289. };
  290. static int sh_pmu_prepare_cpu(unsigned int cpu)
  291. {
  292. struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
  293. memset(cpuhw, 0, sizeof(struct cpu_hw_events));
  294. return 0;
  295. }
  296. int register_sh_pmu(struct sh_pmu *_pmu)
  297. {
  298. if (sh_pmu)
  299. return -EBUSY;
  300. sh_pmu = _pmu;
  301. pr_info("Performance Events: %s support registered\n", _pmu->name);
  302. /*
  303. * All of the on-chip counters are "limited", in that they have
  304. * no interrupts, and are therefore unable to do sampling without
  305. * further work and timer assistance.
  306. */
  307. pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
  308. WARN_ON(_pmu->num_events > MAX_HWEVENTS);
  309. perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
  310. cpuhp_setup_state(CPUHP_PERF_SUPERH, "PERF_SUPERH", sh_pmu_prepare_cpu,
  311. NULL);
  312. return 0;
  313. }