mpic_msgr.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
  4. *
  5. * Some ideas based on un-pushed work done by Vivek Mahajan, Jason Jin, and
  6. * Mingkai Hu from Freescale Semiconductor, Inc.
  7. */
  8. #include <linux/list.h>
  9. #include <linux/of_platform.h>
  10. #include <linux/errno.h>
  11. #include <linux/err.h>
  12. #include <linux/export.h>
  13. #include <linux/slab.h>
  14. #include <asm/prom.h>
  15. #include <asm/hw_irq.h>
  16. #include <asm/ppc-pci.h>
  17. #include <asm/mpic_msgr.h>
  18. #define MPIC_MSGR_REGISTERS_PER_BLOCK 4
  19. #define MPIC_MSGR_STRIDE 0x10
  20. #define MPIC_MSGR_MER_OFFSET 0x100
  21. #define MSGR_INUSE 0
  22. #define MSGR_FREE 1
  23. static struct mpic_msgr **mpic_msgrs;
  24. static unsigned int mpic_msgr_count;
  25. static DEFINE_RAW_SPINLOCK(msgrs_lock);
  26. static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
  27. {
  28. out_be32(msgr->mer, value);
  29. }
  30. static inline u32 _mpic_msgr_mer_read(struct mpic_msgr *msgr)
  31. {
  32. return in_be32(msgr->mer);
  33. }
  34. static inline void _mpic_msgr_disable(struct mpic_msgr *msgr)
  35. {
  36. u32 mer = _mpic_msgr_mer_read(msgr);
  37. _mpic_msgr_mer_write(msgr, mer & ~(1 << msgr->num));
  38. }
  39. struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
  40. {
  41. unsigned long flags;
  42. struct mpic_msgr *msgr;
  43. /* Assume busy until proven otherwise. */
  44. msgr = ERR_PTR(-EBUSY);
  45. if (reg_num >= mpic_msgr_count)
  46. return ERR_PTR(-ENODEV);
  47. raw_spin_lock_irqsave(&msgrs_lock, flags);
  48. msgr = mpic_msgrs[reg_num];
  49. if (msgr->in_use == MSGR_FREE)
  50. msgr->in_use = MSGR_INUSE;
  51. raw_spin_unlock_irqrestore(&msgrs_lock, flags);
  52. return msgr;
  53. }
  54. EXPORT_SYMBOL_GPL(mpic_msgr_get);
  55. void mpic_msgr_put(struct mpic_msgr *msgr)
  56. {
  57. unsigned long flags;
  58. raw_spin_lock_irqsave(&msgr->lock, flags);
  59. msgr->in_use = MSGR_FREE;
  60. _mpic_msgr_disable(msgr);
  61. raw_spin_unlock_irqrestore(&msgr->lock, flags);
  62. }
  63. EXPORT_SYMBOL_GPL(mpic_msgr_put);
  64. void mpic_msgr_enable(struct mpic_msgr *msgr)
  65. {
  66. unsigned long flags;
  67. u32 mer;
  68. raw_spin_lock_irqsave(&msgr->lock, flags);
  69. mer = _mpic_msgr_mer_read(msgr);
  70. _mpic_msgr_mer_write(msgr, mer | (1 << msgr->num));
  71. raw_spin_unlock_irqrestore(&msgr->lock, flags);
  72. }
  73. EXPORT_SYMBOL_GPL(mpic_msgr_enable);
  74. void mpic_msgr_disable(struct mpic_msgr *msgr)
  75. {
  76. unsigned long flags;
  77. raw_spin_lock_irqsave(&msgr->lock, flags);
  78. _mpic_msgr_disable(msgr);
  79. raw_spin_unlock_irqrestore(&msgr->lock, flags);
  80. }
  81. EXPORT_SYMBOL_GPL(mpic_msgr_disable);
  82. /* The following three functions are used to compute the order and number of
  83. * the message register blocks. They are clearly very inefficent. However,
  84. * they are called *only* a few times during device initialization.
  85. */
  86. static unsigned int mpic_msgr_number_of_blocks(void)
  87. {
  88. unsigned int count;
  89. struct device_node *aliases;
  90. count = 0;
  91. aliases = of_find_node_by_name(NULL, "aliases");
  92. if (aliases) {
  93. char buf[32];
  94. for (;;) {
  95. snprintf(buf, sizeof(buf), "mpic-msgr-block%d", count);
  96. if (!of_find_property(aliases, buf, NULL))
  97. break;
  98. count += 1;
  99. }
  100. }
  101. return count;
  102. }
  103. static unsigned int mpic_msgr_number_of_registers(void)
  104. {
  105. return mpic_msgr_number_of_blocks() * MPIC_MSGR_REGISTERS_PER_BLOCK;
  106. }
  107. static int mpic_msgr_block_number(struct device_node *node)
  108. {
  109. struct device_node *aliases;
  110. unsigned int index, number_of_blocks;
  111. char buf[64];
  112. number_of_blocks = mpic_msgr_number_of_blocks();
  113. aliases = of_find_node_by_name(NULL, "aliases");
  114. if (!aliases)
  115. return -1;
  116. for (index = 0; index < number_of_blocks; ++index) {
  117. struct property *prop;
  118. snprintf(buf, sizeof(buf), "mpic-msgr-block%d", index);
  119. prop = of_find_property(aliases, buf, NULL);
  120. if (node == of_find_node_by_path(prop->value))
  121. break;
  122. }
  123. return index == number_of_blocks ? -1 : index;
  124. }
  125. /* The probe function for a single message register block.
  126. */
  127. static int mpic_msgr_probe(struct platform_device *dev)
  128. {
  129. void __iomem *msgr_block_addr;
  130. int block_number;
  131. struct resource rsrc;
  132. unsigned int i;
  133. unsigned int irq_index;
  134. struct device_node *np = dev->dev.of_node;
  135. unsigned int receive_mask;
  136. const unsigned int *prop;
  137. if (!np) {
  138. dev_err(&dev->dev, "Device OF-Node is NULL");
  139. return -EFAULT;
  140. }
  141. /* Allocate the message register array upon the first device
  142. * registered.
  143. */
  144. if (!mpic_msgrs) {
  145. mpic_msgr_count = mpic_msgr_number_of_registers();
  146. dev_info(&dev->dev, "Found %d message registers\n",
  147. mpic_msgr_count);
  148. mpic_msgrs = kcalloc(mpic_msgr_count, sizeof(*mpic_msgrs),
  149. GFP_KERNEL);
  150. if (!mpic_msgrs) {
  151. dev_err(&dev->dev,
  152. "No memory for message register blocks\n");
  153. return -ENOMEM;
  154. }
  155. }
  156. dev_info(&dev->dev, "Of-device full name %pOF\n", np);
  157. /* IO map the message register block. */
  158. of_address_to_resource(np, 0, &rsrc);
  159. msgr_block_addr = devm_ioremap(&dev->dev, rsrc.start, resource_size(&rsrc));
  160. if (!msgr_block_addr) {
  161. dev_err(&dev->dev, "Failed to iomap MPIC message registers");
  162. return -EFAULT;
  163. }
  164. /* Ensure the block has a defined order. */
  165. block_number = mpic_msgr_block_number(np);
  166. if (block_number < 0) {
  167. dev_err(&dev->dev,
  168. "Failed to find message register block alias\n");
  169. return -ENODEV;
  170. }
  171. dev_info(&dev->dev, "Setting up message register block %d\n",
  172. block_number);
  173. /* Grab the receive mask which specifies what registers can receive
  174. * interrupts.
  175. */
  176. prop = of_get_property(np, "mpic-msgr-receive-mask", NULL);
  177. receive_mask = (prop) ? *prop : 0xF;
  178. /* Build up the appropriate message register data structures. */
  179. for (i = 0, irq_index = 0; i < MPIC_MSGR_REGISTERS_PER_BLOCK; ++i) {
  180. struct mpic_msgr *msgr;
  181. unsigned int reg_number;
  182. msgr = kzalloc(sizeof(struct mpic_msgr), GFP_KERNEL);
  183. if (!msgr) {
  184. dev_err(&dev->dev, "No memory for message register\n");
  185. return -ENOMEM;
  186. }
  187. reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
  188. msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
  189. msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET);
  190. msgr->in_use = MSGR_FREE;
  191. msgr->num = i;
  192. raw_spin_lock_init(&msgr->lock);
  193. if (receive_mask & (1 << i)) {
  194. msgr->irq = irq_of_parse_and_map(np, irq_index);
  195. if (!msgr->irq) {
  196. dev_err(&dev->dev,
  197. "Missing interrupt specifier");
  198. kfree(msgr);
  199. return -EFAULT;
  200. }
  201. irq_index += 1;
  202. } else {
  203. msgr->irq = 0;
  204. }
  205. mpic_msgrs[reg_number] = msgr;
  206. mpic_msgr_disable(msgr);
  207. dev_info(&dev->dev, "Register %d initialized: irq %d\n",
  208. reg_number, msgr->irq);
  209. }
  210. return 0;
  211. }
  212. static const struct of_device_id mpic_msgr_ids[] = {
  213. {
  214. .compatible = "fsl,mpic-v3.1-msgr",
  215. .data = NULL,
  216. },
  217. {}
  218. };
  219. static struct platform_driver mpic_msgr_driver = {
  220. .driver = {
  221. .name = "mpic-msgr",
  222. .of_match_table = mpic_msgr_ids,
  223. },
  224. .probe = mpic_msgr_probe,
  225. };
  226. static __init int mpic_msgr_init(void)
  227. {
  228. return platform_driver_register(&mpic_msgr_driver);
  229. }
  230. subsys_initcall(mpic_msgr_init);