fsl_rio.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale MPC85xx/MPC86xx RapidIO support
  4. *
  5. * Copyright 2009 Sysgo AG
  6. * Thomas Moll <thomas.moll@sysgo.com>
  7. * - fixed maintenance access routines, check for aligned access
  8. *
  9. * Copyright 2009 Integrated Device Technology, Inc.
  10. * Alex Bounine <alexandre.bounine@idt.com>
  11. * - Added Port-Write message handling
  12. * - Added Machine Check exception handling
  13. *
  14. * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
  15. * Zhang Wei <wei.zhang@freescale.com>
  16. *
  17. * Copyright 2005 MontaVista Software, Inc.
  18. * Matt Porter <mporter@kernel.crashing.org>
  19. */
  20. #include <linux/init.h>
  21. #include <linux/extable.h>
  22. #include <linux/types.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/device.h>
  26. #include <linux/of_address.h>
  27. #include <linux/of_irq.h>
  28. #include <linux/of_platform.h>
  29. #include <linux/delay.h>
  30. #include <linux/slab.h>
  31. #include <linux/io.h>
  32. #include <linux/uaccess.h>
  33. #include <asm/machdep.h>
  34. #include "fsl_rio.h"
  35. #undef DEBUG_PW /* Port-Write debugging */
  36. #define RIO_PORT1_EDCSR 0x0640
  37. #define RIO_PORT2_EDCSR 0x0680
  38. #define RIO_PORT1_IECSR 0x10130
  39. #define RIO_PORT2_IECSR 0x101B0
  40. #define RIO_GCCSR 0x13c
  41. #define RIO_ESCSR 0x158
  42. #define ESCSR_CLEAR 0x07120204
  43. #define RIO_PORT2_ESCSR 0x178
  44. #define RIO_CCSR 0x15c
  45. #define RIO_LTLEDCSR_IER 0x80000000
  46. #define RIO_LTLEDCSR_PRT 0x01000000
  47. #define IECSR_CLEAR 0x80000000
  48. #define RIO_ISR_AACR 0x10120
  49. #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
  50. #define RIWTAR_TRAD_VAL_SHIFT 12
  51. #define RIWTAR_TRAD_MASK 0x00FFFFFF
  52. #define RIWBAR_BADD_VAL_SHIFT 12
  53. #define RIWBAR_BADD_MASK 0x003FFFFF
  54. #define RIWAR_ENABLE 0x80000000
  55. #define RIWAR_TGINT_LOCAL 0x00F00000
  56. #define RIWAR_RDTYP_NO_SNOOP 0x00040000
  57. #define RIWAR_RDTYP_SNOOP 0x00050000
  58. #define RIWAR_WRTYP_NO_SNOOP 0x00004000
  59. #define RIWAR_WRTYP_SNOOP 0x00005000
  60. #define RIWAR_WRTYP_ALLOC 0x00006000
  61. #define RIWAR_SIZE_MASK 0x0000003F
  62. static DEFINE_SPINLOCK(fsl_rio_config_lock);
  63. #define __fsl_read_rio_config(x, addr, err, op) \
  64. __asm__ __volatile__( \
  65. "1: "op" %1,0(%2)\n" \
  66. " eieio\n" \
  67. "2:\n" \
  68. ".section .fixup,\"ax\"\n" \
  69. "3: li %1,-1\n" \
  70. " li %0,%3\n" \
  71. " b 2b\n" \
  72. ".previous\n" \
  73. EX_TABLE(1b, 3b) \
  74. : "=r" (err), "=r" (x) \
  75. : "b" (addr), "i" (-EFAULT), "0" (err))
  76. void __iomem *rio_regs_win;
  77. void __iomem *rmu_regs_win;
  78. resource_size_t rio_law_start;
  79. struct fsl_rio_dbell *dbell;
  80. struct fsl_rio_pw *pw;
  81. #ifdef CONFIG_E500
  82. int fsl_rio_mcheck_exception(struct pt_regs *regs)
  83. {
  84. const struct exception_table_entry *entry;
  85. unsigned long reason;
  86. if (!rio_regs_win)
  87. return 0;
  88. reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
  89. if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
  90. /* Check if we are prepared to handle this fault */
  91. entry = search_exception_tables(regs->nip);
  92. if (entry) {
  93. pr_debug("RIO: %s - MC Exception handled\n",
  94. __func__);
  95. out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
  96. 0);
  97. regs->msr |= MSR_RI;
  98. regs->nip = extable_fixup(entry);
  99. return 1;
  100. }
  101. }
  102. return 0;
  103. }
  104. EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
  105. #endif
  106. /**
  107. * fsl_local_config_read - Generate a MPC85xx local config space read
  108. * @mport: RapidIO master port info
  109. * @index: ID of RapdiIO interface
  110. * @offset: Offset into configuration space
  111. * @len: Length (in bytes) of the maintenance transaction
  112. * @data: Value to be read into
  113. *
  114. * Generates a MPC85xx local configuration space read. Returns %0 on
  115. * success or %-EINVAL on failure.
  116. */
  117. static int fsl_local_config_read(struct rio_mport *mport,
  118. int index, u32 offset, int len, u32 *data)
  119. {
  120. struct rio_priv *priv = mport->priv;
  121. pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
  122. offset);
  123. *data = in_be32(priv->regs_win + offset);
  124. return 0;
  125. }
  126. /**
  127. * fsl_local_config_write - Generate a MPC85xx local config space write
  128. * @mport: RapidIO master port info
  129. * @index: ID of RapdiIO interface
  130. * @offset: Offset into configuration space
  131. * @len: Length (in bytes) of the maintenance transaction
  132. * @data: Value to be written
  133. *
  134. * Generates a MPC85xx local configuration space write. Returns %0 on
  135. * success or %-EINVAL on failure.
  136. */
  137. static int fsl_local_config_write(struct rio_mport *mport,
  138. int index, u32 offset, int len, u32 data)
  139. {
  140. struct rio_priv *priv = mport->priv;
  141. pr_debug
  142. ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
  143. index, offset, data);
  144. out_be32(priv->regs_win + offset, data);
  145. return 0;
  146. }
  147. /**
  148. * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
  149. * @mport: RapidIO master port info
  150. * @index: ID of RapdiIO interface
  151. * @destid: Destination ID of transaction
  152. * @hopcount: Number of hops to target device
  153. * @offset: Offset into configuration space
  154. * @len: Length (in bytes) of the maintenance transaction
  155. * @val: Location to be read into
  156. *
  157. * Generates a MPC85xx read maintenance transaction. Returns %0 on
  158. * success or %-EINVAL on failure.
  159. */
  160. static int
  161. fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
  162. u8 hopcount, u32 offset, int len, u32 *val)
  163. {
  164. struct rio_priv *priv = mport->priv;
  165. unsigned long flags;
  166. u8 *data;
  167. u32 rval, err = 0;
  168. pr_debug
  169. ("fsl_rio_config_read:"
  170. " index %d destid %d hopcount %d offset %8.8x len %d\n",
  171. index, destid, hopcount, offset, len);
  172. /* 16MB maintenance window possible */
  173. /* allow only aligned access to maintenance registers */
  174. if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
  175. return -EINVAL;
  176. spin_lock_irqsave(&fsl_rio_config_lock, flags);
  177. out_be32(&priv->maint_atmu_regs->rowtar,
  178. (destid << 22) | (hopcount << 12) | (offset >> 12));
  179. out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
  180. data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
  181. switch (len) {
  182. case 1:
  183. __fsl_read_rio_config(rval, data, err, "lbz");
  184. break;
  185. case 2:
  186. __fsl_read_rio_config(rval, data, err, "lhz");
  187. break;
  188. case 4:
  189. __fsl_read_rio_config(rval, data, err, "lwz");
  190. break;
  191. default:
  192. spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
  193. return -EINVAL;
  194. }
  195. if (err) {
  196. pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
  197. err, destid, hopcount, offset);
  198. }
  199. spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
  200. *val = rval;
  201. return err;
  202. }
  203. /**
  204. * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
  205. * @mport: RapidIO master port info
  206. * @index: ID of RapdiIO interface
  207. * @destid: Destination ID of transaction
  208. * @hopcount: Number of hops to target device
  209. * @offset: Offset into configuration space
  210. * @len: Length (in bytes) of the maintenance transaction
  211. * @val: Value to be written
  212. *
  213. * Generates an MPC85xx write maintenance transaction. Returns %0 on
  214. * success or %-EINVAL on failure.
  215. */
  216. static int
  217. fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
  218. u8 hopcount, u32 offset, int len, u32 val)
  219. {
  220. struct rio_priv *priv = mport->priv;
  221. unsigned long flags;
  222. u8 *data;
  223. int ret = 0;
  224. pr_debug
  225. ("fsl_rio_config_write:"
  226. " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
  227. index, destid, hopcount, offset, len, val);
  228. /* 16MB maintenance windows possible */
  229. /* allow only aligned access to maintenance registers */
  230. if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
  231. return -EINVAL;
  232. spin_lock_irqsave(&fsl_rio_config_lock, flags);
  233. out_be32(&priv->maint_atmu_regs->rowtar,
  234. (destid << 22) | (hopcount << 12) | (offset >> 12));
  235. out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
  236. data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
  237. switch (len) {
  238. case 1:
  239. out_8((u8 *) data, val);
  240. break;
  241. case 2:
  242. out_be16((u16 *) data, val);
  243. break;
  244. case 4:
  245. out_be32((u32 *) data, val);
  246. break;
  247. default:
  248. ret = -EINVAL;
  249. }
  250. spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
  251. return ret;
  252. }
  253. static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
  254. {
  255. int i;
  256. /* close inbound windows */
  257. for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
  258. out_be32(&priv->inb_atmu_regs[i].riwar, 0);
  259. }
  260. int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
  261. u64 rstart, u64 size, u32 flags)
  262. {
  263. struct rio_priv *priv = mport->priv;
  264. u32 base_size;
  265. unsigned int base_size_log;
  266. u64 win_start, win_end;
  267. u32 riwar;
  268. int i;
  269. if ((size & (size - 1)) != 0 || size > 0x400000000ULL)
  270. return -EINVAL;
  271. base_size_log = ilog2(size);
  272. base_size = 1 << base_size_log;
  273. /* check if addresses are aligned with the window size */
  274. if (lstart & (base_size - 1))
  275. return -EINVAL;
  276. if (rstart & (base_size - 1))
  277. return -EINVAL;
  278. /* check for conflicting ranges */
  279. for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
  280. riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
  281. if ((riwar & RIWAR_ENABLE) == 0)
  282. continue;
  283. win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
  284. << RIWBAR_BADD_VAL_SHIFT;
  285. win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
  286. if (rstart < win_end && (rstart + size) > win_start)
  287. return -EINVAL;
  288. }
  289. /* find unused atmu */
  290. for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
  291. riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
  292. if ((riwar & RIWAR_ENABLE) == 0)
  293. break;
  294. }
  295. if (i >= RIO_INB_ATMU_COUNT)
  296. return -ENOMEM;
  297. out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
  298. out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
  299. out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
  300. RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
  301. return 0;
  302. }
  303. void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
  304. {
  305. u32 win_start_shift, base_start_shift;
  306. struct rio_priv *priv = mport->priv;
  307. u32 riwar, riwtar;
  308. int i;
  309. /* skip default window */
  310. base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
  311. for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
  312. riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
  313. if ((riwar & RIWAR_ENABLE) == 0)
  314. continue;
  315. riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
  316. win_start_shift = riwtar & RIWTAR_TRAD_MASK;
  317. if (win_start_shift == base_start_shift) {
  318. out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
  319. return;
  320. }
  321. }
  322. }
  323. void fsl_rio_port_error_handler(int offset)
  324. {
  325. /*XXX: Error recovery is not implemented, we just clear errors */
  326. out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
  327. if (offset == 0) {
  328. out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
  329. out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
  330. out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
  331. } else {
  332. out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
  333. out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
  334. out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
  335. }
  336. }
  337. static inline void fsl_rio_info(struct device *dev, u32 ccsr)
  338. {
  339. const char *str;
  340. if (ccsr & 1) {
  341. /* Serial phy */
  342. switch (ccsr >> 30) {
  343. case 0:
  344. str = "1";
  345. break;
  346. case 1:
  347. str = "4";
  348. break;
  349. default:
  350. str = "Unknown";
  351. break;
  352. }
  353. dev_info(dev, "Hardware port width: %s\n", str);
  354. switch ((ccsr >> 27) & 7) {
  355. case 0:
  356. str = "Single-lane 0";
  357. break;
  358. case 1:
  359. str = "Single-lane 2";
  360. break;
  361. case 2:
  362. str = "Four-lane";
  363. break;
  364. default:
  365. str = "Unknown";
  366. break;
  367. }
  368. dev_info(dev, "Training connection status: %s\n", str);
  369. } else {
  370. /* Parallel phy */
  371. if (!(ccsr & 0x80000000))
  372. dev_info(dev, "Output port operating in 8-bit mode\n");
  373. if (!(ccsr & 0x08000000))
  374. dev_info(dev, "Input port operating in 8-bit mode\n");
  375. }
  376. }
  377. /**
  378. * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
  379. * @dev: platform_device pointer
  380. *
  381. * Initializes MPC85xx RapidIO hardware interface, configures
  382. * master port with system-specific info, and registers the
  383. * master port with the RapidIO subsystem.
  384. */
  385. int fsl_rio_setup(struct platform_device *dev)
  386. {
  387. struct rio_ops *ops;
  388. struct rio_mport *port;
  389. struct rio_priv *priv;
  390. int rc = 0;
  391. const u32 *dt_range, *cell, *port_index;
  392. u32 active_ports = 0;
  393. struct resource regs, rmu_regs;
  394. struct device_node *np, *rmu_node;
  395. int rlen;
  396. u32 ccsr;
  397. u64 range_start, range_size;
  398. int paw, aw, sw;
  399. u32 i;
  400. static int tmp;
  401. struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
  402. if (!dev->dev.of_node) {
  403. dev_err(&dev->dev, "Device OF-Node is NULL");
  404. return -ENODEV;
  405. }
  406. rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
  407. if (rc) {
  408. dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
  409. dev->dev.of_node);
  410. return -EFAULT;
  411. }
  412. dev_info(&dev->dev, "Of-device full name %pOF\n",
  413. dev->dev.of_node);
  414. dev_info(&dev->dev, "Regs: %pR\n", &regs);
  415. rio_regs_win = ioremap(regs.start, resource_size(&regs));
  416. if (!rio_regs_win) {
  417. dev_err(&dev->dev, "Unable to map rio register window\n");
  418. rc = -ENOMEM;
  419. goto err_rio_regs;
  420. }
  421. ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
  422. if (!ops) {
  423. rc = -ENOMEM;
  424. goto err_ops;
  425. }
  426. ops->lcread = fsl_local_config_read;
  427. ops->lcwrite = fsl_local_config_write;
  428. ops->cread = fsl_rio_config_read;
  429. ops->cwrite = fsl_rio_config_write;
  430. ops->dsend = fsl_rio_doorbell_send;
  431. ops->pwenable = fsl_rio_pw_enable;
  432. ops->open_outb_mbox = fsl_open_outb_mbox;
  433. ops->open_inb_mbox = fsl_open_inb_mbox;
  434. ops->close_outb_mbox = fsl_close_outb_mbox;
  435. ops->close_inb_mbox = fsl_close_inb_mbox;
  436. ops->add_outb_message = fsl_add_outb_message;
  437. ops->add_inb_buffer = fsl_add_inb_buffer;
  438. ops->get_inb_message = fsl_get_inb_message;
  439. ops->map_inb = fsl_map_inb_mem;
  440. ops->unmap_inb = fsl_unmap_inb_mem;
  441. rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
  442. if (!rmu_node) {
  443. dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
  444. rc = -ENOENT;
  445. goto err_rmu;
  446. }
  447. rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
  448. if (rc) {
  449. dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
  450. rmu_node);
  451. goto err_rmu;
  452. }
  453. rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
  454. if (!rmu_regs_win) {
  455. dev_err(&dev->dev, "Unable to map rmu register window\n");
  456. rc = -ENOMEM;
  457. goto err_rmu;
  458. }
  459. for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
  460. rmu_np[tmp] = np;
  461. tmp++;
  462. }
  463. /*set up doobell node*/
  464. np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
  465. if (!np) {
  466. dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
  467. rc = -ENODEV;
  468. goto err_dbell;
  469. }
  470. dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
  471. if (!(dbell)) {
  472. dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
  473. rc = -ENOMEM;
  474. goto err_dbell;
  475. }
  476. dbell->dev = &dev->dev;
  477. dbell->bellirq = irq_of_parse_and_map(np, 1);
  478. dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
  479. aw = of_n_addr_cells(np);
  480. dt_range = of_get_property(np, "reg", &rlen);
  481. if (!dt_range) {
  482. pr_err("%pOF: unable to find 'reg' property\n",
  483. np);
  484. rc = -ENOMEM;
  485. goto err_pw;
  486. }
  487. range_start = of_read_number(dt_range, aw);
  488. dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
  489. (u32)range_start);
  490. /*set up port write node*/
  491. np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
  492. if (!np) {
  493. dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
  494. rc = -ENODEV;
  495. goto err_pw;
  496. }
  497. pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
  498. if (!(pw)) {
  499. dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
  500. rc = -ENOMEM;
  501. goto err_pw;
  502. }
  503. pw->dev = &dev->dev;
  504. pw->pwirq = irq_of_parse_and_map(np, 0);
  505. dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
  506. aw = of_n_addr_cells(np);
  507. dt_range = of_get_property(np, "reg", &rlen);
  508. if (!dt_range) {
  509. pr_err("%pOF: unable to find 'reg' property\n",
  510. np);
  511. rc = -ENOMEM;
  512. goto err;
  513. }
  514. range_start = of_read_number(dt_range, aw);
  515. pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
  516. /*set up ports node*/
  517. for_each_child_of_node(dev->dev.of_node, np) {
  518. port_index = of_get_property(np, "cell-index", NULL);
  519. if (!port_index) {
  520. dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n",
  521. np);
  522. continue;
  523. }
  524. dt_range = of_get_property(np, "ranges", &rlen);
  525. if (!dt_range) {
  526. dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n",
  527. np);
  528. continue;
  529. }
  530. /* Get node address wide */
  531. cell = of_get_property(np, "#address-cells", NULL);
  532. if (cell)
  533. aw = *cell;
  534. else
  535. aw = of_n_addr_cells(np);
  536. /* Get node size wide */
  537. cell = of_get_property(np, "#size-cells", NULL);
  538. if (cell)
  539. sw = *cell;
  540. else
  541. sw = of_n_size_cells(np);
  542. /* Get parent address wide wide */
  543. paw = of_n_addr_cells(np);
  544. range_start = of_read_number(dt_range + aw, paw);
  545. range_size = of_read_number(dt_range + aw + paw, sw);
  546. dev_info(&dev->dev, "%pOF: LAW start 0x%016llx, size 0x%016llx.\n",
  547. np, range_start, range_size);
  548. port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
  549. if (!port)
  550. continue;
  551. rc = rio_mport_initialize(port);
  552. if (rc) {
  553. kfree(port);
  554. continue;
  555. }
  556. i = *port_index - 1;
  557. port->index = (unsigned char)i;
  558. priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
  559. if (!priv) {
  560. dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
  561. kfree(port);
  562. continue;
  563. }
  564. INIT_LIST_HEAD(&port->dbells);
  565. port->iores.start = range_start;
  566. port->iores.end = port->iores.start + range_size - 1;
  567. port->iores.flags = IORESOURCE_MEM;
  568. port->iores.name = "rio_io_win";
  569. if (request_resource(&iomem_resource, &port->iores) < 0) {
  570. dev_err(&dev->dev, "RIO: Error requesting master port region"
  571. " 0x%016llx-0x%016llx\n",
  572. (u64)port->iores.start, (u64)port->iores.end);
  573. kfree(priv);
  574. kfree(port);
  575. continue;
  576. }
  577. sprintf(port->name, "RIO mport %d", i);
  578. priv->dev = &dev->dev;
  579. port->dev.parent = &dev->dev;
  580. port->ops = ops;
  581. port->priv = priv;
  582. port->phys_efptr = 0x100;
  583. port->phys_rmap = 1;
  584. priv->regs_win = rio_regs_win;
  585. ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
  586. /* Checking the port training status */
  587. if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
  588. dev_err(&dev->dev, "Port %d is not ready. "
  589. "Try to restart connection...\n", i);
  590. /* Disable ports */
  591. out_be32(priv->regs_win
  592. + RIO_CCSR + i*0x20, 0);
  593. /* Set 1x lane */
  594. setbits32(priv->regs_win
  595. + RIO_CCSR + i*0x20, 0x02000000);
  596. /* Enable ports */
  597. setbits32(priv->regs_win
  598. + RIO_CCSR + i*0x20, 0x00600000);
  599. msleep(100);
  600. if (in_be32((priv->regs_win
  601. + RIO_ESCSR + i*0x20)) & 1) {
  602. dev_err(&dev->dev,
  603. "Port %d restart failed.\n", i);
  604. release_resource(&port->iores);
  605. kfree(priv);
  606. kfree(port);
  607. continue;
  608. }
  609. dev_info(&dev->dev, "Port %d restart success!\n", i);
  610. }
  611. fsl_rio_info(&dev->dev, ccsr);
  612. port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
  613. & RIO_PEF_CTLS) >> 4;
  614. dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
  615. port->sys_size ? 65536 : 256);
  616. if (port->host_deviceid >= 0)
  617. out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
  618. RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
  619. else
  620. out_be32(priv->regs_win + RIO_GCCSR,
  621. RIO_PORT_GEN_MASTER);
  622. priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
  623. + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
  624. RIO_ATMU_REGS_PORT2_OFFSET));
  625. priv->maint_atmu_regs = priv->atmu_regs + 1;
  626. priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
  627. (priv->regs_win +
  628. ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
  629. RIO_INB_ATMU_REGS_PORT2_OFFSET));
  630. /* Set to receive packets with any dest ID */
  631. out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80),
  632. RIO_ISR_AACR_AA);
  633. /* Configure maintenance transaction window */
  634. out_be32(&priv->maint_atmu_regs->rowbar,
  635. port->iores.start >> 12);
  636. out_be32(&priv->maint_atmu_regs->rowar,
  637. 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
  638. priv->maint_win = ioremap(port->iores.start,
  639. RIO_MAINT_WIN_SIZE);
  640. rio_law_start = range_start;
  641. fsl_rio_setup_rmu(port, rmu_np[i]);
  642. fsl_rio_inbound_mem_init(priv);
  643. dbell->mport[i] = port;
  644. pw->mport[i] = port;
  645. if (rio_register_mport(port)) {
  646. release_resource(&port->iores);
  647. kfree(priv);
  648. kfree(port);
  649. continue;
  650. }
  651. active_ports++;
  652. }
  653. if (!active_ports) {
  654. rc = -ENOLINK;
  655. goto err;
  656. }
  657. fsl_rio_doorbell_init(dbell);
  658. fsl_rio_port_write_init(pw);
  659. return 0;
  660. err:
  661. kfree(pw);
  662. pw = NULL;
  663. err_pw:
  664. kfree(dbell);
  665. dbell = NULL;
  666. err_dbell:
  667. iounmap(rmu_regs_win);
  668. rmu_regs_win = NULL;
  669. err_rmu:
  670. kfree(ops);
  671. err_ops:
  672. iounmap(rio_regs_win);
  673. rio_regs_win = NULL;
  674. err_rio_regs:
  675. return rc;
  676. }
  677. /* The probe function for RapidIO peer-to-peer network.
  678. */
  679. static int fsl_of_rio_rpn_probe(struct platform_device *dev)
  680. {
  681. printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n",
  682. dev->dev.of_node);
  683. return fsl_rio_setup(dev);
  684. };
  685. static const struct of_device_id fsl_of_rio_rpn_ids[] = {
  686. {
  687. .compatible = "fsl,srio",
  688. },
  689. {},
  690. };
  691. static struct platform_driver fsl_of_rio_rpn_driver = {
  692. .driver = {
  693. .name = "fsl-of-rio",
  694. .of_match_table = fsl_of_rio_rpn_ids,
  695. },
  696. .probe = fsl_of_rio_rpn_probe,
  697. };
  698. static __init int fsl_of_rio_rpn_init(void)
  699. {
  700. return platform_driver_register(&fsl_of_rio_rpn_driver);
  701. }
  702. subsys_initcall(fsl_of_rio_rpn_init);