fsl_pci.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MPC83xx/85xx/86xx PCI/PCIE support routing.
  4. *
  5. * Copyright 2007-2012 Freescale Semiconductor, Inc.
  6. * Copyright 2008-2009 MontaVista Software, Inc.
  7. *
  8. * Initial author: Xianghua Xiao <x.xiao@freescale.com>
  9. * Recode: ZHANG WEI <wei.zhang@freescale.com>
  10. * Rewrite the routing for Frescale PCI and PCI Express
  11. * Roy Zang <tie-fei.zang@freescale.com>
  12. * MPC83xx PCI-Express support:
  13. * Tony Li <tony.li@freescale.com>
  14. * Anton Vorontsov <avorontsov@ru.mvista.com>
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/pci.h>
  18. #include <linux/delay.h>
  19. #include <linux/string.h>
  20. #include <linux/fsl/edac.h>
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/memblock.h>
  24. #include <linux/log2.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/slab.h>
  27. #include <linux/suspend.h>
  28. #include <linux/syscore_ops.h>
  29. #include <linux/uaccess.h>
  30. #include <asm/io.h>
  31. #include <asm/prom.h>
  32. #include <asm/pci-bridge.h>
  33. #include <asm/ppc-pci.h>
  34. #include <asm/machdep.h>
  35. #include <asm/mpc85xx.h>
  36. #include <asm/disassemble.h>
  37. #include <asm/ppc-opcode.h>
  38. #include <asm/swiotlb.h>
  39. #include <sysdev/fsl_soc.h>
  40. #include <sysdev/fsl_pci.h>
  41. static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
  42. static void quirk_fsl_pcie_early(struct pci_dev *dev)
  43. {
  44. u8 hdr_type;
  45. /* if we aren't a PCIe don't bother */
  46. if (!pci_is_pcie(dev))
  47. return;
  48. /* if we aren't in host mode don't bother */
  49. pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
  50. if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
  51. return;
  52. dev->class = PCI_CLASS_BRIDGE_PCI << 8;
  53. fsl_pcie_bus_fixup = 1;
  54. return;
  55. }
  56. static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
  57. int, int, u32 *);
  58. static int fsl_pcie_check_link(struct pci_controller *hose)
  59. {
  60. u32 val = 0;
  61. if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
  62. if (hose->ops->read == fsl_indirect_read_config)
  63. __indirect_read_config(hose, hose->first_busno, 0,
  64. PCIE_LTSSM, 4, &val);
  65. else
  66. early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
  67. if (val < PCIE_LTSSM_L0)
  68. return 1;
  69. } else {
  70. struct ccsr_pci __iomem *pci = hose->private_data;
  71. /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
  72. val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
  73. >> PEX_CSR0_LTSSM_SHIFT;
  74. if (val != PEX_CSR0_LTSSM_L0)
  75. return 1;
  76. }
  77. return 0;
  78. }
  79. static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
  80. int offset, int len, u32 *val)
  81. {
  82. struct pci_controller *hose = pci_bus_to_host(bus);
  83. if (fsl_pcie_check_link(hose))
  84. hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
  85. else
  86. hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
  87. return indirect_read_config(bus, devfn, offset, len, val);
  88. }
  89. #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
  90. static struct pci_ops fsl_indirect_pcie_ops =
  91. {
  92. .read = fsl_indirect_read_config,
  93. .write = indirect_write_config,
  94. };
  95. static u64 pci64_dma_offset;
  96. #ifdef CONFIG_SWIOTLB
  97. static void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev)
  98. {
  99. struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  100. pdev->dev.bus_dma_limit =
  101. hose->dma_window_base_cur + hose->dma_window_size - 1;
  102. }
  103. static void setup_swiotlb_ops(struct pci_controller *hose)
  104. {
  105. if (ppc_swiotlb_enable)
  106. hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb;
  107. }
  108. #else
  109. static inline void setup_swiotlb_ops(struct pci_controller *hose) {}
  110. #endif
  111. static void fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
  112. {
  113. /*
  114. * Fix up PCI devices that are able to DMA to the large inbound
  115. * mapping that allows addressing any RAM address from across PCI.
  116. */
  117. if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) {
  118. dev->bus_dma_limit = 0;
  119. dev->archdata.dma_offset = pci64_dma_offset;
  120. }
  121. }
  122. static int setup_one_atmu(struct ccsr_pci __iomem *pci,
  123. unsigned int index, const struct resource *res,
  124. resource_size_t offset)
  125. {
  126. resource_size_t pci_addr = res->start - offset;
  127. resource_size_t phys_addr = res->start;
  128. resource_size_t size = resource_size(res);
  129. u32 flags = 0x80044000; /* enable & mem R/W */
  130. unsigned int i;
  131. pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
  132. (u64)res->start, (u64)size);
  133. if (res->flags & IORESOURCE_PREFETCH)
  134. flags |= 0x10000000; /* enable relaxed ordering */
  135. for (i = 0; size > 0; i++) {
  136. unsigned int bits = min_t(u32, ilog2(size),
  137. __ffs(pci_addr | phys_addr));
  138. if (index + i >= 5)
  139. return -1;
  140. out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
  141. out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
  142. out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
  143. out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
  144. pci_addr += (resource_size_t)1U << bits;
  145. phys_addr += (resource_size_t)1U << bits;
  146. size -= (resource_size_t)1U << bits;
  147. }
  148. return i;
  149. }
  150. static bool is_kdump(void)
  151. {
  152. struct device_node *node;
  153. node = of_find_node_by_type(NULL, "memory");
  154. if (!node) {
  155. WARN_ON_ONCE(1);
  156. return false;
  157. }
  158. return of_property_read_bool(node, "linux,usable-memory");
  159. }
  160. /* atmu setup for fsl pci/pcie controller */
  161. static void setup_pci_atmu(struct pci_controller *hose)
  162. {
  163. struct ccsr_pci __iomem *pci = hose->private_data;
  164. int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
  165. u64 mem, sz, paddr_hi = 0;
  166. u64 offset = 0, paddr_lo = ULLONG_MAX;
  167. u32 pcicsrbar = 0, pcicsrbar_sz;
  168. u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
  169. PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  170. const u64 *reg;
  171. int len;
  172. bool setup_inbound;
  173. /*
  174. * If this is kdump, we don't want to trigger a bunch of PCI
  175. * errors by closing the window on in-flight DMA.
  176. *
  177. * We still run most of the function's logic so that things like
  178. * hose->dma_window_size still get set.
  179. */
  180. setup_inbound = !is_kdump();
  181. if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) {
  182. /*
  183. * BSC9132 Rev1.0 has an issue where all the PEX inbound
  184. * windows have implemented the default target value as 0xf
  185. * for CCSR space.In all Freescale legacy devices the target
  186. * of 0xf is reserved for local memory space. 9132 Rev1.0
  187. * now has local mempry space mapped to target 0x0 instead of
  188. * 0xf. Hence adding a workaround to remove the target 0xf
  189. * defined for memory space from Inbound window attributes.
  190. */
  191. piwar &= ~PIWAR_TGI_LOCAL;
  192. }
  193. if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
  194. if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
  195. win_idx = 2;
  196. start_idx = 0;
  197. end_idx = 3;
  198. }
  199. }
  200. /* Disable all windows (except powar0 since it's ignored) */
  201. for(i = 1; i < 5; i++)
  202. out_be32(&pci->pow[i].powar, 0);
  203. if (setup_inbound) {
  204. for (i = start_idx; i < end_idx; i++)
  205. out_be32(&pci->piw[i].piwar, 0);
  206. }
  207. /* Setup outbound MEM window */
  208. for(i = 0, j = 1; i < 3; i++) {
  209. if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
  210. continue;
  211. paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
  212. paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
  213. /* We assume all memory resources have the same offset */
  214. offset = hose->mem_offset[i];
  215. n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
  216. if (n < 0 || j >= 5) {
  217. pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
  218. hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
  219. } else
  220. j += n;
  221. }
  222. /* Setup outbound IO window */
  223. if (hose->io_resource.flags & IORESOURCE_IO) {
  224. if (j >= 5) {
  225. pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
  226. } else {
  227. pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
  228. "phy base 0x%016llx.\n",
  229. (u64)hose->io_resource.start,
  230. (u64)resource_size(&hose->io_resource),
  231. (u64)hose->io_base_phys);
  232. out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
  233. out_be32(&pci->pow[j].potear, 0);
  234. out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
  235. /* Enable, IO R/W */
  236. out_be32(&pci->pow[j].powar, 0x80088000
  237. | (ilog2(hose->io_resource.end
  238. - hose->io_resource.start + 1) - 1));
  239. }
  240. }
  241. /* convert to pci address space */
  242. paddr_hi -= offset;
  243. paddr_lo -= offset;
  244. if (paddr_hi == paddr_lo) {
  245. pr_err("%pOF: No outbound window space\n", hose->dn);
  246. return;
  247. }
  248. if (paddr_lo == 0) {
  249. pr_err("%pOF: No space for inbound window\n", hose->dn);
  250. return;
  251. }
  252. /* setup PCSRBAR/PEXCSRBAR */
  253. early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
  254. early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
  255. pcicsrbar_sz = ~pcicsrbar_sz + 1;
  256. if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
  257. (paddr_lo > 0x100000000ull))
  258. pcicsrbar = 0x100000000ull - pcicsrbar_sz;
  259. else
  260. pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
  261. early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
  262. paddr_lo = min(paddr_lo, (u64)pcicsrbar);
  263. pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar);
  264. /* Setup inbound mem window */
  265. mem = memblock_end_of_DRAM();
  266. pr_info("%s: end of DRAM %llx\n", __func__, mem);
  267. /*
  268. * The msi-address-64 property, if it exists, indicates the physical
  269. * address of the MSIIR register. Normally, this register is located
  270. * inside CCSR, so the ATMU that covers all of CCSR is used. But if
  271. * this property exists, then we normally need to create a new ATMU
  272. * for it. For now, however, we cheat. The only entity that creates
  273. * this property is the Freescale hypervisor, and the address is
  274. * specified in the partition configuration. Typically, the address
  275. * is located in the page immediately after the end of DDR. If so, we
  276. * can avoid allocating a new ATMU by extending the DDR ATMU by one
  277. * page.
  278. */
  279. reg = of_get_property(hose->dn, "msi-address-64", &len);
  280. if (reg && (len == sizeof(u64))) {
  281. u64 address = be64_to_cpup(reg);
  282. if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
  283. pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn);
  284. mem += PAGE_SIZE;
  285. } else {
  286. /* TODO: Create a new ATMU for MSIIR */
  287. pr_warn("%pOF: msi-address-64 address of %llx is "
  288. "unsupported\n", hose->dn, address);
  289. }
  290. }
  291. sz = min(mem, paddr_lo);
  292. mem_log = ilog2(sz);
  293. /* PCIe can overmap inbound & outbound since RX & TX are separated */
  294. if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
  295. /* Size window to exact size if power-of-two or one size up */
  296. if ((1ull << mem_log) != mem) {
  297. mem_log++;
  298. if ((1ull << mem_log) > mem)
  299. pr_info("%pOF: Setting PCI inbound window "
  300. "greater than memory size\n", hose->dn);
  301. }
  302. piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
  303. if (setup_inbound) {
  304. /* Setup inbound memory window */
  305. out_be32(&pci->piw[win_idx].pitar, 0x00000000);
  306. out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
  307. out_be32(&pci->piw[win_idx].piwar, piwar);
  308. }
  309. win_idx--;
  310. hose->dma_window_base_cur = 0x00000000;
  311. hose->dma_window_size = (resource_size_t)sz;
  312. /*
  313. * if we have >4G of memory setup second PCI inbound window to
  314. * let devices that are 64-bit address capable to work w/o
  315. * SWIOTLB and access the full range of memory
  316. */
  317. if (sz != mem) {
  318. mem_log = ilog2(mem);
  319. /* Size window up if we dont fit in exact power-of-2 */
  320. if ((1ull << mem_log) != mem)
  321. mem_log++;
  322. piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
  323. pci64_dma_offset = 1ULL << mem_log;
  324. if (setup_inbound) {
  325. /* Setup inbound memory window */
  326. out_be32(&pci->piw[win_idx].pitar, 0x00000000);
  327. out_be32(&pci->piw[win_idx].piwbear,
  328. pci64_dma_offset >> 44);
  329. out_be32(&pci->piw[win_idx].piwbar,
  330. pci64_dma_offset >> 12);
  331. out_be32(&pci->piw[win_idx].piwar, piwar);
  332. }
  333. /*
  334. * install our own dma_set_mask handler to fixup dma_ops
  335. * and dma_offset
  336. */
  337. ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
  338. pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn);
  339. }
  340. } else {
  341. u64 paddr = 0;
  342. if (setup_inbound) {
  343. /* Setup inbound memory window */
  344. out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
  345. out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
  346. out_be32(&pci->piw[win_idx].piwar,
  347. (piwar | (mem_log - 1)));
  348. }
  349. win_idx--;
  350. paddr += 1ull << mem_log;
  351. sz -= 1ull << mem_log;
  352. if (sz) {
  353. mem_log = ilog2(sz);
  354. piwar |= (mem_log - 1);
  355. if (setup_inbound) {
  356. out_be32(&pci->piw[win_idx].pitar,
  357. paddr >> 12);
  358. out_be32(&pci->piw[win_idx].piwbar,
  359. paddr >> 12);
  360. out_be32(&pci->piw[win_idx].piwar, piwar);
  361. }
  362. win_idx--;
  363. paddr += 1ull << mem_log;
  364. }
  365. hose->dma_window_base_cur = 0x00000000;
  366. hose->dma_window_size = (resource_size_t)paddr;
  367. }
  368. if (hose->dma_window_size < mem) {
  369. #ifdef CONFIG_SWIOTLB
  370. ppc_swiotlb_enable = 1;
  371. #else
  372. pr_err("%pOF: ERROR: Memory size exceeds PCI ATMU ability to "
  373. "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
  374. hose->dn);
  375. #endif
  376. /* adjusting outbound windows could reclaim space in mem map */
  377. if (paddr_hi < 0xffffffffull)
  378. pr_warn("%pOF: WARNING: Outbound window cfg leaves "
  379. "gaps in memory map. Adjusting the memory map "
  380. "could reduce unnecessary bounce buffering.\n",
  381. hose->dn);
  382. pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn,
  383. (u64)hose->dma_window_size);
  384. }
  385. }
  386. static void __init setup_pci_cmd(struct pci_controller *hose)
  387. {
  388. u16 cmd;
  389. int cap_x;
  390. early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
  391. cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
  392. | PCI_COMMAND_IO;
  393. early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
  394. cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
  395. if (cap_x) {
  396. int pci_x_cmd = cap_x + PCI_X_CMD;
  397. cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
  398. | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
  399. early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
  400. } else {
  401. early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
  402. }
  403. }
  404. void fsl_pcibios_fixup_bus(struct pci_bus *bus)
  405. {
  406. struct pci_controller *hose = pci_bus_to_host(bus);
  407. int i, is_pcie = 0, no_link;
  408. /* The root complex bridge comes up with bogus resources,
  409. * we copy the PHB ones in.
  410. *
  411. * With the current generic PCI code, the PHB bus no longer
  412. * has bus->resource[0..4] set, so things are a bit more
  413. * tricky.
  414. */
  415. if (fsl_pcie_bus_fixup)
  416. is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
  417. no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
  418. if (bus->parent == hose->bus && (is_pcie || no_link)) {
  419. for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
  420. struct resource *res = bus->resource[i];
  421. struct resource *par;
  422. if (!res)
  423. continue;
  424. if (i == 0)
  425. par = &hose->io_resource;
  426. else if (i < 4)
  427. par = &hose->mem_resources[i-1];
  428. else par = NULL;
  429. res->start = par ? par->start : 0;
  430. res->end = par ? par->end : 0;
  431. res->flags = par ? par->flags : 0;
  432. }
  433. }
  434. }
  435. int fsl_add_bridge(struct platform_device *pdev, int is_primary)
  436. {
  437. int len;
  438. struct pci_controller *hose;
  439. struct resource rsrc;
  440. const int *bus_range;
  441. u8 hdr_type, progif;
  442. struct device_node *dev;
  443. struct ccsr_pci __iomem *pci;
  444. u16 temp;
  445. u32 svr = mfspr(SPRN_SVR);
  446. dev = pdev->dev.of_node;
  447. if (!of_device_is_available(dev)) {
  448. pr_warn("%pOF: disabled\n", dev);
  449. return -ENODEV;
  450. }
  451. pr_debug("Adding PCI host bridge %pOF\n", dev);
  452. /* Fetch host bridge registers address */
  453. if (of_address_to_resource(dev, 0, &rsrc)) {
  454. printk(KERN_WARNING "Can't get pci register base!");
  455. return -ENOMEM;
  456. }
  457. /* Get bus range if any */
  458. bus_range = of_get_property(dev, "bus-range", &len);
  459. if (bus_range == NULL || len < 2 * sizeof(int))
  460. printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
  461. " bus 0\n", dev);
  462. pci_add_flags(PCI_REASSIGN_ALL_BUS);
  463. hose = pcibios_alloc_controller(dev);
  464. if (!hose)
  465. return -ENOMEM;
  466. /* set platform device as the parent */
  467. hose->parent = &pdev->dev;
  468. hose->first_busno = bus_range ? bus_range[0] : 0x0;
  469. hose->last_busno = bus_range ? bus_range[1] : 0xff;
  470. pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
  471. (u64)rsrc.start, (u64)resource_size(&rsrc));
  472. pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
  473. if (!hose->private_data)
  474. goto no_bridge;
  475. setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
  476. PPC_INDIRECT_TYPE_BIG_ENDIAN);
  477. if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
  478. hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
  479. if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
  480. /* use fsl_indirect_read_config for PCIe */
  481. hose->ops = &fsl_indirect_pcie_ops;
  482. /* For PCIE read HEADER_TYPE to identify controller mode */
  483. early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
  484. if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
  485. goto no_bridge;
  486. } else {
  487. /* For PCI read PROG to identify controller mode */
  488. early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
  489. if ((progif & 1) &&
  490. !of_property_read_bool(dev, "fsl,pci-agent-force-enum"))
  491. goto no_bridge;
  492. }
  493. setup_pci_cmd(hose);
  494. /* check PCI express link status */
  495. if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
  496. hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
  497. PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
  498. if (fsl_pcie_check_link(hose))
  499. hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
  500. } else {
  501. /*
  502. * Set PBFR(PCI Bus Function Register)[10] = 1 to
  503. * disable the combining of crossing cacheline
  504. * boundary requests into one burst transaction.
  505. * PCI-X operation is not affected.
  506. * Fix erratum PCI 5 on MPC8548
  507. */
  508. #define PCI_BUS_FUNCTION 0x44
  509. #define PCI_BUS_FUNCTION_MDS 0x400 /* Master disable streaming */
  510. if (((SVR_SOC_VER(svr) == SVR_8543) ||
  511. (SVR_SOC_VER(svr) == SVR_8545) ||
  512. (SVR_SOC_VER(svr) == SVR_8547) ||
  513. (SVR_SOC_VER(svr) == SVR_8548)) &&
  514. !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
  515. early_read_config_word(hose, 0, 0,
  516. PCI_BUS_FUNCTION, &temp);
  517. temp |= PCI_BUS_FUNCTION_MDS;
  518. early_write_config_word(hose, 0, 0,
  519. PCI_BUS_FUNCTION, temp);
  520. }
  521. }
  522. printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
  523. "Firmware bus number: %d->%d\n",
  524. (unsigned long long)rsrc.start, hose->first_busno,
  525. hose->last_busno);
  526. pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
  527. hose, hose->cfg_addr, hose->cfg_data);
  528. /* Interpret the "ranges" property */
  529. /* This also maps the I/O region and sets isa_io/mem_base */
  530. pci_process_bridge_OF_ranges(hose, dev, is_primary);
  531. /* Setup PEX window registers */
  532. setup_pci_atmu(hose);
  533. /* Set up controller operations */
  534. setup_swiotlb_ops(hose);
  535. return 0;
  536. no_bridge:
  537. iounmap(hose->private_data);
  538. /* unmap cfg_data & cfg_addr separately if not on same page */
  539. if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
  540. ((unsigned long)hose->cfg_addr & PAGE_MASK))
  541. iounmap(hose->cfg_data);
  542. iounmap(hose->cfg_addr);
  543. pcibios_free_controller(hose);
  544. return -ENODEV;
  545. }
  546. #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
  547. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
  548. quirk_fsl_pcie_early);
  549. #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
  550. struct mpc83xx_pcie_priv {
  551. void __iomem *cfg_type0;
  552. void __iomem *cfg_type1;
  553. u32 dev_base;
  554. };
  555. struct pex_inbound_window {
  556. u32 ar;
  557. u32 tar;
  558. u32 barl;
  559. u32 barh;
  560. };
  561. /*
  562. * With the convention of u-boot, the PCIE outbound window 0 serves
  563. * as configuration transactions outbound.
  564. */
  565. #define PEX_OUTWIN0_BAR 0xCA4
  566. #define PEX_OUTWIN0_TAL 0xCA8
  567. #define PEX_OUTWIN0_TAH 0xCAC
  568. #define PEX_RC_INWIN_BASE 0xE60
  569. #define PEX_RCIWARn_EN 0x1
  570. static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
  571. {
  572. struct pci_controller *hose = pci_bus_to_host(bus);
  573. if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
  574. return PCIBIOS_DEVICE_NOT_FOUND;
  575. /*
  576. * Workaround for the HW bug: for Type 0 configure transactions the
  577. * PCI-E controller does not check the device number bits and just
  578. * assumes that the device number bits are 0.
  579. */
  580. if (bus->number == hose->first_busno ||
  581. bus->primary == hose->first_busno) {
  582. if (devfn & 0xf8)
  583. return PCIBIOS_DEVICE_NOT_FOUND;
  584. }
  585. if (ppc_md.pci_exclude_device) {
  586. if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
  587. return PCIBIOS_DEVICE_NOT_FOUND;
  588. }
  589. return PCIBIOS_SUCCESSFUL;
  590. }
  591. static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
  592. unsigned int devfn, int offset)
  593. {
  594. struct pci_controller *hose = pci_bus_to_host(bus);
  595. struct mpc83xx_pcie_priv *pcie = hose->dn->data;
  596. u32 dev_base = bus->number << 24 | devfn << 16;
  597. int ret;
  598. ret = mpc83xx_pcie_exclude_device(bus, devfn);
  599. if (ret)
  600. return NULL;
  601. offset &= 0xfff;
  602. /* Type 0 */
  603. if (bus->number == hose->first_busno)
  604. return pcie->cfg_type0 + offset;
  605. if (pcie->dev_base == dev_base)
  606. goto mapped;
  607. out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
  608. pcie->dev_base = dev_base;
  609. mapped:
  610. return pcie->cfg_type1 + offset;
  611. }
  612. static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
  613. int offset, int len, u32 val)
  614. {
  615. struct pci_controller *hose = pci_bus_to_host(bus);
  616. /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
  617. if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
  618. val &= 0xffffff00;
  619. return pci_generic_config_write(bus, devfn, offset, len, val);
  620. }
  621. static struct pci_ops mpc83xx_pcie_ops = {
  622. .map_bus = mpc83xx_pcie_remap_cfg,
  623. .read = pci_generic_config_read,
  624. .write = mpc83xx_pcie_write_config,
  625. };
  626. static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
  627. struct resource *reg)
  628. {
  629. struct mpc83xx_pcie_priv *pcie;
  630. u32 cfg_bar;
  631. int ret = -ENOMEM;
  632. pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
  633. if (!pcie)
  634. return ret;
  635. pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
  636. if (!pcie->cfg_type0)
  637. goto err0;
  638. cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
  639. if (!cfg_bar) {
  640. /* PCI-E isn't configured. */
  641. ret = -ENODEV;
  642. goto err1;
  643. }
  644. pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
  645. if (!pcie->cfg_type1)
  646. goto err1;
  647. WARN_ON(hose->dn->data);
  648. hose->dn->data = pcie;
  649. hose->ops = &mpc83xx_pcie_ops;
  650. hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
  651. out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
  652. out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
  653. if (fsl_pcie_check_link(hose))
  654. hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
  655. return 0;
  656. err1:
  657. iounmap(pcie->cfg_type0);
  658. err0:
  659. kfree(pcie);
  660. return ret;
  661. }
  662. int __init mpc83xx_add_bridge(struct device_node *dev)
  663. {
  664. int ret;
  665. int len;
  666. struct pci_controller *hose;
  667. struct resource rsrc_reg;
  668. struct resource rsrc_cfg;
  669. const int *bus_range;
  670. int primary;
  671. is_mpc83xx_pci = 1;
  672. if (!of_device_is_available(dev)) {
  673. pr_warn("%pOF: disabled by the firmware.\n",
  674. dev);
  675. return -ENODEV;
  676. }
  677. pr_debug("Adding PCI host bridge %pOF\n", dev);
  678. /* Fetch host bridge registers address */
  679. if (of_address_to_resource(dev, 0, &rsrc_reg)) {
  680. printk(KERN_WARNING "Can't get pci register base!\n");
  681. return -ENOMEM;
  682. }
  683. memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
  684. if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
  685. printk(KERN_WARNING
  686. "No pci config register base in dev tree, "
  687. "using default\n");
  688. /*
  689. * MPC83xx supports up to two host controllers
  690. * one at 0x8500 has config space registers at 0x8300
  691. * one at 0x8600 has config space registers at 0x8380
  692. */
  693. if ((rsrc_reg.start & 0xfffff) == 0x8500)
  694. rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
  695. else if ((rsrc_reg.start & 0xfffff) == 0x8600)
  696. rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
  697. }
  698. /*
  699. * Controller at offset 0x8500 is primary
  700. */
  701. if ((rsrc_reg.start & 0xfffff) == 0x8500)
  702. primary = 1;
  703. else
  704. primary = 0;
  705. /* Get bus range if any */
  706. bus_range = of_get_property(dev, "bus-range", &len);
  707. if (bus_range == NULL || len < 2 * sizeof(int)) {
  708. printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
  709. " bus 0\n", dev);
  710. }
  711. pci_add_flags(PCI_REASSIGN_ALL_BUS);
  712. hose = pcibios_alloc_controller(dev);
  713. if (!hose)
  714. return -ENOMEM;
  715. hose->first_busno = bus_range ? bus_range[0] : 0;
  716. hose->last_busno = bus_range ? bus_range[1] : 0xff;
  717. if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
  718. ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
  719. if (ret)
  720. goto err0;
  721. } else {
  722. setup_indirect_pci(hose, rsrc_cfg.start,
  723. rsrc_cfg.start + 4, 0);
  724. }
  725. printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
  726. "Firmware bus number: %d->%d\n",
  727. (unsigned long long)rsrc_reg.start, hose->first_busno,
  728. hose->last_busno);
  729. pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
  730. hose, hose->cfg_addr, hose->cfg_data);
  731. /* Interpret the "ranges" property */
  732. /* This also maps the I/O region and sets isa_io/mem_base */
  733. pci_process_bridge_OF_ranges(hose, dev, primary);
  734. return 0;
  735. err0:
  736. pcibios_free_controller(hose);
  737. return ret;
  738. }
  739. #endif /* CONFIG_PPC_83xx */
  740. u64 fsl_pci_immrbar_base(struct pci_controller *hose)
  741. {
  742. #ifdef CONFIG_PPC_83xx
  743. if (is_mpc83xx_pci) {
  744. struct mpc83xx_pcie_priv *pcie = hose->dn->data;
  745. struct pex_inbound_window *in;
  746. int i;
  747. /* Walk the Root Complex Inbound windows to match IMMR base */
  748. in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
  749. for (i = 0; i < 4; i++) {
  750. /* not enabled, skip */
  751. if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN))
  752. continue;
  753. if (get_immrbase() == in_le32(&in[i].tar))
  754. return (u64)in_le32(&in[i].barh) << 32 |
  755. in_le32(&in[i].barl);
  756. }
  757. printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
  758. }
  759. #endif
  760. #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
  761. if (!is_mpc83xx_pci) {
  762. u32 base;
  763. pci_bus_read_config_dword(hose->bus,
  764. PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
  765. /*
  766. * For PEXCSRBAR, bit 3-0 indicate prefetchable and
  767. * address type. So when getting base address, these
  768. * bits should be masked
  769. */
  770. base &= PCI_BASE_ADDRESS_MEM_MASK;
  771. return base;
  772. }
  773. #endif
  774. return 0;
  775. }
  776. #ifdef CONFIG_E500
  777. static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
  778. {
  779. unsigned int rd, ra, rb, d;
  780. rd = get_rt(inst);
  781. ra = get_ra(inst);
  782. rb = get_rb(inst);
  783. d = get_d(inst);
  784. switch (get_op(inst)) {
  785. case 31:
  786. switch (get_xop(inst)) {
  787. case OP_31_XOP_LWZX:
  788. case OP_31_XOP_LWBRX:
  789. regs->gpr[rd] = 0xffffffff;
  790. break;
  791. case OP_31_XOP_LWZUX:
  792. regs->gpr[rd] = 0xffffffff;
  793. regs->gpr[ra] += regs->gpr[rb];
  794. break;
  795. case OP_31_XOP_LBZX:
  796. regs->gpr[rd] = 0xff;
  797. break;
  798. case OP_31_XOP_LBZUX:
  799. regs->gpr[rd] = 0xff;
  800. regs->gpr[ra] += regs->gpr[rb];
  801. break;
  802. case OP_31_XOP_LHZX:
  803. case OP_31_XOP_LHBRX:
  804. regs->gpr[rd] = 0xffff;
  805. break;
  806. case OP_31_XOP_LHZUX:
  807. regs->gpr[rd] = 0xffff;
  808. regs->gpr[ra] += regs->gpr[rb];
  809. break;
  810. case OP_31_XOP_LHAX:
  811. regs->gpr[rd] = ~0UL;
  812. break;
  813. case OP_31_XOP_LHAUX:
  814. regs->gpr[rd] = ~0UL;
  815. regs->gpr[ra] += regs->gpr[rb];
  816. break;
  817. default:
  818. return 0;
  819. }
  820. break;
  821. case OP_LWZ:
  822. regs->gpr[rd] = 0xffffffff;
  823. break;
  824. case OP_LWZU:
  825. regs->gpr[rd] = 0xffffffff;
  826. regs->gpr[ra] += (s16)d;
  827. break;
  828. case OP_LBZ:
  829. regs->gpr[rd] = 0xff;
  830. break;
  831. case OP_LBZU:
  832. regs->gpr[rd] = 0xff;
  833. regs->gpr[ra] += (s16)d;
  834. break;
  835. case OP_LHZ:
  836. regs->gpr[rd] = 0xffff;
  837. break;
  838. case OP_LHZU:
  839. regs->gpr[rd] = 0xffff;
  840. regs->gpr[ra] += (s16)d;
  841. break;
  842. case OP_LHA:
  843. regs->gpr[rd] = ~0UL;
  844. break;
  845. case OP_LHAU:
  846. regs->gpr[rd] = ~0UL;
  847. regs->gpr[ra] += (s16)d;
  848. break;
  849. default:
  850. return 0;
  851. }
  852. return 1;
  853. }
  854. static int is_in_pci_mem_space(phys_addr_t addr)
  855. {
  856. struct pci_controller *hose;
  857. struct resource *res;
  858. int i;
  859. list_for_each_entry(hose, &hose_list, list_node) {
  860. if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
  861. continue;
  862. for (i = 0; i < 3; i++) {
  863. res = &hose->mem_resources[i];
  864. if ((res->flags & IORESOURCE_MEM) &&
  865. addr >= res->start && addr <= res->end)
  866. return 1;
  867. }
  868. }
  869. return 0;
  870. }
  871. int fsl_pci_mcheck_exception(struct pt_regs *regs)
  872. {
  873. u32 inst;
  874. int ret;
  875. phys_addr_t addr = 0;
  876. /* Let KVM/QEMU deal with the exception */
  877. if (regs->msr & MSR_GS)
  878. return 0;
  879. #ifdef CONFIG_PHYS_64BIT
  880. addr = mfspr(SPRN_MCARU);
  881. addr <<= 32;
  882. #endif
  883. addr += mfspr(SPRN_MCAR);
  884. if (is_in_pci_mem_space(addr)) {
  885. if (user_mode(regs))
  886. ret = copy_from_user_nofault(&inst,
  887. (void __user *)regs->nip, sizeof(inst));
  888. else
  889. ret = get_kernel_nofault(inst, (void *)regs->nip);
  890. if (!ret && mcheck_handle_load(regs, inst)) {
  891. regs->nip += 4;
  892. return 1;
  893. }
  894. }
  895. return 0;
  896. }
  897. #endif
  898. #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
  899. static const struct of_device_id pci_ids[] = {
  900. { .compatible = "fsl,mpc8540-pci", },
  901. { .compatible = "fsl,mpc8548-pcie", },
  902. { .compatible = "fsl,mpc8610-pci", },
  903. { .compatible = "fsl,mpc8641-pcie", },
  904. { .compatible = "fsl,qoriq-pcie", },
  905. { .compatible = "fsl,qoriq-pcie-v2.1", },
  906. { .compatible = "fsl,qoriq-pcie-v2.2", },
  907. { .compatible = "fsl,qoriq-pcie-v2.3", },
  908. { .compatible = "fsl,qoriq-pcie-v2.4", },
  909. { .compatible = "fsl,qoriq-pcie-v3.0", },
  910. /*
  911. * The following entries are for compatibility with older device
  912. * trees.
  913. */
  914. { .compatible = "fsl,p1022-pcie", },
  915. { .compatible = "fsl,p4080-pcie", },
  916. {},
  917. };
  918. struct device_node *fsl_pci_primary;
  919. void fsl_pci_assign_primary(void)
  920. {
  921. struct device_node *np;
  922. /* Callers can specify the primary bus using other means. */
  923. if (fsl_pci_primary)
  924. return;
  925. /* If a PCI host bridge contains an ISA node, it's primary. */
  926. np = of_find_node_by_type(NULL, "isa");
  927. while ((fsl_pci_primary = of_get_parent(np))) {
  928. of_node_put(np);
  929. np = fsl_pci_primary;
  930. if (of_match_node(pci_ids, np) && of_device_is_available(np))
  931. return;
  932. }
  933. /*
  934. * If there's no PCI host bridge with ISA, arbitrarily
  935. * designate one as primary. This can go away once
  936. * various bugs with primary-less systems are fixed.
  937. */
  938. for_each_matching_node(np, pci_ids) {
  939. if (of_device_is_available(np)) {
  940. fsl_pci_primary = np;
  941. of_node_put(np);
  942. return;
  943. }
  944. }
  945. }
  946. #ifdef CONFIG_PM_SLEEP
  947. static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
  948. {
  949. struct pci_controller *hose = dev_id;
  950. struct ccsr_pci __iomem *pci = hose->private_data;
  951. u32 dr;
  952. dr = in_be32(&pci->pex_pme_mes_dr);
  953. if (!dr)
  954. return IRQ_NONE;
  955. out_be32(&pci->pex_pme_mes_dr, dr);
  956. return IRQ_HANDLED;
  957. }
  958. static int fsl_pci_pme_probe(struct pci_controller *hose)
  959. {
  960. struct ccsr_pci __iomem *pci;
  961. struct pci_dev *dev;
  962. int pme_irq;
  963. int res;
  964. u16 pms;
  965. /* Get hose's pci_dev */
  966. dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
  967. /* PME Disable */
  968. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
  969. pms &= ~PCI_PM_CTRL_PME_ENABLE;
  970. pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
  971. pme_irq = irq_of_parse_and_map(hose->dn, 0);
  972. if (!pme_irq) {
  973. dev_err(&dev->dev, "Failed to map PME interrupt.\n");
  974. return -ENXIO;
  975. }
  976. res = devm_request_irq(hose->parent, pme_irq,
  977. fsl_pci_pme_handle,
  978. IRQF_SHARED,
  979. "[PCI] PME", hose);
  980. if (res < 0) {
  981. dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq);
  982. irq_dispose_mapping(pme_irq);
  983. return -ENODEV;
  984. }
  985. pci = hose->private_data;
  986. /* Enable PTOD, ENL23D & EXL23D */
  987. clrbits32(&pci->pex_pme_mes_disr,
  988. PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
  989. out_be32(&pci->pex_pme_mes_ier, 0);
  990. setbits32(&pci->pex_pme_mes_ier,
  991. PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
  992. /* PME Enable */
  993. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
  994. pms |= PCI_PM_CTRL_PME_ENABLE;
  995. pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
  996. return 0;
  997. }
  998. static void send_pme_turnoff_message(struct pci_controller *hose)
  999. {
  1000. struct ccsr_pci __iomem *pci = hose->private_data;
  1001. u32 dr;
  1002. int i;
  1003. /* Send PME_Turn_Off Message Request */
  1004. setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
  1005. /* Wait trun off done */
  1006. for (i = 0; i < 150; i++) {
  1007. dr = in_be32(&pci->pex_pme_mes_dr);
  1008. if (dr) {
  1009. out_be32(&pci->pex_pme_mes_dr, dr);
  1010. break;
  1011. }
  1012. udelay(1000);
  1013. }
  1014. }
  1015. static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
  1016. {
  1017. send_pme_turnoff_message(hose);
  1018. }
  1019. static int fsl_pci_syscore_suspend(void)
  1020. {
  1021. struct pci_controller *hose, *tmp;
  1022. list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  1023. fsl_pci_syscore_do_suspend(hose);
  1024. return 0;
  1025. }
  1026. static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
  1027. {
  1028. struct ccsr_pci __iomem *pci = hose->private_data;
  1029. u32 dr;
  1030. int i;
  1031. /* Send Exit L2 State Message */
  1032. setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
  1033. /* Wait exit done */
  1034. for (i = 0; i < 150; i++) {
  1035. dr = in_be32(&pci->pex_pme_mes_dr);
  1036. if (dr) {
  1037. out_be32(&pci->pex_pme_mes_dr, dr);
  1038. break;
  1039. }
  1040. udelay(1000);
  1041. }
  1042. setup_pci_atmu(hose);
  1043. }
  1044. static void fsl_pci_syscore_resume(void)
  1045. {
  1046. struct pci_controller *hose, *tmp;
  1047. list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  1048. fsl_pci_syscore_do_resume(hose);
  1049. }
  1050. static struct syscore_ops pci_syscore_pm_ops = {
  1051. .suspend = fsl_pci_syscore_suspend,
  1052. .resume = fsl_pci_syscore_resume,
  1053. };
  1054. #endif
  1055. void fsl_pcibios_fixup_phb(struct pci_controller *phb)
  1056. {
  1057. #ifdef CONFIG_PM_SLEEP
  1058. fsl_pci_pme_probe(phb);
  1059. #endif
  1060. }
  1061. static int add_err_dev(struct platform_device *pdev)
  1062. {
  1063. struct platform_device *errdev;
  1064. struct mpc85xx_edac_pci_plat_data pd = {
  1065. .of_node = pdev->dev.of_node
  1066. };
  1067. errdev = platform_device_register_resndata(&pdev->dev,
  1068. "mpc85xx-pci-edac",
  1069. PLATFORM_DEVID_AUTO,
  1070. pdev->resource,
  1071. pdev->num_resources,
  1072. &pd, sizeof(pd));
  1073. return PTR_ERR_OR_ZERO(errdev);
  1074. }
  1075. static int fsl_pci_probe(struct platform_device *pdev)
  1076. {
  1077. struct device_node *node;
  1078. int ret;
  1079. node = pdev->dev.of_node;
  1080. ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
  1081. if (ret)
  1082. return ret;
  1083. ret = add_err_dev(pdev);
  1084. if (ret)
  1085. dev_err(&pdev->dev, "couldn't register error device: %d\n",
  1086. ret);
  1087. return 0;
  1088. }
  1089. static struct platform_driver fsl_pci_driver = {
  1090. .driver = {
  1091. .name = "fsl-pci",
  1092. .of_match_table = pci_ids,
  1093. },
  1094. .probe = fsl_pci_probe,
  1095. };
  1096. static int __init fsl_pci_init(void)
  1097. {
  1098. #ifdef CONFIG_PM_SLEEP
  1099. register_syscore_ops(&pci_syscore_pm_ops);
  1100. #endif
  1101. return platform_driver_register(&fsl_pci_driver);
  1102. }
  1103. arch_initcall(fsl_pci_init);
  1104. #endif