fsl_msi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Tony Li <tony.li@freescale.com>
  6. * Jason Jin <Jason.jin@freescale.com>
  7. *
  8. * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
  9. */
  10. #include <linux/irq.h>
  11. #include <linux/msi.h>
  12. #include <linux/pci.h>
  13. #include <linux/slab.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/seq_file.h>
  17. #include <sysdev/fsl_soc.h>
  18. #include <asm/prom.h>
  19. #include <asm/hw_irq.h>
  20. #include <asm/ppc-pci.h>
  21. #include <asm/mpic.h>
  22. #include <asm/fsl_hcalls.h>
  23. #include "fsl_msi.h"
  24. #include "fsl_pci.h"
  25. #define MSIIR_OFFSET_MASK 0xfffff
  26. #define MSIIR_IBS_SHIFT 0
  27. #define MSIIR_SRS_SHIFT 5
  28. #define MSIIR1_IBS_SHIFT 4
  29. #define MSIIR1_SRS_SHIFT 0
  30. #define MSI_SRS_MASK 0xf
  31. #define MSI_IBS_MASK 0x1f
  32. #define msi_hwirq(msi, msir_index, intr_index) \
  33. ((msir_index) << (msi)->srs_shift | \
  34. ((intr_index) << (msi)->ibs_shift))
  35. static LIST_HEAD(msi_head);
  36. struct fsl_msi_feature {
  37. u32 fsl_pic_ip;
  38. u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
  39. };
  40. struct fsl_msi_cascade_data {
  41. struct fsl_msi *msi_data;
  42. int index;
  43. int virq;
  44. };
  45. static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
  46. {
  47. return in_be32(base + (reg >> 2));
  48. }
  49. /*
  50. * We do not need this actually. The MSIR register has been read once
  51. * in the cascade interrupt. So, this MSI interrupt has been acked
  52. */
  53. static void fsl_msi_end_irq(struct irq_data *d)
  54. {
  55. }
  56. static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
  57. {
  58. struct fsl_msi *msi_data = irqd->domain->host_data;
  59. irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
  60. int cascade_virq, srs;
  61. srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
  62. cascade_virq = msi_data->cascade_array[srs]->virq;
  63. seq_printf(p, " fsl-msi-%d", cascade_virq);
  64. }
  65. static struct irq_chip fsl_msi_chip = {
  66. .irq_mask = pci_msi_mask_irq,
  67. .irq_unmask = pci_msi_unmask_irq,
  68. .irq_ack = fsl_msi_end_irq,
  69. .irq_print_chip = fsl_msi_print_chip,
  70. };
  71. static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
  72. irq_hw_number_t hw)
  73. {
  74. struct fsl_msi *msi_data = h->host_data;
  75. struct irq_chip *chip = &fsl_msi_chip;
  76. irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
  77. irq_set_chip_data(virq, msi_data);
  78. irq_set_chip_and_handler(virq, chip, handle_edge_irq);
  79. return 0;
  80. }
  81. static const struct irq_domain_ops fsl_msi_host_ops = {
  82. .map = fsl_msi_host_map,
  83. };
  84. static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
  85. {
  86. int rc, hwirq;
  87. rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
  88. irq_domain_get_of_node(msi_data->irqhost));
  89. if (rc)
  90. return rc;
  91. /*
  92. * Reserve all the hwirqs
  93. * The available hwirqs will be released in fsl_msi_setup_hwirq()
  94. */
  95. for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
  96. msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
  97. return 0;
  98. }
  99. static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
  100. {
  101. struct msi_desc *entry;
  102. struct fsl_msi *msi_data;
  103. irq_hw_number_t hwirq;
  104. for_each_pci_msi_entry(entry, pdev) {
  105. if (!entry->irq)
  106. continue;
  107. hwirq = virq_to_hw(entry->irq);
  108. msi_data = irq_get_chip_data(entry->irq);
  109. irq_set_msi_desc(entry->irq, NULL);
  110. irq_dispose_mapping(entry->irq);
  111. msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
  112. }
  113. return;
  114. }
  115. static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
  116. struct msi_msg *msg,
  117. struct fsl_msi *fsl_msi_data)
  118. {
  119. struct fsl_msi *msi_data = fsl_msi_data;
  120. struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  121. u64 address; /* Physical address of the MSIIR */
  122. int len;
  123. const __be64 *reg;
  124. /* If the msi-address-64 property exists, then use it */
  125. reg = of_get_property(hose->dn, "msi-address-64", &len);
  126. if (reg && (len == sizeof(u64)))
  127. address = be64_to_cpup(reg);
  128. else
  129. address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
  130. msg->address_lo = lower_32_bits(address);
  131. msg->address_hi = upper_32_bits(address);
  132. /*
  133. * MPIC version 2.0 has erratum PIC1. It causes
  134. * that neither MSI nor MSI-X can work fine.
  135. * This is a workaround to allow MSI-X to function
  136. * properly. It only works for MSI-X, we prevent
  137. * MSI on buggy chips in fsl_setup_msi_irqs().
  138. */
  139. if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
  140. msg->data = __swab32(hwirq);
  141. else
  142. msg->data = hwirq;
  143. pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
  144. (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
  145. (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
  146. }
  147. static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  148. {
  149. struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  150. struct device_node *np;
  151. phandle phandle = 0;
  152. int rc, hwirq = -ENOMEM;
  153. unsigned int virq;
  154. struct msi_desc *entry;
  155. struct msi_msg msg;
  156. struct fsl_msi *msi_data;
  157. if (type == PCI_CAP_ID_MSI) {
  158. /*
  159. * MPIC version 2.0 has erratum PIC1. For now MSI
  160. * could not work. So check to prevent MSI from
  161. * being used on the board with this erratum.
  162. */
  163. list_for_each_entry(msi_data, &msi_head, list)
  164. if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
  165. return -EINVAL;
  166. }
  167. /*
  168. * If the PCI node has an fsl,msi property, then we need to use it
  169. * to find the specific MSI.
  170. */
  171. np = of_parse_phandle(hose->dn, "fsl,msi", 0);
  172. if (np) {
  173. if (of_device_is_compatible(np, "fsl,mpic-msi") ||
  174. of_device_is_compatible(np, "fsl,vmpic-msi") ||
  175. of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
  176. phandle = np->phandle;
  177. else {
  178. dev_err(&pdev->dev,
  179. "node %pOF has an invalid fsl,msi phandle %u\n",
  180. hose->dn, np->phandle);
  181. return -EINVAL;
  182. }
  183. }
  184. for_each_pci_msi_entry(entry, pdev) {
  185. /*
  186. * Loop over all the MSI devices until we find one that has an
  187. * available interrupt.
  188. */
  189. list_for_each_entry(msi_data, &msi_head, list) {
  190. /*
  191. * If the PCI node has an fsl,msi property, then we
  192. * restrict our search to the corresponding MSI node.
  193. * The simplest way is to skip over MSI nodes with the
  194. * wrong phandle. Under the Freescale hypervisor, this
  195. * has the additional benefit of skipping over MSI
  196. * nodes that are not mapped in the PAMU.
  197. */
  198. if (phandle && (phandle != msi_data->phandle))
  199. continue;
  200. hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
  201. if (hwirq >= 0)
  202. break;
  203. }
  204. if (hwirq < 0) {
  205. rc = hwirq;
  206. dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
  207. goto out_free;
  208. }
  209. virq = irq_create_mapping(msi_data->irqhost, hwirq);
  210. if (!virq) {
  211. dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
  212. msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
  213. rc = -ENOSPC;
  214. goto out_free;
  215. }
  216. /* chip_data is msi_data via host->hostdata in host->map() */
  217. irq_set_msi_desc(virq, entry);
  218. fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
  219. pci_write_msi_msg(virq, &msg);
  220. }
  221. return 0;
  222. out_free:
  223. /* free by the caller of this function */
  224. return rc;
  225. }
  226. static irqreturn_t fsl_msi_cascade(int irq, void *data)
  227. {
  228. unsigned int cascade_irq;
  229. struct fsl_msi *msi_data;
  230. int msir_index = -1;
  231. u32 msir_value = 0;
  232. u32 intr_index;
  233. u32 have_shift = 0;
  234. struct fsl_msi_cascade_data *cascade_data = data;
  235. irqreturn_t ret = IRQ_NONE;
  236. msi_data = cascade_data->msi_data;
  237. msir_index = cascade_data->index;
  238. if (msir_index >= NR_MSI_REG_MAX)
  239. cascade_irq = 0;
  240. switch (msi_data->feature & FSL_PIC_IP_MASK) {
  241. case FSL_PIC_IP_MPIC:
  242. msir_value = fsl_msi_read(msi_data->msi_regs,
  243. msir_index * 0x10);
  244. break;
  245. case FSL_PIC_IP_IPIC:
  246. msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
  247. break;
  248. #ifdef CONFIG_EPAPR_PARAVIRT
  249. case FSL_PIC_IP_VMPIC: {
  250. unsigned int ret;
  251. ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
  252. if (ret) {
  253. pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
  254. "irq %u (ret=%u)\n", irq, ret);
  255. msir_value = 0;
  256. }
  257. break;
  258. }
  259. #endif
  260. }
  261. while (msir_value) {
  262. intr_index = ffs(msir_value) - 1;
  263. cascade_irq = irq_linear_revmap(msi_data->irqhost,
  264. msi_hwirq(msi_data, msir_index,
  265. intr_index + have_shift));
  266. if (cascade_irq) {
  267. generic_handle_irq(cascade_irq);
  268. ret = IRQ_HANDLED;
  269. }
  270. have_shift += intr_index + 1;
  271. msir_value = msir_value >> (intr_index + 1);
  272. }
  273. return ret;
  274. }
  275. static int fsl_of_msi_remove(struct platform_device *ofdev)
  276. {
  277. struct fsl_msi *msi = platform_get_drvdata(ofdev);
  278. int virq, i;
  279. if (msi->list.prev != NULL)
  280. list_del(&msi->list);
  281. for (i = 0; i < NR_MSI_REG_MAX; i++) {
  282. if (msi->cascade_array[i]) {
  283. virq = msi->cascade_array[i]->virq;
  284. BUG_ON(!virq);
  285. free_irq(virq, msi->cascade_array[i]);
  286. kfree(msi->cascade_array[i]);
  287. irq_dispose_mapping(virq);
  288. }
  289. }
  290. if (msi->bitmap.bitmap)
  291. msi_bitmap_free(&msi->bitmap);
  292. if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
  293. iounmap(msi->msi_regs);
  294. kfree(msi);
  295. return 0;
  296. }
  297. static struct lock_class_key fsl_msi_irq_class;
  298. static struct lock_class_key fsl_msi_irq_request_class;
  299. static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
  300. int offset, int irq_index)
  301. {
  302. struct fsl_msi_cascade_data *cascade_data = NULL;
  303. int virt_msir, i, ret;
  304. virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
  305. if (!virt_msir) {
  306. dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
  307. __func__, irq_index);
  308. return 0;
  309. }
  310. cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
  311. if (!cascade_data) {
  312. dev_err(&dev->dev, "No memory for MSI cascade data\n");
  313. return -ENOMEM;
  314. }
  315. irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class,
  316. &fsl_msi_irq_request_class);
  317. cascade_data->index = offset;
  318. cascade_data->msi_data = msi;
  319. cascade_data->virq = virt_msir;
  320. msi->cascade_array[irq_index] = cascade_data;
  321. ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD,
  322. "fsl-msi-cascade", cascade_data);
  323. if (ret) {
  324. dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
  325. virt_msir, ret);
  326. return ret;
  327. }
  328. /* Release the hwirqs corresponding to this MSI register */
  329. for (i = 0; i < IRQS_PER_MSI_REG; i++)
  330. msi_bitmap_free_hwirqs(&msi->bitmap,
  331. msi_hwirq(msi, offset, i), 1);
  332. return 0;
  333. }
  334. static const struct of_device_id fsl_of_msi_ids[];
  335. static int fsl_of_msi_probe(struct platform_device *dev)
  336. {
  337. const struct of_device_id *match;
  338. struct fsl_msi *msi;
  339. struct resource res, msiir;
  340. int err, i, j, irq_index, count;
  341. const u32 *p;
  342. const struct fsl_msi_feature *features;
  343. int len;
  344. u32 offset;
  345. struct pci_controller *phb;
  346. match = of_match_device(fsl_of_msi_ids, &dev->dev);
  347. if (!match)
  348. return -EINVAL;
  349. features = match->data;
  350. printk(KERN_DEBUG "Setting up Freescale MSI support\n");
  351. msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
  352. if (!msi) {
  353. dev_err(&dev->dev, "No memory for MSI structure\n");
  354. return -ENOMEM;
  355. }
  356. platform_set_drvdata(dev, msi);
  357. msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
  358. NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
  359. if (msi->irqhost == NULL) {
  360. dev_err(&dev->dev, "No memory for MSI irqhost\n");
  361. err = -ENOMEM;
  362. goto error_out;
  363. }
  364. /*
  365. * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
  366. * property. Instead, we use hypercalls to access the MSI.
  367. */
  368. if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
  369. err = of_address_to_resource(dev->dev.of_node, 0, &res);
  370. if (err) {
  371. dev_err(&dev->dev, "invalid resource for node %pOF\n",
  372. dev->dev.of_node);
  373. goto error_out;
  374. }
  375. msi->msi_regs = ioremap(res.start, resource_size(&res));
  376. if (!msi->msi_regs) {
  377. err = -ENOMEM;
  378. dev_err(&dev->dev, "could not map node %pOF\n",
  379. dev->dev.of_node);
  380. goto error_out;
  381. }
  382. msi->msiir_offset =
  383. features->msiir_offset + (res.start & 0xfffff);
  384. /*
  385. * First read the MSIIR/MSIIR1 offset from dts
  386. * On failure use the hardcode MSIIR offset
  387. */
  388. if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
  389. msi->msiir_offset = features->msiir_offset +
  390. (res.start & MSIIR_OFFSET_MASK);
  391. else
  392. msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
  393. }
  394. msi->feature = features->fsl_pic_ip;
  395. /* For erratum PIC1 on MPIC version 2.0*/
  396. if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC
  397. && (fsl_mpic_primary_get_version() == 0x0200))
  398. msi->feature |= MSI_HW_ERRATA_ENDIAN;
  399. /*
  400. * Remember the phandle, so that we can match with any PCI nodes
  401. * that have an "fsl,msi" property.
  402. */
  403. msi->phandle = dev->dev.of_node->phandle;
  404. err = fsl_msi_init_allocator(msi);
  405. if (err) {
  406. dev_err(&dev->dev, "Error allocating MSI bitmap\n");
  407. goto error_out;
  408. }
  409. p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
  410. if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
  411. of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
  412. msi->srs_shift = MSIIR1_SRS_SHIFT;
  413. msi->ibs_shift = MSIIR1_IBS_SHIFT;
  414. if (p)
  415. dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
  416. __func__);
  417. for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
  418. irq_index++) {
  419. err = fsl_msi_setup_hwirq(msi, dev,
  420. irq_index, irq_index);
  421. if (err)
  422. goto error_out;
  423. }
  424. } else {
  425. static const u32 all_avail[] =
  426. { 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
  427. msi->srs_shift = MSIIR_SRS_SHIFT;
  428. msi->ibs_shift = MSIIR_IBS_SHIFT;
  429. if (p && len % (2 * sizeof(u32)) != 0) {
  430. dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
  431. __func__);
  432. err = -EINVAL;
  433. goto error_out;
  434. }
  435. if (!p) {
  436. p = all_avail;
  437. len = sizeof(all_avail);
  438. }
  439. for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
  440. if (p[i * 2] % IRQS_PER_MSI_REG ||
  441. p[i * 2 + 1] % IRQS_PER_MSI_REG) {
  442. pr_warn("%s: %pOF: msi available range of %u at %u is not IRQ-aligned\n",
  443. __func__, dev->dev.of_node,
  444. p[i * 2 + 1], p[i * 2]);
  445. err = -EINVAL;
  446. goto error_out;
  447. }
  448. offset = p[i * 2] / IRQS_PER_MSI_REG;
  449. count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
  450. for (j = 0; j < count; j++, irq_index++) {
  451. err = fsl_msi_setup_hwirq(msi, dev, offset + j,
  452. irq_index);
  453. if (err)
  454. goto error_out;
  455. }
  456. }
  457. }
  458. list_add_tail(&msi->list, &msi_head);
  459. /*
  460. * Apply the MSI ops to all the controllers.
  461. * It doesn't hurt to reassign the same ops,
  462. * but bail out if we find another MSI driver.
  463. */
  464. list_for_each_entry(phb, &hose_list, list_node) {
  465. if (!phb->controller_ops.setup_msi_irqs) {
  466. phb->controller_ops.setup_msi_irqs = fsl_setup_msi_irqs;
  467. phb->controller_ops.teardown_msi_irqs = fsl_teardown_msi_irqs;
  468. } else if (phb->controller_ops.setup_msi_irqs != fsl_setup_msi_irqs) {
  469. dev_err(&dev->dev, "Different MSI driver already installed!\n");
  470. err = -ENODEV;
  471. goto error_out;
  472. }
  473. }
  474. return 0;
  475. error_out:
  476. fsl_of_msi_remove(dev);
  477. return err;
  478. }
  479. static const struct fsl_msi_feature mpic_msi_feature = {
  480. .fsl_pic_ip = FSL_PIC_IP_MPIC,
  481. .msiir_offset = 0x140,
  482. };
  483. static const struct fsl_msi_feature ipic_msi_feature = {
  484. .fsl_pic_ip = FSL_PIC_IP_IPIC,
  485. .msiir_offset = 0x38,
  486. };
  487. static const struct fsl_msi_feature vmpic_msi_feature = {
  488. .fsl_pic_ip = FSL_PIC_IP_VMPIC,
  489. .msiir_offset = 0,
  490. };
  491. static const struct of_device_id fsl_of_msi_ids[] = {
  492. {
  493. .compatible = "fsl,mpic-msi",
  494. .data = &mpic_msi_feature,
  495. },
  496. {
  497. .compatible = "fsl,mpic-msi-v4.3",
  498. .data = &mpic_msi_feature,
  499. },
  500. {
  501. .compatible = "fsl,ipic-msi",
  502. .data = &ipic_msi_feature,
  503. },
  504. #ifdef CONFIG_EPAPR_PARAVIRT
  505. {
  506. .compatible = "fsl,vmpic-msi",
  507. .data = &vmpic_msi_feature,
  508. },
  509. {
  510. .compatible = "fsl,vmpic-msi-v4.3",
  511. .data = &vmpic_msi_feature,
  512. },
  513. #endif
  514. {}
  515. };
  516. static struct platform_driver fsl_of_msi_driver = {
  517. .driver = {
  518. .name = "fsl-msi",
  519. .of_match_table = fsl_of_msi_ids,
  520. },
  521. .probe = fsl_of_msi_probe,
  522. .remove = fsl_of_msi_remove,
  523. };
  524. static __init int fsl_of_msi_init(void)
  525. {
  526. return platform_driver_register(&fsl_of_msi_driver);
  527. }
  528. subsys_initcall(fsl_of_msi_init);