fsl_85xx_l2ctlr.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
  4. *
  5. * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
  6. *
  7. * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/of_platform.h>
  12. #include <asm/io.h>
  13. #include "fsl_85xx_cache_ctlr.h"
  14. static char *sram_size;
  15. static char *sram_offset;
  16. struct mpc85xx_l2ctlr __iomem *l2ctlr;
  17. static int get_cache_sram_params(struct sram_parameters *sram_params)
  18. {
  19. unsigned long long addr;
  20. unsigned int size;
  21. if (!sram_size || (kstrtouint(sram_size, 0, &size) < 0))
  22. return -EINVAL;
  23. if (!sram_offset || (kstrtoull(sram_offset, 0, &addr) < 0))
  24. return -EINVAL;
  25. sram_params->sram_offset = addr;
  26. sram_params->sram_size = size;
  27. return 0;
  28. }
  29. static int __init get_size_from_cmdline(char *str)
  30. {
  31. if (!str)
  32. return 0;
  33. sram_size = str;
  34. return 1;
  35. }
  36. static int __init get_offset_from_cmdline(char *str)
  37. {
  38. if (!str)
  39. return 0;
  40. sram_offset = str;
  41. return 1;
  42. }
  43. __setup("cache-sram-size=", get_size_from_cmdline);
  44. __setup("cache-sram-offset=", get_offset_from_cmdline);
  45. static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
  46. {
  47. long rval;
  48. unsigned int rem;
  49. unsigned char ways;
  50. const unsigned int *prop;
  51. unsigned int l2cache_size;
  52. struct sram_parameters sram_params;
  53. if (!dev->dev.of_node) {
  54. dev_err(&dev->dev, "Device's OF-node is NULL\n");
  55. return -EINVAL;
  56. }
  57. prop = of_get_property(dev->dev.of_node, "cache-size", NULL);
  58. if (!prop) {
  59. dev_err(&dev->dev, "Missing L2 cache-size\n");
  60. return -EINVAL;
  61. }
  62. l2cache_size = *prop;
  63. if (get_cache_sram_params(&sram_params))
  64. return 0; /* fall back to L2 cache only */
  65. rem = l2cache_size % sram_params.sram_size;
  66. ways = LOCK_WAYS_FULL * sram_params.sram_size / l2cache_size;
  67. if (rem || (ways & (ways - 1))) {
  68. dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
  69. return -EINVAL;
  70. }
  71. l2ctlr = of_iomap(dev->dev.of_node, 0);
  72. if (!l2ctlr) {
  73. dev_err(&dev->dev, "Can't map L2 controller\n");
  74. return -EINVAL;
  75. }
  76. /*
  77. * Write bits[0-17] to srbar0
  78. */
  79. out_be32(&l2ctlr->srbar0,
  80. lower_32_bits(sram_params.sram_offset) & L2SRAM_BAR_MSK_LO18);
  81. /*
  82. * Write bits[18-21] to srbare0
  83. */
  84. #ifdef CONFIG_PHYS_64BIT
  85. out_be32(&l2ctlr->srbarea0,
  86. upper_32_bits(sram_params.sram_offset) & L2SRAM_BARE_MSK_HI4);
  87. #endif
  88. clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
  89. switch (ways) {
  90. case LOCK_WAYS_EIGHTH:
  91. setbits32(&l2ctlr->ctl,
  92. L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
  93. break;
  94. case LOCK_WAYS_TWO_EIGHTH:
  95. setbits32(&l2ctlr->ctl,
  96. L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
  97. break;
  98. case LOCK_WAYS_HALF:
  99. setbits32(&l2ctlr->ctl,
  100. L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
  101. break;
  102. case LOCK_WAYS_FULL:
  103. default:
  104. setbits32(&l2ctlr->ctl,
  105. L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
  106. break;
  107. }
  108. eieio();
  109. rval = instantiate_cache_sram(dev, sram_params);
  110. if (rval < 0) {
  111. dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
  112. iounmap(l2ctlr);
  113. return -EINVAL;
  114. }
  115. return 0;
  116. }
  117. static int mpc85xx_l2ctlr_of_remove(struct platform_device *dev)
  118. {
  119. BUG_ON(!l2ctlr);
  120. iounmap(l2ctlr);
  121. remove_cache_sram(dev);
  122. dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");
  123. return 0;
  124. }
  125. static const struct of_device_id mpc85xx_l2ctlr_of_match[] = {
  126. {
  127. .compatible = "fsl,p2020-l2-cache-controller",
  128. },
  129. {
  130. .compatible = "fsl,p2010-l2-cache-controller",
  131. },
  132. {
  133. .compatible = "fsl,p1020-l2-cache-controller",
  134. },
  135. {
  136. .compatible = "fsl,p1011-l2-cache-controller",
  137. },
  138. {
  139. .compatible = "fsl,p1013-l2-cache-controller",
  140. },
  141. {
  142. .compatible = "fsl,p1022-l2-cache-controller",
  143. },
  144. {
  145. .compatible = "fsl,mpc8548-l2-cache-controller",
  146. },
  147. { .compatible = "fsl,mpc8544-l2-cache-controller",},
  148. { .compatible = "fsl,mpc8572-l2-cache-controller",},
  149. { .compatible = "fsl,mpc8536-l2-cache-controller",},
  150. { .compatible = "fsl,p1021-l2-cache-controller",},
  151. { .compatible = "fsl,p1012-l2-cache-controller",},
  152. { .compatible = "fsl,p1025-l2-cache-controller",},
  153. { .compatible = "fsl,p1016-l2-cache-controller",},
  154. { .compatible = "fsl,p1024-l2-cache-controller",},
  155. { .compatible = "fsl,p1015-l2-cache-controller",},
  156. { .compatible = "fsl,p1010-l2-cache-controller",},
  157. { .compatible = "fsl,bsc9131-l2-cache-controller",},
  158. {},
  159. };
  160. static struct platform_driver mpc85xx_l2ctlr_of_platform_driver = {
  161. .driver = {
  162. .name = "fsl-l2ctlr",
  163. .of_match_table = mpc85xx_l2ctlr_of_match,
  164. },
  165. .probe = mpc85xx_l2ctlr_of_probe,
  166. .remove = mpc85xx_l2ctlr_of_remove,
  167. };
  168. static __init int mpc85xx_l2ctlr_of_init(void)
  169. {
  170. return platform_driver_register(&mpc85xx_l2ctlr_of_platform_driver);
  171. }
  172. static void __exit mpc85xx_l2ctlr_of_exit(void)
  173. {
  174. platform_driver_unregister(&mpc85xx_l2ctlr_of_platform_driver);
  175. }
  176. subsys_initcall(mpc85xx_l2ctlr_of_init);
  177. module_exit(mpc85xx_l2ctlr_of_exit);
  178. MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
  179. MODULE_LICENSE("GPL v2");