cpm_common.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Common CPM code
  4. *
  5. * Author: Scott Wood <scottwood@freescale.com>
  6. *
  7. * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
  8. *
  9. * Some parts derived from commproc.c/cpm2_common.c, which is:
  10. * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
  11. * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
  12. * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
  13. * 2006 (c) MontaVista Software, Inc.
  14. * Vitaly Bordug <vbordug@ru.mvista.com>
  15. */
  16. #include <linux/init.h>
  17. #include <linux/of_device.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/export.h>
  20. #include <linux/of.h>
  21. #include <linux/of_address.h>
  22. #include <linux/slab.h>
  23. #include <asm/udbg.h>
  24. #include <asm/io.h>
  25. #include <asm/cpm.h>
  26. #include <asm/fixmap.h>
  27. #include <soc/fsl/qe/qe.h>
  28. #include <mm/mmu_decl.h>
  29. #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
  30. #include <linux/of_gpio.h>
  31. #endif
  32. static int __init cpm_init(void)
  33. {
  34. struct device_node *np;
  35. np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
  36. if (!np)
  37. np = of_find_compatible_node(NULL, NULL, "fsl,cpm2");
  38. if (!np)
  39. return -ENODEV;
  40. cpm_muram_init();
  41. of_node_put(np);
  42. return 0;
  43. }
  44. subsys_initcall(cpm_init);
  45. #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
  46. static u32 __iomem *cpm_udbg_txdesc;
  47. static u8 __iomem *cpm_udbg_txbuf;
  48. static void udbg_putc_cpm(char c)
  49. {
  50. if (c == '\n')
  51. udbg_putc_cpm('\r');
  52. while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
  53. ;
  54. out_8(cpm_udbg_txbuf, c);
  55. out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
  56. }
  57. void __init udbg_init_cpm(void)
  58. {
  59. #ifdef CONFIG_PPC_8xx
  60. mmu_mapin_immr();
  61. cpm_udbg_txdesc = (u32 __iomem __force *)
  62. (CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE +
  63. VIRT_IMMR_BASE);
  64. cpm_udbg_txbuf = (u8 __iomem __force *)
  65. (in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE +
  66. VIRT_IMMR_BASE);
  67. #else
  68. cpm_udbg_txdesc = (u32 __iomem __force *)
  69. CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
  70. cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
  71. #endif
  72. if (cpm_udbg_txdesc) {
  73. #ifdef CONFIG_CPM2
  74. setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
  75. #endif
  76. udbg_putc = udbg_putc_cpm;
  77. }
  78. }
  79. #endif
  80. #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
  81. struct cpm2_ioports {
  82. u32 dir, par, sor, odr, dat;
  83. u32 res[3];
  84. };
  85. struct cpm2_gpio32_chip {
  86. struct of_mm_gpio_chip mm_gc;
  87. spinlock_t lock;
  88. /* shadowed data register to clear/set bits safely */
  89. u32 cpdata;
  90. };
  91. static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
  92. {
  93. struct cpm2_gpio32_chip *cpm2_gc =
  94. container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
  95. struct cpm2_ioports __iomem *iop = mm_gc->regs;
  96. cpm2_gc->cpdata = in_be32(&iop->dat);
  97. }
  98. static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
  99. {
  100. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  101. struct cpm2_ioports __iomem *iop = mm_gc->regs;
  102. u32 pin_mask;
  103. pin_mask = 1 << (31 - gpio);
  104. return !!(in_be32(&iop->dat) & pin_mask);
  105. }
  106. static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
  107. int value)
  108. {
  109. struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
  110. struct cpm2_ioports __iomem *iop = mm_gc->regs;
  111. if (value)
  112. cpm2_gc->cpdata |= pin_mask;
  113. else
  114. cpm2_gc->cpdata &= ~pin_mask;
  115. out_be32(&iop->dat, cpm2_gc->cpdata);
  116. }
  117. static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
  118. {
  119. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  120. struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
  121. unsigned long flags;
  122. u32 pin_mask = 1 << (31 - gpio);
  123. spin_lock_irqsave(&cpm2_gc->lock, flags);
  124. __cpm2_gpio32_set(mm_gc, pin_mask, value);
  125. spin_unlock_irqrestore(&cpm2_gc->lock, flags);
  126. }
  127. static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
  128. {
  129. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  130. struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
  131. struct cpm2_ioports __iomem *iop = mm_gc->regs;
  132. unsigned long flags;
  133. u32 pin_mask = 1 << (31 - gpio);
  134. spin_lock_irqsave(&cpm2_gc->lock, flags);
  135. setbits32(&iop->dir, pin_mask);
  136. __cpm2_gpio32_set(mm_gc, pin_mask, val);
  137. spin_unlock_irqrestore(&cpm2_gc->lock, flags);
  138. return 0;
  139. }
  140. static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
  141. {
  142. struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  143. struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
  144. struct cpm2_ioports __iomem *iop = mm_gc->regs;
  145. unsigned long flags;
  146. u32 pin_mask = 1 << (31 - gpio);
  147. spin_lock_irqsave(&cpm2_gc->lock, flags);
  148. clrbits32(&iop->dir, pin_mask);
  149. spin_unlock_irqrestore(&cpm2_gc->lock, flags);
  150. return 0;
  151. }
  152. int cpm2_gpiochip_add32(struct device *dev)
  153. {
  154. struct device_node *np = dev->of_node;
  155. struct cpm2_gpio32_chip *cpm2_gc;
  156. struct of_mm_gpio_chip *mm_gc;
  157. struct gpio_chip *gc;
  158. cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
  159. if (!cpm2_gc)
  160. return -ENOMEM;
  161. spin_lock_init(&cpm2_gc->lock);
  162. mm_gc = &cpm2_gc->mm_gc;
  163. gc = &mm_gc->gc;
  164. mm_gc->save_regs = cpm2_gpio32_save_regs;
  165. gc->ngpio = 32;
  166. gc->direction_input = cpm2_gpio32_dir_in;
  167. gc->direction_output = cpm2_gpio32_dir_out;
  168. gc->get = cpm2_gpio32_get;
  169. gc->set = cpm2_gpio32_set;
  170. gc->parent = dev;
  171. gc->owner = THIS_MODULE;
  172. return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc);
  173. }
  174. #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */